PCI 9080 Data Book Version 1.06 January 2000 Website: http://www.plxtech.com Email: apps@plxtech.com Phone: 408 774-9060 800 759-3735 Fax: 408 774-2169 (c) 2000 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products. PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc. Other brands and names are property of their respective owners. Order Number: 9080-SIL-DB-P1-1.06 Printed in the USA, January 2000 CONTENTS FIGURES XI TABLES XIII TIMING DIAGRAMS .......................................................................................................................................................... XVII PREFACE XXI REVISION HISTORY ........................................................................................................................................................ XXIII FEATURES 1 1. GENERAL DESCRIPTION ..............................................................................................................................................3 1.1 COMPANY AND PRODUCT BACKGROUND ......................................................................................................................3 1.2 PCI 9080 APPLICATIONS ............................................................................................................................................3 1.2.1 PCI Adapter Cards .............................................................................................................................................3 1.2.2 Embedded Systems ...........................................................................................................................................3 1.3 MAJOR FEATURES .......................................................................................................................................................3 1.4 COMPATIBILITY WITH PCI 9060, PCI 9060ES, AND PCI 9060SD.................................................................................4 1.4.1 Pin Compatibility.................................................................................................................................................4 1.4.2 Register Compatibility ........................................................................................................................................4 1.5 2. COMPARISON OF PCI 9060, PCI 9060ES, PCI 9060SD, AND PCI 9080 .....................................................................5 BUS OPERATION ...........................................................................................................................................................7 2.1 PCI BUS CYCLES ........................................................................................................................................................7 2.1.1 PCI Target Command Codes .............................................................................................................................7 2.1.2 PCI Master Command Codes ............................................................................................................................7 2.1.2.1 DMA Master Command Codes .......................................................................................................................................7 2.1.2.2 Direct Local-to-PCI Command Codes .............................................................................................................................7 2.1.3 2.2 PCI Arbitration ....................................................................................................................................................7 LOCAL BUS CYCLES ....................................................................................................................................................8 2.2.1 Local Bus Arbitration ..........................................................................................................................................8 2.2.2 Local Bus Direct Master .....................................................................................................................................8 2.2.3 Local Bus Direct Slave .......................................................................................................................................8 2.2.3.1 Ready/Wait State Control................................................................................................................................................8 2.2.3.1.1 Wait State--Local Bus ..............................................................................................................................................9 2.2.3.1.2 Wait State--PCI Bus.................................................................................................................................................9 2.2.3.2 Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode).....................................................................9 2.2.3.2.1 Burst Mode................................................................................................................................................................9 2.2.3.2.2 Continuous Burst Mode (Bterm "Burst Terminate" Mode).......................................................................................10 2.2.3.2.3 Partial Lword Accesses...........................................................................................................................................10 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved v Contents 3. 2.2.3.3 Recovery States............................................................................................................................................................10 2.2.3.4 Local Bus Read Accesses ............................................................................................................................................10 2.2.3.5 Local Bus Write Accesses.............................................................................................................................................10 2.2.3.6 Direct Slave Write Accesses--8- and 16-Bit Buses ......................................................................................................10 2.2.3.7 Local Bus Data Parity....................................................................................................................................................10 2.2.3.8 Local Bus Big/Little Endian ...........................................................................................................................................11 2.2.3.8.1 32-Bit Local Bus--Big Endian Mode .......................................................................................................................11 2.2.3.8.2 16-Bit Local Bus--Big Endian Mode .......................................................................................................................11 2.2.3.8.3 8-Bit Local Bus--Big Endian Mode .........................................................................................................................12 FUNCTIONAL DESCRIPTION ......................................................................................................................................13 3.1 RESET ......................................................................................................................................................................13 3.1.1 PCI Bus Input RST# .........................................................................................................................................13 3.1.2 Software Reset LRESETo#..............................................................................................................................13 3.1.3 Local Bus Input LRESETi#...............................................................................................................................13 3.1.4 Local Bus Output LRESETo#...........................................................................................................................13 3.1.5 Software Reset.................................................................................................................................................13 3.2 PCI 9080 INITIALIZATION...........................................................................................................................................13 3.2.1 Serial EEPROM Initialization............................................................................................................................14 3.2.2 Local Initialization .............................................................................................................................................14 3.3 SERIAL EEPROM .....................................................................................................................................................14 3.3.1 Short Serial EEPROM Load .............................................................................................................................15 3.3.2 Long Serial EEPROM Load..............................................................................................................................15 3.3.3 Extra Long Serial EEPROM Load ....................................................................................................................17 3.3.4 Recommended Serial EEPROMs ....................................................................................................................17 3.3.5 Programming the Serial EEPROM ...................................................................................................................17 3.4 INTERNAL REGISTER ACCESS ....................................................................................................................................17 3.4.1 PCI Bus Access to Internal Registers ..............................................................................................................18 3.4.2 Local Bus Access to Internal Registers............................................................................................................18 3.5 RESPONSE TO FULL AND EMPTY FIFOS .....................................................................................................................19 3.6 DIRECT DATA TRANSFER MODES ...............................................................................................................................19 3.6.1 vi Direct Master Operation (Local Master to PCI Target) ....................................................................................20 3.6.1.1 Decode..........................................................................................................................................................................20 3.6.1.2 FIFOs ............................................................................................................................................................................20 3.6.1.3 Memory Access ............................................................................................................................................................21 3.6.1.4 IO/CFG Access .............................................................................................................................................................21 3.6.1.5 I/O .................................................................................................................................................................................21 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Contents 3.6.1.6 CFG (PCI Configuration Type 0 or Type 1 Cycles) .......................................................................................................21 3.6.1.7 Direct Bus Master Lock .................................................................................................................................................22 3.6.1.8 Master/Target Abort ......................................................................................................................................................22 3.6.1.9 Write and Invalidate ......................................................................................................................................................22 3.6.1.9.1 DMA Write and Invalidate .......................................................................................................................................23 3.6.1.9.2 Direct Master Write and Invalidate ..........................................................................................................................23 3.6.2 3.6.2.1 PCI 2.1 Mode ................................................................................................................................................................25 3.6.2.2 PCI-to-Local Address Mapping .....................................................................................................................................27 3.6.2.2.1 Byte Enables...........................................................................................................................................................27 3.6.2.2.2 Local Bus Initialization Software .............................................................................................................................27 3.6.2.2.3 PCI Initialization Software .......................................................................................................................................27 3.6.2.3 Deadlock and BREQo ...................................................................................................................................................29 3.6.2.3.1 Backoff....................................................................................................................................................................30 3.6.2.3.2 Software/Hardware Solution for Systems without Backoff Capability......................................................................30 3.6.2.3.3 Software Solutions to Deadlock ..............................................................................................................................30 3.6.2.4 3.6.3 3.7 Direct Slave Operation (PCI Master to Local Bus Access) ..............................................................................25 Direct Slave Lock ..........................................................................................................................................................30 Direct Slave Priority..........................................................................................................................................31 DMA OPERATION .....................................................................................................................................................31 3.7.1 Non-Chaining Mode DMA ................................................................................................................................31 3.7.2 Chaining Mode DMA ........................................................................................................................................33 3.7.3 DMA Data Transfers.........................................................................................................................................34 3.7.3.1 Local-to-PCI Bus DMA Transfer....................................................................................................................................35 3.7.3.2 PCI-to-Local Bus DMA Transfer....................................................................................................................................35 3.7.3.3 Unaligned Transfers......................................................................................................................................................36 3.7.4 Demand Mode DMA.........................................................................................................................................36 3.7.5 DMA Priority .....................................................................................................................................................36 3.7.6 DMA Arbitration ................................................................................................................................................36 3.7.6.1 End of Transfer (EOT0# or EOT1#) Input .....................................................................................................................36 3.7.6.2 DMA Abort ....................................................................................................................................................................37 3.7.6.3 Local Latency and Pause Timers ..................................................................................................................................37 3.8 VENDOR AND DEVICE ID REGISTERS..........................................................................................................................37 3.9 DOORBELL REGISTERS ..............................................................................................................................................37 3.10 MAILBOX REGISTERS.................................................................................................................................................37 3.11 USER INPUT AND OUTPUT ..........................................................................................................................................37 3.12 INTERRUPTS .............................................................................................................................................................38 3.12.1 PCI Interrupts (INTA#)......................................................................................................................................38 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved vii Contents 3.12.1.1 Local Interrupt Input ..................................................................................................................................................38 3.12.1.2 Master/Target Abort Interrupt....................................................................................................................................38 3.12.2 Local interrupts (LINTo#)..................................................................................................................................39 3.12.2.1 Local-to-PCI Doorbell Interrupt .................................................................................................................................39 3.12.2.2 PCI-to-Local Doorbell Interrupt .................................................................................................................................39 3.12.2.3 Built-In Self Test Interrupt (BIST) ..............................................................................................................................39 3.12.2.4 DMA Channel 0/1 Interrupts......................................................................................................................................40 3.12.3 PCI SERR# (PCI NMI) .....................................................................................................................................40 3.12.4 Local LSERR# (Local NMI) ..............................................................................................................................40 3.13 I2O COMPATIBLE MESSAGE UNIT ...............................................................................................................................40 3.13.1 Inbound Messages ...........................................................................................................................................41 3.13.2 Outbound Messages ........................................................................................................................................41 3.13.3 I2O Pointer Management ..................................................................................................................................41 3.13.4 Inbound Free List FIFO ....................................................................................................................................42 3.13.5 Inbound Post List FIFO ....................................................................................................................................44 3.13.6 Outbound Post List FIFO..................................................................................................................................44 3.13.7 Outbound Post Queue......................................................................................................................................44 3.13.8 Inbound Free Queue ........................................................................................................................................44 3.13.9 Outbound Free List FIFO .................................................................................................................................44 3.13.10 I2O Enable Sequence .......................................................................................................................................45 4. REGISTERS...................................................................................................................................................................47 4.1 NEW REGISTER DEFINITIONS SUMMARY .....................................................................................................................47 4.1.1 Register Differences between PCI 9080 and PCI 9060, PCI 9060ES, and PCI 9060SD................................48 4.2 REGISTER ADDRESS MAPPING ...................................................................................................................................54 4.3 PCI CONFIGURATION REGISTERS ..............................................................................................................................59 4.4 LOCAL CONFIGURATION REGISTERS...........................................................................................................................66 4.5 RUNTIME REGISTERS ................................................................................................................................................75 4.6 DMA REGISTERS ......................................................................................................................................................80 4.7 MESSAGING QUEUE REGISTERS ................................................................................................................................85 5. PIN DESCRIPTION........................................................................................................................................................89 5.1 PIN SUMMARY ...........................................................................................................................................................89 5.2 PIN OUT COMMON TO ALL BUS MODES ......................................................................................................................90 5.3 C BUS MODE PIN OUT ..............................................................................................................................................94 5.4 J BUS MODE PIN OUT ...............................................................................................................................................96 5.5 S BUS MODE PIN OUT...............................................................................................................................................98 6. viii ELECTRICAL SPECIFICATIONS ...............................................................................................................................101 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Contents 7. 8. 6.1 GENERAL SPECIFICATIONS ......................................................................................................................................101 6.2 LOCAL INPUTS.........................................................................................................................................................103 6.3 LOCAL OUTPUTS .....................................................................................................................................................104 PACKAGE, SIGNAL, AND PIN OUT SPECS.............................................................................................................107 7.1 PACKAGE MECHANICAL DIMENSIONS........................................................................................................................107 7.2 TYPICAL PCI BUS MASTER ADAPTER .......................................................................................................................108 7.3 PCI 9080 PIN OUT .................................................................................................................................................109 TIMING DIAGRAMS ....................................................................................................................................................111 8.1 INITIALIZATION .........................................................................................................................................................111 8.2 C MODE .................................................................................................................................................................115 8.2.1 C Mode Direct Slave ......................................................................................................................................115 8.2.2 C Mode Direct Master ....................................................................................................................................137 8.2.3 C Mode DMA ..................................................................................................................................................159 8.3 J MODE ..................................................................................................................................................................170 8.3.1 J Mode Direct Slave .......................................................................................................................................170 8.3.2 J Mode Direct Master .....................................................................................................................................177 8.3.3 J Mode DMA...................................................................................................................................................180 8.4 S MODE..................................................................................................................................................................184 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved ix This page intentionally left blank. x PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved FIGURES Typical Adapter Block Diagram ...............................................................................................................................................1 PCI 9080 Internal Block Diagram ............................................................................................................................................2 Figure 2-1. Wait States............................................................................................................................................................8 Figure 2-2. Big/Little Endian--32-Bit Local Bus ....................................................................................................................11 Figure 2-3. Big/Little Endian--16-Bit Local Bus ....................................................................................................................12 Figure 2-4. Big/Little Endian--8-Bit Local Bus ......................................................................................................................12 Figure 3-1. Reset and Initialization Process..........................................................................................................................13 Figure 3-2. PCI 9080 Internal Register Access .....................................................................................................................17 Figure 3-3. Dual Address Decode Mode ...............................................................................................................................18 Figure 3-4. Direct Master, Direct Slave, and DMA ................................................................................................................19 Figure 3-5. Mailbox/Doorbell Message Passing....................................................................................................................19 Figure 3-6. Direct Master Write .............................................................................................................................................20 Figure 3-7. Direct Master Read .............................................................................................................................................20 Figure 3-8. Local Master Direct Master Access of PCI Bus ..................................................................................................24 Figure 3-9. PCI Specification v2.1 Delayed Reads ...............................................................................................................25 Figure 3-10. PCI 9080 Read Ahead Mode ............................................................................................................................26 Figure 3-11. Direct Slave Write .............................................................................................................................................26 Figure 3-12. Direct Slave Read .............................................................................................................................................26 Figure 3-13. Direct Slave Access of Local Bus .....................................................................................................................28 Figure 3-14. Non-Chaining DMA Initialization .......................................................................................................................31 Figure 3-15. DMA, PCI-to-Local ............................................................................................................................................32 Figure 3-16. DMA, Local-to-PCI ............................................................................................................................................32 Figure 3-17. Chaining DMA Initialization ...............................................................................................................................33 Figure 3-18. Chaining Mode DMA from PCI-to-Local ...........................................................................................................34 Figure 3-19. Local-to-PCI Bus DMA Data Transfer Operation..............................................................................................35 Figure 3-20. PCI-to-Local Bus DMA Data Transfer Operation..............................................................................................35 Figure 3-21. Interrupt and Error Sources ..............................................................................................................................38 Figure 3-22. I2O System Architecture ....................................................................................................................................40 Figure 3-23. I2O Software Architecture..................................................................................................................................41 Figure 3-24. Circular FIFO Operation....................................................................................................................................43 Figure 6-1. PCI 9080 Local Input Setup and Hold Waveform .............................................................................................103 Figure 6-2. PCI 9080 Local Output Delay ...........................................................................................................................104 Figure 6-3. ALE Operation...................................................................................................................................................105 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved xi Figures Figure 7-1. Package Mechanical Dimensions .....................................................................................................................107 Figure 7-2. Typical PCI Bus Master Adapter.......................................................................................................................108 Figure 7-3. PCI 9080 Pin Out (All Modes)...........................................................................................................................109 xii PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved TABLES Table 1-1. Programmable Local Bus Modes ...........................................................................................................................4 Table 1-2. Pin Compatibility.....................................................................................................................................................4 Table 1-3. Comparison of the PCI 9060, PCI 9060ES, PCI 9060SD, and PCI 9080..............................................................5 Table 2-1. PCI Target Command Codes.................................................................................................................................7 Table 2-2. DMA Master Command Codes ..............................................................................................................................7 Table 2-3. Local-to-PCI Memory Access.................................................................................................................................7 Table 2-4. Local-to-PCI I/O Access.........................................................................................................................................7 Table 2-5. Local-to-PCI Configuration Access ........................................................................................................................7 Table 2-6. Local Processor Bus Types ...................................................................................................................................8 Table 2-7. Burst and Bterm on the Local Bus .........................................................................................................................9 Table 2-8. Burst Mode ............................................................................................................................................................9 Table 2-9. Partial Lword Accesses........................................................................................................................................10 Table 2-10. Big/Little Endian Program Mode ........................................................................................................................11 Table 2-11. Upper Lword Lane Transfer ...............................................................................................................................11 Table 2-12. Upper Word Lane Transfer ................................................................................................................................11 Table 2-13. Lower Word Lane Transfer ................................................................................................................................11 Table 2-14. Upper Byte Lane Transfer..................................................................................................................................12 Table 2-15. Lower Byte Lane Transfer..................................................................................................................................12 Table 3-1. NB# and Serial EEPROM Guidelines ..................................................................................................................14 Table 3-2. Short Serial EEPROM Load Registers.................................................................................................................15 Table 3-3. Long Serial EEPROM Load Registers .................................................................................................................16 Table 3-4. Extra Long Serial EEPROM Load Registers........................................................................................................17 Table 3-5. Recommended Serial EEPROM Loads ...............................................................................................................17 Table 3-6. Response to Full and Empty FIFOs .....................................................................................................................19 Table 3-7. Queue Starting Address.......................................................................................................................................41 Table 3-8. Circular FIFO Summary .......................................................................................................................................45 Table 4-1. New Registers Definitions Summary....................................................................................................................47 Table 4-2. Register Differences between PCI 9080 and PCI 9060.......................................................................................48 Table 4-3. Register Differences between PCI 9080 and PCI 9060ES ..................................................................................50 Table 4-4. Register Differences between PCI 9080 and PCI 9060SD..................................................................................52 Table 4-5. PCI Configuration Registers.................................................................................................................................54 Table 4-6. Local Configuration Registers ..............................................................................................................................55 Table 4-7. Runtime Registers................................................................................................................................................56 Table 4-8. DMA Registers .....................................................................................................................................................57 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved xiii Tables Table 4-9. Messaging Queue Registers................................................................................................................................58 Table 4-10. (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register ............................................................................59 Table 4-11. (PCICR; PCI:04h, LOC:04h) PCI Command Register .......................................................................................59 Table 4-12. (PCISR; PCI:06h, LOC:06h) PCI Status Register..............................................................................................60 Table 4-13. (PCIREV; PCI:08h, LOC:08h) PCI Revision ID Register ...................................................................................60 Table 4-14. (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code Register .......................................................................60 Table 4-15. (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size Register........................................................................61 Table 4-16. (PCILTR; PCI:0Dh, LOC:0Dh) PCI Latency Timer Register ..............................................................................61 Table 4-17. (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type Register................................................................................61 Table 4-18. (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) Register............................................................61 Table 4-19. (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses to Local, Runtime, and DMA Registers.............................................................................................62 Table 4-20. (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses to Local, Runtime, and DMA Registers.............................................................................................62 Table 4-21. (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to Local Address Space 0 .................................................................................................................63 Table 4-22. (PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses to Local Address Space 1 .................................................................................................................63 Table 4-23. (PCIBAR4; PCI:20h, LOC:20h) PCI Base Address Register .............................................................................64 Table 4-24. (PCIBAR5; PCI:24h, LOC:24h) PCI Base Address Register .............................................................................64 Table 4-25. (PCICIS; PCI:28h, LOC:28h) PCI Cardbus CIS Pointer Register......................................................................64 Table 4-26. (PCISVID; PCI:2Ch, LOC:2Ch) PCI Subsystem Vendor ID Register ................................................................64 Table 4-27. (PCISID; PCI:2Eh, LOC:2Eh) PCI Subsystem ID Register ...............................................................................64 Table 4-28. (PCIERBAR; PCI:30h, LOC:30h) PCI Expansion ROM Base Register.............................................................64 Table 4-29. (PCIILR; PCI:3Ch, LOC:3Ch) PCI Interrupt Line Register.................................................................................64 Table 4-30. (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Register ..................................................................................65 Table 4-31. (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Register ......................................................................................65 Table 4-32. (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat Register .......................................................................................65 Table 4-33. (LAS0RR; PCI:00h, LOC:80h) Local Address Space 0 Range Register for PCI-to-Local Bus .........................66 Table 4-34. (LAS0BA; PCI:04h, LOC:84h) Local Address Space 0 Local Base Address (Remap) Register.......................66 Table 4-35. (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/Arbitration Register ........................................................67 Table 4-36. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register ...............................................................68 Table 4-37. (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range Register....................................................................69 Table 4-38. (EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) Register and BREQo Control ..........................................................................................................................69 Table 4-39. (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor Register ........70 Table 4-40. (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register for Direct Master to PCI...................................................71 xiv PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Tables Table 4-41. (DMLBAM; PCI:20h, LOC:A0h) Local Bus Base Address Register for Direct Master to PCI Memory..............71 Table 4-42. (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register for Direct Master to PCI IO/CFG........................71 Table 4-43. (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master to PCI Memory ........72 Table 4-44. (DMCFGA; PCI:2Ch, LOC:ACh) PCI Configuration Address Register for Direct Master to PCI IO/CFG .........73 Table 4-45. (LAS1RR; PCI:F0h, LOC:170h) Local Address Space 1 Range Register for PCI-to-Local Bus .......................73 Table 4-46. (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap) Register ....................74 Table 4-47. (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor Register..................................74 Table 4-48. (MBOX0; PCI:40h or 78h, LOC:C0h) Mailbox Register 0 ..................................................................................75 Table 4-49. (MBOX1; PCI:44h or 7Ch, LOC:C4h) Mailbox Register 1 .................................................................................75 Table 4-50. (MBOX2; PCI:48h, LOC:C8h) Mailbox Register 2 .............................................................................................75 Table 4-51. (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 3 ............................................................................................75 Table 4-52. (MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4 .............................................................................................75 Table 4-53. (MBOX5; PCI:54h, LOC:D4h) Mailbox Register 5 .............................................................................................75 Table 4-54. (MBOX6; PCI:58h, LOC:D8h) Mailbox Register 6 .............................................................................................75 Table 4-55. (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 7 ............................................................................................75 Table 4-56. (P2LDBELL; PCI:60h, LOC:E0h) PCI-to-Local Doorbell Register .....................................................................76 Table 4-57. (L2PDBELL; PCI:64h, LOC:E4h) Local-to-PCI Doorbell Register .....................................................................76 Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register.......................................................................77 Table 4-59. (CNTRL; PCI:6Ch, LOC:ECh) Serial EEPROM Control, PCI Command Codes, User I/O Control, Init Control Register ..........................................................................................................................79 Table 4-60. (PCIHIDR; PCI:70h, LOC:F0h) PCI Permanent Configuration ID Register .......................................................79 Table 4-61. (PCIHREV; PCI:74h, LOC:F4h) PCI Permanent Revision ID Register .............................................................79 Table 4-62. (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode Register ...............................................................80 Table 4-63. (DMAPADR0; PCI:84h, LOC:104h) DMA Channel 0 PCI Address Register .....................................................81 Table 4-64. (DMALADR0; PCI:88h, LOC:108h) DMA Channel 0 Local Address Register...................................................81 Table 4-65. (DMASIZ0; PCI:8Ch, LOC:10Ch) DMA Channel 0 Transfer Size (Bytes) Register .......................................... 81 Table 4-66. (DMADPR0; PCI:90h, LOC:110h) DMA Channel 0 Descriptor Pointer Register...............................................81 Table 4-67. (DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode Register ...............................................................82 Table 4-68. (DMAPADR1; PCI:98h, LOC:118h) DMA Channel 1 PCI Address Register .....................................................83 Table 4-69. (DMALADR1; PCI:9Ch, LOC:11Ch) DMA Channel 1 Local Address Register ................................................. 83 Table 4-70. (DMASIZ1; PCI:A0h, LOC:120h) DMA Channel 1 Transfer Size (Bytes) Register ...........................................83 Table 4-71. (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer Register ..............................................83 Table 4-72. (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Register ...............................................83 Table 4-73. (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Register ...............................................84 Table 4-74. (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration Register .............................................................................84 Table 4-75. (DMATHR; PCI:B0h, LOC:130h) DMA Threshold Register ...............................................................................84 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved xv Tables Table 4-76. (OPLFIS; PCI:30h, LOC:B0) Outbound Post List FIFO Interrupt Status Register.............................................85 Table 4-77. (OPLFIM; PCI:34h, LOC:B4) Outbound Post List FIFO Interrupt Mask Register ..............................................85 Table 4-78. (IQP; PCI:40h) Inbound Queue Port Register....................................................................................................85 Table 4-79. (OQP; PCI:44h) Outbound Queue Port Register ...............................................................................................85 Table 4-80. (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration Register ........................................................86 Table 4-81. (QBAR; PCI:C4h, LOC:144h) Queue Base Address Register...........................................................................86 Table 4-82. (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer Register.................................................................86 Table 4-83. (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer Register...................................................................86 Table 4-84. (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer Register.................................................................87 Table 4-85. (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer Register ....................................................................87 Table 4-86. (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer Register ............................................................87 Table 4-87. (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer Register ..............................................................87 Table 4-88. (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer Register ............................................................87 Table 4-89. (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer Register................................................................88 Table 4-90. (QSR; PCI:E8h, LOC:168h) Queue Status/Control Register .............................................................................88 Table 5-1. Pin Type Abbreviations ........................................................................................................................................89 Table 5-2. Power and Ground Pin Description......................................................................................................................90 Table 5-3. Serial EEPROM Interface Pin Description ...........................................................................................................90 Table 5-4. PCI System Bus Interface Pin Description...........................................................................................................91 Table 5-5. Local Bus Mode and Processor Independent Interface Pin Description..............................................................92 Table 5-6. C Bus Mode Interface Pin Description .................................................................................................................94 Table 5-7. J Bus Mode Interface Pin Description ..................................................................................................................96 Table 5-8. S Bus Mode Interface Pin Description .................................................................................................................98 Table 6-1. Absolute Maximum Ratings ...............................................................................................................................101 Table 6-2. Operating Ranges ..............................................................................................................................................101 Table 6-3. Capacitance (sample tested only)......................................................................................................................101 Table 6-4. Electrical Characteristics Estimated over Operating Range ..............................................................................102 Table 6-5. AC Electrical Characteristics (Local Inputs) Estimated over Operating Range .................................................103 Table 6-6. AC Electrical Characteristics (Local Outputs) Estimated over Operating Range ..............................................104 Table 6-7. ALE Operation....................................................................................................................................................105 xvi PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved TIMING DIAGRAMS Timing Diagram 8-1. (C, J Modes) PCI RST# Asserting Local Output LRESETo# ............................................................111 Timing Diagram 8-2. (S Mode) Two Phase Clock Synchronization Using LRESETo#.......................................................111 Timing Diagram 8-3. PCI 9080 Local Bus Arbitration..........................................................................................................112 Timing Diagram 8-4. PCI 9080 1K Serial EEPROM PCI Initialization.................................................................................113 Timing Diagram 8-5. Local Interrupt (LINTi#) Input Asserting PCI Output INTA# ..............................................................114 Timing Diagram 8-6. (C Mode) PCI Configuration Write to PCI 9080 PCI Configuration Register.....................................115 Timing Diagram 8-7. (C Mode) PCI Configuration Read to PCI 9080 PCI Configuration Register ....................................115 Timing Diagram 8-8. (C Mode) PCI Memory Write to PCI 9080 Local Configuration Register ..........................................116 Timing Diagram 8-9. (C Mode) PCI Memory Read to PCI 9080 Local Configuration Register .......................................... 116 Timing Diagram 8-10. (C Mode) Direct Slave Single Cycle Read (32-Bit Local Bus).........................................................117 Timing Diagram 8-11. (C Mode) Direct Slave Single Cycle Write.......................................................................................118 Timing Diagram 8-12. (C Mode) PCI 9080 DMA or Direct Slave Burst Read from Local Bus, No Wait States, Bterm Enabled ......................................................................................................119 Timing Diagram 8-13. (C Mode) DMA or Direct Slave PCI 9080 Burst Write to Local Bus, Bterm Enabled ......................120 Timing Diagram 8-14. (C Mode) Direct Slave PCI-to-Local Burst Read, Bterm Disabled ..................................................121 Timing Diagram 8-15. (C Mode) PCI 9080 DMA or Direct Slave Burst Write, Bterm Disabled ..........................................122 Timing Diagram 8-16. (C Mode) Direct Slave Read with Prefetch Counter Set to 5 ..........................................................123 Timing Diagram 8-17. (C Mode) Direct Slave or DMA Burst Write to 32-Bit Local Bus Suspended by BREQ Input .........124 Timing Diagram 8-18. (C Mode) Direct Slave Burst Read of Five Lwords with One Wait State.........................................125 Timing Diagram 8-19. (C Mode) Direct Slave Burst Write of Five Lwords with One Wait State.........................................126 Timing Diagram 8-20. (C Mode) Direct Slave Read 2.1 Spec ............................................................................................127 Timing Diagram 8-21. (C Mode) Direct Slave Read No Flush Mode (Read Ahead Mode).................................................128 Timing Diagram 8-22. (C Mode) Direct Slave Read of Two Lwords from 8-Bit Bus ...........................................................129 Timing Diagram 8-23. (C Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 8-Bit Local Bus, No Wait States, Bterm Enabled ......................................................................................................130 Timing Diagram 8-24. (C Mode) Direct Slave Read of Two Lwords from 16-Bit Bus .........................................................131 Timing Diagram 8-25. (C Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 16-Bit Local Bus, No Wait States, Bterm Enabled ......................................................................................................132 Timing Diagram 8-26. (C Mode) Direct Slave Read of Two Lwords from 8-Bit I/O Local Bus, Burst Disabled ..................133 Timing Diagram 8-27. (C Mode) Direct Slave Write of Two Lwords to 8-Bit I/O Local Bus, Burst Disabled.......................134 Timing Diagram 8-28. (C Mode) Direct Slave in BIGEND Local Bus with BIGEND# Input or Internal Register Setting ....135 Timing Diagram 8-29. (C Mode) Locked Direct Slave Read Followed by Write and Release (LLOCKo#).........................136 Timing Diagram 8-30. (C Mode) Local Bus Read from PCI 9080 CFG Registers ..............................................................137 Timing Diagram 8-31. (C Mode) Local Bus Write to PCI 9080 CFG Registers ..................................................................138 Timing Diagram 8-32. (C Mode) Local Bus Direct Master Single Memory Read................................................................139 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved xvii Timing DIagrams Timing Diagram 8-33. (C Mode) Local Bus Direct Master Single Memory Write Cycle......................................................140 Timing Diagram 8-34. (C Mode) PCI 9080 Direct Master Memory Read, 12 Lword Burst .................................................141 Timing Diagram 8-35. (C Mode) PCI 9080 Direct Master Memory Write of 12 Lwords ......................................................142 Timing Diagram 8-36. (C Mode) PCI 9080 Direct Master Memory Read with WAITI# .......................................................143 Timing Diagram 8-37. (C Mode) PCI 9080 Direct Master Memory Write with WAITI# .......................................................144 Timing Diagram 8-38. (C Mode) PCI 9080 Direct Master Configuration Read--Type 1 or Type 0 ....................................145 Timing Diagram 8-39. (C Mode) PCI 9080 Direct Master Configuration Write--Type 1 or Type 0 ....................................146 Timing Diagram 8-40. (C Mode) Local Bus Direct Master Read from PCI I/O....................................................................147 Timing Diagram 8-41. (C Mode) Direct Master Write to PCI I/O .........................................................................................148 Timing Diagram 8-42. (C Mode) PCI 9080 Direct Master Memory Read--Keep Bus ........................................................149 Timing Diagram 8-43. (C Mode) PCI 9080 Direct Master Memory Read--Drop Bus.........................................................150 Timing Diagram 8-44. (C Mode) PCI Bus Request (REQ#) Delay During Direct Master Write (8 PCI Clock Delay) .........151 Timing Diagram 8-45. (C Mode) Direct Master Memory Read, Prefetch of 16 ...................................................................152 Timing Diagram 8-46. (C Mode) Direct Master Memory Write and Invalidate (MWI)--Cache Line Size of 8 ....................153 Timing Diagram 8-47. (C Mode) Direct Master in BIGEND Local Bus with BIGEND# Input or Interrupt............................154 Timing Diagram 8-48. (C Mode) Direct Master Burst, Memory Read Cycles (Changing LBE[3:0]#) .................................155 Timing Diagram 8-49. (C Mode) Direct Master Five Lword Burst Write (Changing LBE[3:0]#) ..........................................156 Timing Diagram 8-50. (C Mode) Direct Master Locked Read Followed by Write and Release (LLOCK# and LOCK#).....157 Timing Diagram 8-51. (C Mode) BREQo and Deadlock .....................................................................................................158 Timing Diagram 8-52. (C Mode) DMA Aligned PCI Address to Aligned Local Address, Bterm Disabled...........................159 Timing Diagram 8-53. (C Mode) DMA Aligned Local Address to Aligned PCI Address, Burst Enabled, Bterm Enabled...160 Timing Diagram 8-54. (C Mode) DMA Aligned PCI Address to Aligned Local Address (External Generation of Wait States) ..............................................................................................161 Timing Diagram 8-55. (C Mode) Read of DMA Chaining Parameters from PCI and Local Buses .....................................162 Timing Diagram 8-56. (C Mode) PCI 9080 DMA Read of Chaining Parameters from Local Bus, No Wait States.............163 Timing Diagram 8-57. (C Mode) Read of DMA Chaining Parameters from PCI Bus (Local-to-PCI Transfer)....................164 Timing Diagram 8-58. (C Mode) Single Cycle DMA Demand Mode PCI-to-Local..............................................................165 Timing Diagram 8-59. (C Mode) Multiple Cycle (Burst) DMA Demand Mode PCI-to-Local, No Wait States .....................165 Timing Diagram 8-60. (C Mode) DMA Demand Mode Terminated with BLAST# (Local-to-PCI) .......................................166 Timing Diagram 8-61. (C Mode) DMA Local-to-PCI, Terminated with EOT[1:0]# ..............................................................167 Timing Diagram 8-62. (C Mode) DMA PCI-to-Local, Terminated with EOT[1:0]# ..............................................................168 Timing Diagram 8-63. (C Mode) DMA PCI-to-Local with Local Pause Timer and Local Latency Timer ............................169 Timing Diagram 8-64. (J Mode) PCI 9080 Direct Slave Burst Read from Local Bus, No Wait States, Bterm Enabled......170 Timing Diagram 8-65. (J Mode) PCI 9080 Direct Slave Burst Write to Local Bus, No Wait States, Bterm Enabled ..........171 Timing Diagram 8-66. (J Mode) PCI 9080 DMA or Direct Slave Burst Write to Local Bus, No Wait States, Bterm Disabled................................................................................................................................172 xviii PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Timing DIagrams Timing Diagram 8-67. (J Mode) Direct Slave in BIGEND Local Bus with BIGEND# Input or Internal Register Setting .....173 Timing Diagram 8-68. (J Mode) Direct Slave Read v2.1 Spec ...........................................................................................174 Timing Diagram 8-69. (J Mode) Direct Slave Read No Flush Mode (Read Ahead Mode), Prefetch Mode Enabled .........175 Timing Diagram 8-70. (J Mode) Local Bus Read from PCI 9080 CFG Registers...............................................................176 Timing Diagram 8-71. (J Mode) Local Bus Write to PCI 9080 CFG Registers ...................................................................176 Timing Diagram 8-72. (J Mode) Direct Master Read Access from PCI Bus (Keep PCI Bus If Read FIFO Full Mode), No PCI Disconnects...............................................................................177 Timing Diagram 8-73. (J Mode) Local Bus Direct Master Burst Write Access to PCI Bus, Continuous If Same Clock Rate and No PCI Disconnects .............................................................178 Timing Diagram 8-74. (J Mode) Local Bus Direct Master Lock Memory Read Access from PCI Bus Followed by Write and Release ......................................................................................................179 Timing Diagram 8-75. (J Mode) PCI 9080 DMA Local-to-PCI, No Wait States, Bterm Enabled ........................................180 Timing Diagram 8-76. (J Mode) PCI 9080 DMA PCI-to-Local Bus, No Wait States, Bterm Enabled .................................181 Timing Diagram 8-77. (J Mode) DMA Read of Chaining Parameters, No Wait States.......................................................182 Timing Diagram 8-78. (J Mode) PCI 9080 Write to Local Bus BREQ Asserted..................................................................183 Timing Diagram 8-79. (S Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 16-Bit Local Bus, No Wait States, Bterm Enabled ......................................................................................................184 Timing Diagram 8-80. (S Mode) Local Bus Read from PCI 9080 CFG Registers ..............................................................185 Timing Diagram 8-81. (S Mode) Local Bus Write to PCI 9080 CFG Registers...................................................................186 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved xix This page intentionally left blank. xx PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved PREFACE The information contained in this document should be considered preliminary. Although an effort has been made to keep the information accurate, there may be misleading or even incorrect statements made herein. The document is being written in parallel with actual chip development and, as such, it is subject to change. This description is intended to be a living document, to be updated throughout the PCI 9080 design effort. It provides a broad technical overview of the PCI 9080. The following is a list of additional documentation to provide the reader with further information about the PCI 9080 and related subjects: * PCI Local Bus Specification, Revision 2.1 PCI Special Interest Group 5200 N.E. Elam Young Parkway, Hillsboro, OR, 97124-6497 USA 503-696-2000, http://www.pcisig.com * PCI Hot-Plug Specification, Revision 1.0 PCI Special Interest Group 5200 N.E. Elam Young Parkway, Hillsboro, OR, 97124-6497 USA 503-696-2000, http://www.pcisig.com * PCI Power Management Interface Specification, Revision 1.0, June 30, 1997 PCI Special Interest Group 5200 N.E. Elam Young Parkway, Hillsboro, OR, 97124-6497 USA 503-696-2000, http://www.pcisig.com * PICMG 2.0, CompactPCI (registered) Specification, Revision 2.1 or greater PCI Industrial Computer Manufacturers Group (PICMG) 301 Edgewater Place, Suite 220, Wakefield, MA 01880, USA Tel: 781-224-1100, Fax: 617-224-1239, http://www.picmg.org * Intelligent I/O (I2O) Architecture Specification, Revision 1.5 I2O Special Interest Group 404 Balboa Street, San Francisco, CA 94118 USA Tel: 415-750-8352, Fax: 415-751-4829, http://www.i2osig.com PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved xxi This page intentionally left blank. xxii PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved REVISION HISTORY Date Revision 07/3/1997 1.0 07/10/1997 07/24/1997 08/19/1997 01/26/1998 1.01 1.02 1.03 1.04 Comment * Initial release. * Release timing diagrams. * Corrected typos and matched spec. * Changed Pin 170 to NC. * Changed LARBR (Local/Arbitration Register) to MARBR (Mode/Arbitration Register). * Set up hold and output timings * Change mechanical package dimension. * Complete electrical tables in Section 6. * Correct timing diagrams. * Matched spec. * Changed the title of Section 7. * Added READYo# value to Table 6-6. * Removed WR# and RD# signals from and corrected signal LA[31:0] reference in Timing Diagram 8-20. * Corrected titles of Timing Diagrams 8-20 and 8-68. * Corrected titles of Sections 8.3.3 and 8.4.3. * Corrected Bterm mode reference in Section 2.2.3.2. * Corrected reference to Note in Table 4-7. * Corrected information for bits [23:20] in Table 4-75. * Corrected package mechanical dimension to 30.6 x 30.6 mm in Figure 7-1. * Corrected LBE[3:0]# signal information in Timing Diagram 8-15. * Corrected signal LA[31:0] reference in Timing Diagram 8-21. * Corrected all "Bterm enabled" and "Bterm disabled" references to "BTERM# enabled" and "BTERM# disabled" in all affected timing diagrams in Section 8. * Applied general editing to register and pin out tables. * Corrected values in Table 3-5. * Corrected direction of DEVSEL#, TRDY# signal in Figure 3-16. * Corrected name of Figure "Typical Adapter Block Diagram" and Table 6-3. * Changed VIL and VIH values to include both CMOS and TTL values in Table 6-4. * Significantly revised Table 6-5 and Table 6-6. * Updated timing diagrams. * Reversed "BTERM# enabled/disabled" changes made in v1.03 back to "Bterm enabled/disabled." * Corrected text for DMATHR [31:28, 15:12] now reads "...before requesting PCI Bus for reads" and bits [27:24, 11:8] now reads "...before requesting PCI Bus for writes." PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved xxiii REVISION HISTORY Date Revision 09/01/1999 1.05 01/2000 xxiv 1.06 Comment * Changed document title from "Data Sheet" to "Data Book." * Added company background information. * Corrected register bit number in section 3.7.6.1. * Corrected Serial EEPROM Writable capability of 30h PCI CFG Register in Table 4-5. * Corrected Bterm information on bit 23 of Table 4-39. * Revised DMA Channel 1 number of full entries (delete divide by 2 operation) in Table 4-75. * Updated timing diagrams. * Added ALE Operation section after Electrical Specification page 101, Section 6. * Added values in Table 6-1. * Revised operating range temperature values in Table 6-2. * Added values in Table 6-4 for VOH3, VOL3, VIH3, and VIL3. * Revised LAD values in Table 6-6. * Revised timing diagrams 8-10, 8-17, 8-30, 8-31, 8-70, and 8-71. * Cosmetic changes (capitalizations of specific terms, etc.). * Applied minor format changes. * Changed copyright date to 2000. * Added primary title page, 800 number, disclaimer and trademarks, part number, and list of Figures, Tables, and Timing Diagrams. * Changed "negate" to "de-assert." * Added PCI and Local Bus information to FIgure 3-5. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved PCI 9080 PCI I/O Accelerator I2O Compatible PCI Bus Master Interface Chip for Adapters and Embedded Systems January 2000 VERSION 1.06 FEATURES * PCI Specification 2.1 (v2.1) compliant Bus Master Interface chip for adapters and embedded systems * I2O Compatible Messaging Unit * 3.3 or 5 volt PCI signaling, 5 volt core, low-power CMOS in a 208-pin PQFP * Two independent DMA channels for Local Bus memory to and from PCI Host Bus Data transfers * Eight programmable FIFOs for zero wait state burst operation Boot ROM CPU * PCI Local Data transfers up to 132 MB/sec * Programmable Local Bus supports nonmultiplexed 32-bit address/data, multiplexed 32- or 16-bit, and Slave accesses of 32-, 16-, or 8-bit Local Bus devices * Local Bus runs asynchronously to the PCI Bus * Eight 32-bit Mailbox and two 32-bit Doorbell registers * Performs Big Endian/Little Endian conversion * Upward compatibility with the PCI 9060, PCI 9060ES, and PCI 9060SD Local Memory I/O Device (LAN, Disk, Video, etc.) Local Bus PCI 9080 Registers Serial EEPROM Local Bus Interface FIFOs PCI Local Runtime DMA I2O Control: - DMA - I2O - Unaligned Transfer PCI Interface PCI Bus Typical Adapter Block Diagram PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 1 Features Internal Registers PCI Config. Local Config. Run-Time DMA Serial EEPROM Initialization I2O Messaging PCI Bus State Machines PCI Bus Interface Control Logic FIFOs PCI Initiator (for Direct Master Xfers) Dir. Master Write PCI Target (for Direct Slave Xfers) Dir. Slave Write PCI Initiator (For Ch 1 DMA Xfers) DMA1 PCI/Loc PCI Initiator (For Ch 0 DMA Xfers) DMA0 PCI/Loc Dir. Master Read Dir. Slave Read DMA1 Loc/PCI DMA0 Loc/PCI I2O Messaging DMA Local Bus State Machines Local Slave (for Direct Master Xfers) Local Master (for Direct Slave Xfers) Local Master (For Ch 1 DMA Xfers) Local Master (For Ch 0 DMA Xfers) DMA Chaining Local Bus Interface: - Select Bus Width 8,16, or 32 bit - Endian Conversion - Select Muxed or non-Muxed Addr/Data Unaligned Xfer PCI 9080 Internal Block Diagram 2 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 1. GENERAL DESCRIPTION management pointers that can be used for message passing under the I2O protocol or a custom protocol. 1.1 Company and Product Background 1.2.2 Embedded Systems PLX Technology, Inc., the world leader in PCI-to-Local Bus I/O accelerator chips, supports more than 500 OEM customers in a wide variety of PCI applications. Customer applications include PC workstations and servers, PCI add-in boards, embedded PCI communication systems such as routers and switches, and industrial PCI implementations such as CompactPCI, PMC, and Passive Backplane PCI. Another application for the PCI 9080 is in embedded systems, such as network hubs and routers, printer engines, and industrial equipment. In this configuration, all four of the above-mentioned Data Transfer modes are used. In addition, the PCI 9080 supports Type 0 and Type 1 PCI Configuration cycles, which allows embedded CPU to act as the embedded system host and to configure other PCI devices in the system. PLX Technology, Inc., is an active participant in industry , standard committees, including the PCI SIG I2O SIG, and PICMG , and maintains active developer technology and cross-marketing partnerships with industry leaders, such as Intel, IBM, Hewlett-Packard, Motorola, Integrated Systems, WindRiver and others. Focused on providing complete solutions for PCI implementations, PLX provides design assistance to customers in the form of Reference Design and Software Development kits. Depending upon the application, these kits may include reference boards, API libraries, software debug tools, and sample device drivers with source, enabling customers to quickly bring new designs to production. New tools, application notes, FAQs, and information updates are constantly added to the website for the convenience of PLX customers. Our expertise and total solutions for the PCI interface allow customers to focus on adding value in their designs without worrying about the complexities of implementing PCI, I2O, and CompactPCI. 1.2 PCI 9080 Applications 1.2.1 PCI Adapter Cards Major PCI adapter card applications for the PCI 9080 include high performance communications, networking, disk control, multimedia, and video adapters. The PCI 9080 moves data between the host PCI Bus and adapter Local Bus in several ways. First, the local CPU or host processor may program the DMA controller of the PCI 9080 to move data between the adapter memory and host PCI Bus. Second, the PCI 9080 can perform Direct Master Transfers, whereby a local CPU or controller accesses the PCI Bus directly through a PCI Master transfer. The PCI 9080 also supports Slave transfers in which another PCI device is the Master. Finally, the PCI 9080 contains a complete messaging unit with mailbox registers, doorbell registers, and queue PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 1.3 Major Features PCI 2.1 Compliant. The PCI 9080 is compliant with all aspects of PCI Specification v2.1. I2O Messaging Unit. The PCI 9080 incorporates an I2O messaging unit. This enables the adapter or embedded system to communicate with other I2O-supported devices. The I2O messaging unit is fully compatible with the PCI extension of the I2O specification v1.5. Dual Independent Programmable DMA Controllers with Programmable FIFOs. The PCI 9080 provides two independently programmable DMA controllers with programmable FIFOs for each channel. Each channel supports Non-chaining and Chaining DMA modes, Demand mode DMA, and End of Transfer (EOT) mode. Direct Bus Master. The PCI 9080 supports MemoryMapped bursts, Transfer accesses, and I/O-Mapped Single-Transfer accesses to the PCI Bus from the Local Bus Master. The PCI 9080 also supports PCI Bus Interlock (LOCK#) cycles. The Read and Write FIFOs enable high-performance bursting. PCI Host Capability. In Direct Master mode, the PCI 9080 can generate Type 0 or Type 1 PCI Configuration cycles. Direct Slave. The PCI 9080 supports Burst MemoryMapped and single I/O-Mapped accesses to the Local Bus. The Read and Write FIFOs enable highperformance bursting. Programmable Local Bus Modes. The PCI 9080 is a PCI Bus Master interface chip that connects a PCI Bus to one of three Local Bus types, selected through mode pins. The PCI 9080 may be connected to any Local Bus with a similar design with little or no glue logic. Table 1-1 lists the three modes. 3 Section 1 General Description Compatibility with PCI 9060, PCI 9060ES, and PCI 9060SD Table 1-1. Programmable Local Bus Modes Mode Description C 32-bit address/32-bit data, nonmultiplexed J 32-bit address/32-bit data, multiplexed S 32-bit address/16-bit data, multiplexed Interrupt Generator. The PCI 9080 can generate PCI and Local interrupts from several sources. Clock. The PCI 9080 Local Bus interface runs from a local TTL clock and generates the necessary internal clocks. This clock runs asynchronously to the PCI clock. There is a buffered PCI clock (BPCLKo) for the Local Bus to use. BPCLKo may be connected to LCLK. 3.3 Volt and 5 Volt Operation. The PCI 9080 core requires 5V Vcc. The PCI 9080 provides 3.3V or 5V signaling on the PCI Bus. The Local Bus operates at a 5V signaling level. Serial EEPROM Interface. The PCI 9080 contains an optional serial EEPROM interface that can be used to load configuration information. This is useful for loading information unique to a particular adapter (such as Network ID or Vendor ID). Mailbox registers. The PCI 9080 contains eight 32-bit mailbox registers that may be accessed from the PCI or Local Bus. Bus. Address must be subsequent to previous address and 32-bit aligned (next address = current address + 4). Programmable Bus Wait States. The PCI 9080 can be programmed to keep the PCI Bus by generating a wait state(s), thereby de-asserting TRDY#, if the Write FIFO becomes full. The PCI 9080 can also be programmed to keep the Local Bus. LHOLD is asserted if the Direct Slave Write FIFO becomes empty or the Direct Slave Read FIFO becomes full. The Local Bus is dropped in either case when the Local Bus Latency Timer is enabled and expires. 1.4 Compatibility with PCI 9060, PCI 9060ES, and PCI 9060SD The PCI 9080 is upward compatible with the PCI 9060, PCI 9060ES and PCI 9060SD, except as noted in Table 1-2 and Section 4.1, "New Register Definitions Summary." 1.4.1 Pin Compatibility When upgrading from the PCI 9060, 9060ES or 9060SD, observe the following new pin definitions listed in Table 1-2. Table 1-2. Pin Compatibility Doorbell registers. The PCI 9080 includes two 32-bit doorbell registers. One generates interrupts from the PCI Bus to Local Bus. The other generates interrupts from the Local Bus to the PCI Bus. Pin # PCI 9060/9060ES/9060SD 170 CLKSEL NC -- Unaligned DMA Transfer Support. The PCI 9080 can transfer data on any byte boundary. Serial EEPROM Clock Select 175 EE1MC Optional Serial EEPROM Clock Source EESEL Serial EEPROM Select Big/Little Endian Conversion. The PCI 9080 supports dynamic switching between Big Endian and Little Endian operations for Direct Slave, Direct Master, DMA, and the Internal register accesses on the Local Bus. The PCI 9080 supports on-the-fly Endian conversion for Space 0, Space 1, and Expansion ROM space. The Local Bus can be Big/Little Endian by using the BIGEND# input pin or programmable internal register configuration. When BIGEND# is asserted, it overrides the internal register configuration. Note: The PCI Bus is always Little Endian. Pin Name Description PCI 9080 Pin Name Description 1=93CS46 (1K bit) 0=93CS56 (2K bit) 1.4.2 Register Compatibility All registers implemented in the PCI 9060, PCI 9060ES, and PCI 9060SD are implemented in the PCI 9080. There are a limited number of new bit definitions and several new registers. Refer to Section 4.1, "New Register Definitions Summary." Read Ahead Mode. The PCI 9080 supports Read Ahead mode, where prefetched data can be read from the PCI 9080 internal FIFO instead of from the Local 4 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 1 General Description Comparison of PCI 9060, PCI 9060ES, PCI 9060SD, and PCI 9080 1.5 Comparison of PCI 9060, PCI 9060ES, PCI 9060SD, and PCI 9080 Table 1-3. Comparison of the PCI 9060, PCI 9060ES, PCI 9060SD, and PCI 9080 Feature Number of DMA Channel(s) Local Address Spaces PCI 9060 PCI 9060ES PCI 9060SD PCI 9080 2 0 1 2 2 2 3 3 Yes Yes No Yes Mailbox Registers Eight 32-bit Four 32-bit Four 32-bit Eight 32-bit Doorbell Registers Two 32-bit Two 8-bit Two 8-bit Two 32-bit Direct Master Mode FIFOs 8 4 4 8 FIFO Depth--Direct Slave Write, Direct Master Write, DMA 0 Read and DMA 0 Write 8 Lwords (32 bytes) 16 Lwords (64 bytes) 16 Lwords (64 bytes) 32 Lwords (128 bytes) FIFO Depth--Direct Slave Read, Direct Master Read, DMA 1 Read and DMA 1 Write 8 Lwords (32 bytes) 16 Lwords (64 bytes) 16 Lwords (64 bytes) 16 Lwords (64 bytes) LLOCKo# Pin for Lock Cycles No Yes Yes Yes WAITI# Pin for Wait State Generation No Yes Yes Yes BPCLKo Pin; Buffered PCI Clock No Yes Yes Yes DREQ# and DACK# Pins for Demand Mode DMA Support Yes No Yes (Channel 1 only) Yes Register Addresses -- Identical except 9060ES has no DMA registers and Tables 25, 26, and 43 were added Identical, except 9060SD has one DMA register and Tables 4-29 and 4-30 were added Identical except PCI 9080 has additional I2O related registers and 30h, 34h, 40h, and 44h were remapped Pin Out -- Signals deleted: DREQ0# (pin 29) DACK0# (pin 30) Signals deleted: BREQ (pin 21) DMPAF# (pin 8) DREQ0# (pin 29) DACK0# (pin 30) BTERMo# (pin 28) Input signal added: EOT1# (pin 163) Note: The PCI 9080 includes all changes made for PCI 9060, PCI 9060ES, and PCI 9060SD. Input signals added: WAITI# (pin 6) BIGEND# (pin 48) Output signals added: BPCLKo (pin 168) LLOCKo# (pin 7) Signal changed: EESEL (pin 175) Input signals added: WAITI# (pin 6) BIGEND# (pin 48) EOT0# (pin 164 in C mode, Pin 5 in J and S modes) Output signals added: BPCLKo (pin 168) LLOCKo# (pin 7) Big/Little Endian Conversion No Yes Yes Yes PCI Specification v2.1 Deferred Reads No Yes Yes Yes Programmable Prefetch Counter No Yes Yes Yes Write and Invalidate Cycle No Yes Yes Yes Additional Device and Vendor ID Register No Yes Yes Yes I2O Messaging Unit No No No Yes 3.3V PCI Bus Signaling No No No Yes PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 5 This page intentionally left blank. 6 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 2. BUS OPERATION 2.1.2.1 DMA Master Command Codes 2.1 PCI Bus Cycles DMA controllers of the PCI 9080 can generate the Memory cycles listed in Table 2-2. The PCI 9080 is compliant with PCI Specification v2.1. Refer to the PCI 2.1 spec for any specific features of the PCI Bus. 2.1.1 PCI Target Command Codes As a Target, the PCI 9080 allows access to its Internal registers and the Local Bus, using the commands listed in Table 2-1. Table 2-1. PCI Target Command Codes Command Type Code (C/BE[3:0]#) I/O Read 0010 (2h) I/O Write 0011 (3h) Table 2-2. DMA Master Command Codes Command Type Code (C/BE[3:0]#) Memory Read 0110 (6h) Memory Write 0111 (7h) Memory Read Multiple 1100 (Ch) Memory Read Line 1110 (Eh) Memory Write and Invalidate 1111 (Fh) 2.1.2.2 Direct Local-to-PCI Command Codes For direct Local-to-PCI Bus accesses, the PCI 9080 generates the cycles listed in Table 2-3 through Table 2-5. Memory Read 0110 (6h) Memory Write 0111 (7h) Memory Read Multiple 1100 (Ch) Memory Read Line 1110 (Eh) Command Type Memory Write and Invalidate 1111 (Fh) Memory Read 0110 (6h) Configuration Read 1010 (Ah) Memory Write 0111 (7h) Configuration Write 1011 (Bh) Memory Read Multiple 1100 (Ch) Memory Read Line 1110 (Eh) All Read or Write accesses to the PCI 9080 can be Byte, Word, or Longword (Lword) accesses. All memory commands are aliased to the basic memory commands. All I/O accesses to the PCI 9080 are decoded to an Lword boundary. The byte enables are used to determine which bytes are read or written. An I/O access with illegal byte enable combinations is terminated with a Target Abort. Table 2-3. Local-to-PCI Memory Access Table 2-4. Local-to-PCI I/O Access Command Type The PCI 9080 can access the PCI Bus to perform DMA transfers or Direct Master Local-to-PCI Bus transfers. During the Direct Master or DMA transfer, the command code assigned to the PCI 9080 Internal register location, (CNTRL[15:0], is used as the PCI command code. Table 2-2 through Table 2-5 lists the various PCI Master Command codes. Notes: Programmable Internal registers determine PCI command codes when the PCI 9080 is Master. Code (C/BE[3:0]#) I/O Read 0010 (2h) I/O Write 0011 (3h) Table 2-5. Local-to-PCI Configuration Access Command Type 2.1.2 PCI Master Command Codes Code (C/BE[3:0]#) Code (C/BE[3:0]#) Configuration Memory Read 1010 (Ah) Configuration Memory Write 1011 (Bh) 2.1.3 PCI Arbitration The PCI 9080 asserts output REQ# to request the PCI Bus. The PCI 9080 can be programmed using MARBR[23] to de-assert REQ# when it asserts FRAME# during a Bus Master cycle, or to keep REQ# asserted for the entire Bus Master cycle. The PCI 9080 always deasserts REQ# for a minimum of two PCI clocks between Bus Master ownership that includes a Target disconnect. DMA cannot perform I/O or Configuration accesses. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 7 Section 2 Bus Operation Local Bus Cycles The Direct Master Write Delay bits (DMPBAM[15:14]) can be programmed to delay assertion of the PCI 9080 PCI REQ# signal during a Direct Master Write cycle. This register can be programmed to wait 0, 4, 8, or 16 PCI Bus clocks after the PCI 9080 has received its first Write data from the Local Master and is ready to begin the PCI Write transaction. This feature is useful in applications where the Local Master is bursting and the Local Bus clock is slower than the PCI Bus clock. This allows Write data to accumulate in the Direct Master Write FIFO of the PCI 9080, which provides for better utilization of the PCI Bus. 2.2.2 Local Bus Direct Master Local Bus cycles can be Continuous Single or Burst cycles (programmable by way of the PCI 9080 Internal registers). As a Local Bus Target, the PCI 9080 allows access to its Internal registers and the PCI Bus. In C and J modes, Local Bus Direct Master accesses to the PCI 9080 must be for a 32-bit nonpipelined bus. In S mode, Local Bus Direct Master accesses to the PCI 9080 must be for a 16-bit nonpipelined bus. 2.2.3 Local Bus Direct Slave 2.2 Local Bus Cycles The PCI 9080 connects a PCI Host bus to several Local processor bus types, as listed in Table 2-6. It operates in one of three modes, selected through mode pins 9 and 10, corresponding to three bus types--C, J, and S. Table 2-6. Local Processor Bus Types Bit 9 Bit 10 Mode Bus Type 0 0 C 32-bit nonmultiplexed 0 1 J 32-bit multiplexed 1 0 S 16-bit multiplexed 1 1 Reserved -- 2.2.1 Local Bus Arbitration When the PCI 9080 owns the Local Bus, both its LHOLD output and LHOLDA input are asserted. When the PCI 9080 samples that BREQ is asserted during a DMA transfer or Direct Slave Write transfer, it gives up the Local Bus within two Lword transfers by de-asserting LHOLD and floating its Local Bus outputs if: * BREQ is gated or disabled; or * Gating is enabled and the Local Bus Latency Timer expires The Local Arbiter can now grant the Local Bus to another Local Master. After the PCI 9080 samples that its LHOLDA is de-asserted and its Local Pause Timer is zero, it re-asserts LHOLD to request the Local Bus. When the PCI 9080 receives LHOLDA, it drives the bus and continues from where it left off. PCI Bus Master Read/Write to Local Bus (the PCI 9080 is a PCI Bus Target and Local Bus Master). 2.2.3.1 Ready/Wait State Control Accessing PCI 9080 from PCI Bus Accessing PCI 9080 from Local Bus PCI 9080 de-asserts TRDY# when waiting on the Local Bus PCI 9080 generates READYo# when data is valid on the following clock edge PCI Bus de-asserts IRDY# or simply end the cycle when it's not ready PCI 9080 Accessing PCI Bus PCI 9080 PCI 9080 can be programmed to de-assert IRDY# when its FIFOs are on a Direct Master Read Local Processor generates wait states with WAITI# PCI 9080 Accessing Local Bus PCI 9080 generates wait states with WAITO# (programmable) PCI Bus de-asserts TRDY# when it's not ready Local Bus can respond to PCI 9080 requests with READYi# Figure 2-1. Wait States Note: The figure represents a sequence of Bus cycles. If READYi# input is disabled, the external READYi# input has no effect on wait states for a local access. Wait states between Data cycles are generated internally by a wait state counter. Wait state counter is initialized with its Configuration register value at the start of each data access. If READYi# is enabled, READYi# has no effect until the wait state counter is 0. READYi# then controls the number of additional wait states. BTERM# input is not sampled until the wait state counter is 0. BTERM# overrides READYi# when BTERM# is asserted. 8 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 2 Bus Operation Local Bus Cycles 2.2.3.1.1 Wait State--Local Bus With Direct Master mode and accessing the PCI 9080 registers (PCI 9080 local as Slave): * PCI 9080 generates wait states with READYo# * Local processor generates wait states with WAITI# With Direct Slave and DMA modes (PCI 9080 Local Bus as Master): * The PCI 9080 generates wait states with WAITO# * Local processor generates wait states with READYi# * Use LBRD0[21:18, 5:2], DMAMODE0[5:2], and DMAMODE1[5:2] to program the number of wait states 2.2.3.1.2 Wait State--PCI Bus 2.2.3.2 Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode) Table 2-7. Burst and Bterm on the Local Bus Mode Burst Bterm Result Single Cycle 0 0 One ADS# per data (default) Single Cycle 0 1 Still one ADS# per data Burst-4 1 0 One ADS# per four data (use this mode for i960) Burst Forever 1 1 One ADS# per BTERM# On the Local Bus, BLAST# and BTERM# perform the following: * BTERM# input is valid only when the PCI 9080 is the Master of the Local Bus (Direct Slave or DMA modes). * BTERM# is generated by external logic. It is input to the PCI 9080 (and i960) and used to tell the PCI 9080 (and i960) to break up a Burst cycle. * BTERM# is used, for example, to signal that a Memory access is crossing the page boundary. On the PCI Bus, burst is always enabled. Notes: If Bterm is disabled, the PCI 9080 performs the following: * 32-bit Local Bus--Burst up to four Lwords * 16-bit Local Bus--Burst up to two Lwords * 8-bit Local Bus--Burst up to one Lword In every case, it performs four transactions. When the wait state occurs on the PCI Bus, Master throttles IRDY# and Slave throttles TRDY#. * * If burst is enabled (LBRD0[26,24] for non-DMA, DMAMODE0[8] and DMAMODE1[8] for DMA), but Bterm mode is disabled (LBRD0[7], DMAMODE0[7] and DMAMODE1[7]), then the PCI 9080 bursts four Lwords. BLAST# is generated at the fourth Lword (LA[3:2]=11), new ADS# at the first Lword (LA[3:2]=00) of the next burst. In the following sections, Bterm refers to the PCI 9080 Internal register bit. BTERM# refers to the PCI 9080 external signal. 2.2.3.2.1 Burst Mode If bursting is enabled and BTERM# input is not enabled, bursting can start on any boundary and continue up to an address boundary, as described in Table 2-8. After the data at the boundary is transferred, the PCI 9080 generates a new Address cycle (ADS#). Table 2-8. Burst Mode Bus Mode Burst C, J 32-bit bus--Four Lwords or up to a quad Lword boundary (LA3, LA2 = 11) C, J 16-bit bus--Four words or up to a quad word boundary (LA2, LA1 = 11) C, J 8-bit bus--Four bytes or up to a quad byte boundary (LA1, LA0 = 11) S 16-bit bus--Eight words or up to a quad Lword boundary (LA3, LA2 = 11) If BTERM# sampling is enabled and BTERM# is low, the PCI 9080 forces a new ADS#, but does not generate a new BLAST# signal. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 9 Section 2 Bus Operation Local Bus Cycles 2.2.3.2.2 Continuous Burst Mode (Bterm "Burst Terminate" Mode) Bterm mode enables the PCI 9080 to perform long bursts to devices that can accept longer than four Lword bursts. The PCI 9080 generates one Address cycle and continues to burst data. If a device requires a new Address cycle after a certain address boundary, it can assert BTERM# input to cause the PCI 9080 to generate a new Address cycle. BTERM# input acknowledges the current Data transfer and requests that a new Address cycle be generated (ADS#). This address is used for the next Data transfer. If Bterm mode is enabled, the PCI 9080 asserts BLAST# only if its FIFOs become full or empty, or if a transfer is complete. Note: If BTERM# is asserted, BLAST# does not assert until the previously described conditions are met. 2.2.3.2.3 Partial Lword Accesses Lword accesses in which not all byte enables are asserted are broken into Single Address and Data cycles, as listed in Table 2-9. Table 2-9. Partial Lword Accesses Register Value for LBRD0 For all Single Cycle Local Bus Read accesses, the PCI 9080 reads only bytes corresponding to byte enables requested by the PCI initiator. For all Burst Cycle Bus Read accesses, the PCI 9080 reads only Lwords. 2.2.3.5 Local Bus Write Accesses For Local Bus writes, only the bytes specified by a PCI Bus Master or the PCI 9080 DMA controller are written. Access to an 8- or 16-bit bus results in the PCI Bus Lword being broken into multiple Local Bus transfers. For each transfer, the byte enables are encoded as in the 80960C to provide Local Address bits LA[1:0]. 2.2.3.6 Direct Slave Write Accesses--8- and 16-Bit Buses A Direct PCI access to an 8- or 16-bit bus results in the PCI Bus Lword being broken into multiple Local Bus transfers. For each transfer, the byte enables are encoded as in the 80960C to provide Local Address bits LA[1:0]. Result Burst Enable Bterm Enable (Number of Transfers) 0 0 Single Cycle (Default) 0 1 Single Cycle 1 0 Burst four Lwords at a time 1 1 Continuous Burst Mode 2.2.3.3 Recovery States In J and S modes, the PCI 9080 inserts one recovery state between the last Data transfer and next Address cycle. The PCI 9080 does not support the 80960J feature of using READYi# input to add recovery states. No additional recovery states are added if READYi# input remains asserted during the last Data cycle. 10 2.2.3.4 Local Bus Read Accesses 2.2.3.7 Local Bus Data Parity There is one data parity pin for each byte lane of the PCI 9080 data bus (DP[3:0]). Even data parity is generated for each lane during Local Bus reads from the PCI 9080 and during PCI 9080 Master writes to the Local Bus. Even data parity is checked during Local Bus writes to the PCI 9080 and during PCI 9080 reads from the Local Bus. Parity is checked for each byte lane with an asserted byte enable. PCHK# is asserted in the Clock cycle following the data being checked if a parity error is detected. Generation or use of Local Bus data parity is optional. Signals on data parity pins do not affect operation of the PCI 9080. PCI Bus parity checking and generation is independent of Local Bus parity checking and generation. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 2 Bus Operation Local Bus Cycles 2.2.3.8 Local Bus Big/Little Endian Little Endian 31 PCI Bus is a Little Endian bus (that is, data is Lword aligned to the lowermost byte lane). Byte 0 (address 0) appears in AD[7:0], Byte 1 appears in AD[15:8], Byte 2 appears in AD[23:16] and Byte 3 appears in AD[31:24]. BYTE 3 BYTE 2 BYTE 1 0 BYTE 0 The PCI 9080 Local Bus can be programmed to operate in Big or Little Endian mode, as listed in Table 2-10. 31 Table 2-10. Big/Little Endian Program Mode BIGEND# Pin Register 1=Big, 0=Little Endian 0 0 Big 0 1 Big 1 0 Little 1 1 Big 0 BYTE 0 BYTE 1 BYTE 2 BYTE 3 Big Endian Figure 2-2. Big/Little Endian--32-Bit Local Bus 2.2.3.8.2 16-Bit Local Bus--Big Endian Mode For Configuration cycles, refer to BIGEND[0]. For Direct Master, Memory, and I/O cycles, refer to BIGEND[1]. For Direct Slave cycles, refer to BIGEND[2], Space 0, and BIGEND[3], Expansion ROM. For a 16-bit Local Bus, the PCI 9080 can be programmed to use the upper or lower word lane. Byte lanes and burst order are listed in Table 2-12 and Table 2-13 and illustrated in Figure 2-3. In Big Endian mode, the PCI 9080 transposes data byte lanes. Data is transferred as listed in Table 2-11 through Table 2-15. Table 2-12. Upper Word Lane Transfer 2.2.3.8.1 32-Bit Local Bus--Big Endian Mode Burst Order Byte Lane First Transfer Byte 0 appears on Local Data [31:24] Byte 1 appears on Local Data [23:16] Second Transfer Data is Lword aligned to the uppermost byte lane. Byte lanes and burst orders are listed in Table 2-11 and illustrated in Figure 2-2. Table 2-11. Upper Lword Lane Transfer Byte 3 appears on Local Data [23:16] Table 2-13. Lower Word Lane Transfer Burst Order First Transfer Burst Order Byte Lane First Transfer Byte 0 appears on Local Data [31:24] Byte 1 appears on Local Data [23:16] Byte 2 appears on Local Data [31:24] Byte Lane Byte 0 appears on Local Data [15:8] Byte 1 appears on Local Data [7:0] Second Transfer Byte 2 appears on Local Data [15:8] Byte 3 appears on Local Data [7:0] Byte 2 appears on Local Data [15:8] Byte 3 appears on Local Data [7:0] PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 11 Section 2 Bus Operation Local Bus Cycles Little Endian 31 BYTE 3 BYTE 1 BYTE 2 Little Endian 31 0 BYTE 3 BYTE 0 BYTE 2 0 BYTE 1 BYTE 0 First Cycle First Cycle Second Cycle BYTE 0 BYTE 1 31 15 Big Endian BYTE 1 31 15 31 7 BYTE 0 Big Endian 31 7 31 7 BYTE 0 Fourth Cycle 16 0 31 7 BYTE 0 Third Cycle BYTE 0 BYTE 0 Second Cycle 16 0 24 0 24 0 24 0 Big Endian 24 0 Figure 2-3. Big/Little Endian--16-Bit Local Bus Figure 2-4. Big/Little Endian--8-Bit Local Bus 2.2.3.8.3 8-Bit Local Bus--Big Endian Mode For an 8-bit Local Bus, the PCI 9080 can be programmed to use the upper or lower byte lane. Byte lanes and burst order are listed in Table 2-14 and Table 2-15 and illustrated in Figure 2-4. For each of the following transfer types, the PCI 9080 Local Bus can be independently programmed to operate in Little Endian or Big Endian mode: * Local Bus accesses to the PCI 9080 Configuration registers * Direct Slave PCI accesses to Local Address Space 0 * Direct Slave PCI accesses to Local Address Space 1 * Direct Slave PCI accesses to Expansion ROM * DMA Channel 0 accesses to the Local Bus * DMA Channel 1 accesses to the Local Bus * Direct Master accesses to PCI Bus Table 2-14. Upper Byte Lane Transfer Burst Order Byte Lane First transfer Byte 0 appears on Local Data [31:24] Second transfer Byte 1 appears on Local Data [31:24] Third transfer Byte 2 appears on Local Data [31:24] Fourth transfer Byte 3 appears on Local Data [31:24] Table 2-15. Lower Byte Lane Transfer Burst Order Byte Lane First Transfer Byte 0 appears on Local Data [7:0] Second Transfer Byte 1 appears on Local Data [7:0] Third Transfer Byte 2 appears on Local Data [7:0] Fourth Transfer Byte 3 appears on Local Data [7:0] For Local Bus Configuration accesses, an input pin can be used to dynamically change the Endian mode. Notes: The PCI Bus is always Little Endian mode. Only byte lanes are swapped, not individual bits. 12 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 3. FUNCTIONAL DESCRIPTION 3.1.3 Local Bus Input LRESETi# Functional operation described can be changed or modified, depending on the register configuration. When asserted, the LRESETi# input resets the Local Bus portion of the PCI 9080, clears all local configuration and DMA registers and causes LRESETo# output to be asserted. 3.1 Reset 3.1.4 Local Bus Output LRESETo# 3.1.1 PCI Bus Input RST# PCI Bus RST# input pin is a PCI Host reset. It causes all PCI Bus outputs to float, resets the entire PCI 9080 and causes the local reset output, LRESETo#, to be asserted. If you have a PCI Host (PCICR[2:0]), Master Enable, Memory Space, I/O Space is programmed by the host after initialization is complete (CNTRL[31]=1). (Refer to Figure 3-1.) PCI Reset Serial EEPROM Initialization Local Processor Sets CNTRL[3] Local Init = Done Local Processor Configures PCI 9080 Host Configures PCI 9080 LRESETo# is asserted when PCI Bus RST# input is asserted, the LRESETi# input is asserted, or the Software Reset bit in the Init Control register is set to 1. 3.1.5 Software Reset A host on the PCI Bus can set the software Software Reset bit in the Init Control register to reset the PCI 9080 and assert the LRESETo# output. All Local Configuration and DMA registers reset. PCI Configuration registers do not reset. When the Software Reset bit is set, the PCI 9080 responds to PCI accesses, but not to Local accesses. The PCI 9080 remains in this reset condition until the PCI Host clears the bit. Note: The Local Bus cannot clear this reset bit because the Local Bus is in a reset state. 3.2 PCI 9080 Initialization The PCI 9080 Configuration registers can be programmed by an optional serial EEPROM and/or by a Local processor, as listed in Table 3-1. The serial EEPROM can be reloaded by setting CNTRL[29]. Figure 3-1. Reset and Initialization Process In general, the PCI 9080 retries all PCI cycles until the Local Init Done bit is set or until NB# is low. 3.1.2 Software Reset LRESETo# Note: The PCI Host processor can also access the internal Configuration register after power-on. When asserted, the LRESETo# Software Reset CNTRL[30] resets the PCI 9080 Local Configuration and Local DMA registers. However, it does not reset the PCI Configuration and Shared Runtime registers. When the bit is set, the PCI 9080 responds to PCI accesses, but not to local accesses. The PCI 9080 remains in this condition until PCI Host clears the bit. The serial EEPROM is reloaded if CNTRL[29] is set. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 13 Section 3 Functional Description Table 3-1. NB# and Serial EEPROM Guidelines NB# Serial EEPROM Low No Boot with PCI 9080 default values. Programmed Boot with serial EEPROM values. Blank Not recommended (uses default values). High No System Boot Condition Local processor programs the PCI 9080 registers, then sets Local Init Status (CNTRL[31] = done). Note: Some systems hang if Direct Slave reads and writes take too long (during initialization, the PCI Host also performs Direct Slave accesses). Value of PCI Target Retry Delay Clocks (LBRD0[31:28]) may resolve this problem. Programmed Blank Load serial EEPROM, but Local processor can reprogram the PCI 9080. Load serial EEPROM (default values), but Local processor can reprogram the PCI 9080. The system can boot. Note: The serial EEPROM can be programmed through the PCI 9080 after system boots in this condition. Serial EEPROM 3.3 Serial EEPROM After reset, the PCI 9080 attempts to read the serial EEPROM to determine its presence. An active low start bit indicates the serial EEPROM is present (the PCI 9080 supports 93CS46 (1K) or 93CS56 (2K), selectable by way of the EESEL pin). (Refer to manufacturer's data sheet for particular serial EEPROM being used.) The first word is then checked to verify the serial EEPROM is programmed. If the first word (16 bit) is all ones, a blank serial EEPROM the PCI 9080 uses default values instead. The 5V serial EEPROM clock (EESK, pin 173) is derived from the PCI clock. The PCI 9080 generates the serial EEPROM clock by internally dividing the PCI clock by 32. The serial EEPROM can be read or programmed from the PCI or Local Bus. Bits [27:24] of the Serial EEPROM Control register (CNTRL[27:24]) control the PCI 9080 pins that enable the reading or writing of serial EEPROM data bits. (Refer to manufacturer's data sheet for particular serial EEPROM being used.) The PCI 9080 has three serial EEPROM load options: * Short Load Mode--SHORT# input pin is pulled down and the PCI 9080 loads five Lwords from the serial EEPROM * Long Load Mode--SHORT# input pin is pulled up, bit 25 of the Local Bus Region Descriptor Register is set to 0, and the PCI 9080 loads 17 Lwords from the serial EEPROM (LBRDO[25]) * Extra Long Load Mode--SHORT# input pin is pulled up, bit 25 of the Local Bus Region Descriptor Register is set to 1 during Long Load from the serial EEPROM, and the PCI 9080 loads 21 Lwords from the serial EEPROM (LBRDO[25]) 3.2.1 Serial EEPROM Initialization During serial EEPROM initialization, the PCI 9080 response to PCI Target accesses is Retry. During serial EEPROM initialization, the PCI 9080 response to a Local processor is to hold off READYo#. 3.2.2 Local Initialization The PCI 9080 issues a Retry to all PCI accesses until the Local Init Done bit in the Init Control register is set. The Init Done bit is programmable through Local Bus Configuration accesses. If this bit is not going to be set by a Local processor, then NB# input should be tied low. Holding NB# input low externally forces the Local Init Done bit to 1. The PCI 9080 default values are used if a serial EEPROM is not present and Local Init Status bit is set to 1 by holding the NB# input low or set by the Local processor. 14 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description Serial EEPROM 3.3.1 Short Serial EEPROM Load 3.3.2 Long Serial EEPROM Load The registers listed in Table 3-2 are loaded from serial EEPROM after reset is de-asserted if SHORT# pin is low. The serial EEPROM is organized in 16-bit words. The PCI 9080 first loads MSW (Most Significant Word; bits [31:16]), starting from the most significant bit [31]. The PCI 9080 then loads LSW (Least Significant Word; bits [15:0]), starting again from the most significant bit [15]. Therefore, the PCI 9080 loads Device ID, Vendor ID, class code, and so forth. The five 32-bit words are stored sequentially in the serial EEPROM. The registers listed in LBRD0 are loaded from serial EEPROM after reset is de-asserted if SHORT# pin is high. The serial EEPROM is organized in 16-bit words. The PCI 9080 first loads MSW (Most Significant Word; bits [31:16]), starting from the most significant bit [31]. The PCI 9080 then loads LSW (Least Significant Word; bits [15:0]), starting again from the most significant bit [15]. Therefore, the PCI 9080 loads Device ID, Vendor ID, class code, and so forth. Table 3-2. Short Serial EEPROM Load Registers Serial EEPROM Offset Description Sample Serial EEPROM Value 0h Device ID 9080 2h Vendor ID 10B5 4h Class Code 0680 6h Class Code, Revision 0002 8h Maximum Latency, Minimum Grant 0000 Ah Interrupt Pin, Interrupt Line Routing 0100 Ch MSW of Mailbox 0 (User Defined) xxxx Eh LSW of Mailbox 0 (User Defined) xxxx 10h MSW of Mailbox 1 (User Defined) xxxx 12h LSW of Mailbox 1 (User Defined) xxxx PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved The serial EEPROM value can be entered into a DATA I/O programmer in the order shown below. The values shown are examples and must be modified for each particular application. The 34 16-bit words listed in the table are stored sequentially in the serial EEPROM. 15 Section 3 Functional Description Serial EEPROM Table 3-3. Long Serial EEPROM Load Registers Serial EEPROM Offset 16 Description 0h Device ID 2h Vendor ID 4h Class Code 6h Class Code, Revision 8h Maximum Latency, Minimum Grant Ah Interrupt Pin, Interrupt Line Routing Ch MSW of Mailbox 0 (User Defined) Eh LSW of Mailbox 0 (User Defined) 10h MSW of Mailbox 1 (User Defined) 12h LSW of Mailbox 1 (User Defined) 14h MSW of Range for PCI-to-Local Address Space 0 16h LSW of Range for PCI-to-Local Address Space 0 18h MSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 1Ah LSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 1Ch MSW of Local Arbitration Register 1Eh LSW of Local Arbitration Register 20h MSW of Local Bus Big/Little Endian Descriptor Register 22h LSW of Local Bus Big/Little Endian Descriptor Register 24h MSW of Range for PCI-to-Local Expansion ROM 26h LSW of Range for PCI-to-Local Expansion ROM 28h MSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM 2Ah LSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM 2Ch MSW of Bus Region Descriptors for PCI-to-Local Accesses 2Eh LSW of Bus Region Descriptors for PCI-to-Local Accesses 30h MSW of range for Direct Master to PCI 32h LSW of range for Direct Master to PCI 34h MSW of Local Base Address for Direct Master to PCI Memory 36h LSW of Local Base Address for Direct Master to PCI Memory 38h MSW of Local Bus Address for Direct Master to PCI IO/CFG 3Ah LSW of Local Bus Address for Direct Master to PCI IO/CFG 3Ch MSW of PCI Base Address (Remap) for Direct Master to PCI 3Eh LSW of PCI Base Address (Remap) for Direct Master to PCI 40h MSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG 42h LSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description Internal Register Access 3.3.3 Extra Long Serial EEPROM Load An Extra Long Load mode is provided in the PCI 9080 (LBRDO) to load an additional five Lwords from the serial EEPROM. If bit 25 is set to 1 in the Local Bus Region Descriptor register (LBRDO), the following five Lword registers are loaded in addition to normal Long Load process (refer to Section 3.3.2, "Long Serial EEPROM Load"). Bit 25 must be set to 1 during the Long Load Process. (Refer to Table 3-4.) Note: The PCI 9080 does not support serial EEPROMs that do not support sequential read and write (such as the NM93C46 or NM93C56). 3.3.5 Programming the Serial EEPROM The serial EEPROM can be written or read, using bits [28:24] of the Serial EEPROM Control register (CNTRL[28:24]). 3.4 Internal Register Access Table 3-4. Extra Long Serial EEPROM Load Registers Description The PCI 9080 chip provides several Internal registers, allowing for maximum flexibility in bus interface design and performance. The register types are accessible from both the PCI and Local Buses, including the following: 44 Subsystem ID * PCI Configuration registers 46 Subsystem Vendor ID 48 MSW of Range for PCI-to-Local Address Space 1 (1 MB) * Local Configuration registers * Mailbox registers 4A LSW of Range for PCI-to-Local Address Space 1 (1 MB) * Doorbell registers 4C MSW of Local Base Address (Remap) for PCI-to-Local Address Space 1 * DMA registers 4E LSW of Local Base Address (Remap) for PCI-to-Local Address Space 1 * Messaging queue registers (I2O) 50 MSW of Bus Region Descriptors (Space 1) for PCI-to-Local accesses 52 LSW of Bus Region Descriptors (Space 1) for PCI-to-Local accesses 54 MSW of PCI Base Address for Local Expansion ROM 56 Figure 3-2 illustrates how these registers are accessed. PCI Bus Master Local Bus Master PCI 9080 PCI Configuration Registers LSW of PCI Base Address for Local Expansion ROM Local Configuration Registers A 1K-bit (National NM93CS46 or compatible) or 2K-bit (National NM93CS56 or compatible) device can be used. Table 3-5 lists the recommended serial EEPROM loads. Refer also to Table 5-2 in Section 5, "Pin Description." PCI Interrupt 3.3.4 Recommended Serial EEPROMs DMA Registers Mailbox Registers Set Clear PCI-to-Local Doorbell Register LocalPCI -toDoorbell Register Clear Local Interrupt Serial EEPROM Offset Set Table 3-5. Recommended Serial EEPROM Loads Load Unused Bytes for CS46 (1K bit) Unused Bytes for CS56 (2K bit) Short 108 236 Long 60 188 Extra Long 40 168 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Messaging Queue Registers Figure 3-2. PCI 9080 Internal Register Access 17 Section 3 Functional Description 3.4.1 PCI Bus Access to Internal Registers The PCI 9080 PCI Configuration registers can be accessed from the PCI Bus with a Type 0 Configuration cycle. The PCI 9080 Internal registers can be accessed by a Memory cycle, with the PCI Bus address that matches the base address specified in the PCI Base Address 0 for Memory-Mapped Configuration register of the PCI 9080. They can also be accessed by an I/O cycle, with the PCI Bus address matching the base address specified in the PCI Base Address 1 for the I/O-Mapped Configuration register of the PCI 9080. Internal Register Access All Local Read or Write accesses to the PCI 9080 registers can be Byte, Word, or Lword accesses. All Local accesses to the PCI 9080 registers can be Burst or Non-burst. For C and J modes, accesses must be for a 32-bit nonpipelined bus. The PCI 9080 READYo# indicates a Data transfer is complete. For S mode, accesses must be for a 16-bit nonpipelined bus. The PCI 9080 READYo# indicates a Data transfer is complete. Address Decode Mode Pin 1 All PCI Read or Write accesses to the PCI 9080 registers can be Byte, Word, or Lword accesses. All PCI Memory accesses to the PCI 9080 registers can be Burst or Non-burst. The PCI 9080 responds with a PCI Disconnect for all Burst I/O accesses to the PCI 9080 registers. LA31 LA30 PCI 9080 0 S2 compare PCI 9080 S0 S1 LA29 (PCI 9080 Chip Select) S0 = 3.4.2 Local Bus Access to Internal Registers The Local processor can access all the Internal registers of the PCI 9080 through either internal or external address decode logic. The PCI 9080 provides an Address Decode Mode Pin (ADMODE) that selects whether the internal address decode logic is used or the designer supplies an external chip select from an external address decoder. Figure 3-3 illustrates how dual address decode logic works. PCI 9080 Internal Register Chip Select PCI 9080 Internal Register Chip Select Figure 3-3. Dual Address Decode Mode If the Address Decode Mode pin is set to 1, internal PCI 9080 address decode logic is enabled. In this mode, the PCI 9080 Internal registers are selected when Local Address bits LA[31:29] match input address select pins S[2:0]. If the Address Decode Mode pin is set to 0, the PCI 9080 responds to Local Bus access when S0 is asserted low through external chip select logic. Notes: S0 must be decoded while ADS# is low. If ADMODE is 1 LA[31:29], specify 512 MB of Local Memory space allocated for accessing Internal registers. 18 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description Response to Full and Empty FIFOs 3.5 Response to Full and Empty FIFOs Table 3-6 lists the response of the PCI 9080 to full and empty FIFOs. Table 3-6. Response to Full and Empty FIFOs Mode Direction FIFO Direct Master Write Local-to-PCI Full Direct Master Read PCI-to-Local Direct Slave Write PCI-to-Local Empty Full Empty Direct Slave Read Local-to-PCI Local-to-PCI PCI-to-Local De-assert REQ# (off PCI Bus) No action De-assert REQ# or throttle IRDY# No action No action De-assert READYo# No action Empty No action De-assert LHOLD, assert BLAST# (see Note) Full No action De-assert LHOLD, assert BLAST# (see Note) Full Throttle TRDY# No action No action De-assert LHOLD, assert BLAST# Empty De-assert REQ# No action Full De-assert REQ# No action No action De-assert LHOLD, assert BLAST# Empty Note: Local Bus De-assert READYo# Disconnect or throttle TRDY# Full Empty DMA PCI Bus No action De-assertion of LHOLD depends on MARBR[21]. 3.6 Direct Data Transfer Modes PCI Bus Figure 3-4 and Figure 3-5 illustrate the direct Data Transfer modes. Refer also to Table 3-6 for responses to full and empty FIFOs. Local Bus Mailbox registers can be read and/or written from both sides Mailbox 0 Mailbox 1 Host CPU PLX or System Chipset Physical System Memory Local Bus Doorbell registers set and clear interrupts Set Clear PCI-to-Local Clear Local-to-PCI Set Mailbox 2 Mailbox 3 Mailbox 4 Mailbox 5 PCI Bus PCI Bus Used for Passing * Commands * Pointers * Status Mailbox 6 Local Memory or I/O PLX * Address Translation * DMA, Memory, I/O Cycles * Interrupts * Software Protocol Local CPU Mailbox 7 Figure 3-5. Mailbox/Doorbell Message Passing Host CPU accesses Local Memory or I/O = Direct Slave read/write Local CPU accesses System Memory = Direct Master read/write PCI 9080 read/write from System Memory and write/read to Local memory = DMA read/write Figure 3-4. Direct Master, Direct Slave, and DMA PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 19 Section 3 Functional Description * Local Base Address for Direct Master to PCI Memory Register * Local Base Address for Direct Master to PCI IO/CFG Register * PCI Configuration Address Register for Direct Master to PCI IO/CFG * PCI Base Address 3.6.1.1 Decode The Range register specifies the Local Address bits to use for decoding a Local-to-PCI access. The Local processor can perform only Memory cycles. Therefore, the Local Base Address for Direct Master to PCI Memory register is used to decode an access to PCI memory space. The Local Base Address for Direct Master to PCI IO/CFG register is used to decode an access to PCI I/O space or PCI Bus Configuration cycle access. GNT# PCI 9080 FRAME#, C/BE# AD (addr) IRDY# DEVSEL#, TRDY# AD (data) Figure 3-6. Direct Master Write Slave Master LA, ADS#, LW/R# REQ# GNT# FRAME#, C/BE#, AD (addr) IRDY# PCI 9080 LD, READYo# 3.6.1.2 FIFOs 20 Master Slave DEVSEL#, TRDY#, AD (data) For Direct Master Memory access to the PCI Bus, the PCI 9080 has a 32-Lword (128 byte) Write FIFO and a 16-Lword (64 byte) Read FIFO. The FIFOs enable the Local Bus to operate independently of the PCI Bus and allows high-performance bursting on the Local and PCI Buses. In a Direct Master Write, the Local processor (Master) writes data to the PCI (Slave). In a Direct Master Read, the Local processor (Master) reads data from the PCI (Slave). Figure 3-6 and Figure 3-7 illustrate the FIFOs during a Direct Master Write and Read. Local Bus Range READYo# REQ# Local Bus * Master Slave Master LA, ADS#, LBE#, LD, LW/R#, BLAST# PCI Bus The PCI 9080 supports direct access of the PCI Bus by the Local processor or an intelligent controller. Master mode must be enabled in the PCI Command register. Five registers are used to define Local-to-PCI access: Slave PCI Bus 3.6.1 Direct Master Operation (Local Master to PCI Target) Direct Data Transfer Modes BLAST# Figure 3-7. Direct Master Read Note: The figures represent a sequence of Bus cycles. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description Direct Data Transfer Modes 3.6.1.3 Memory Access 3.6.1.5 I/O The Local processor can read or write to the PCI memory. The PCI 9080 converts the Local Read/Write access. The Local Address space starts from the Direct Master Local Base Address up to the range. Remap (PCI Base Address) defines the PCI starting address. If the Configuration Enable bit is clear, a single I/O access is made to the PCI Bus. The Local Address, remapped decode address bits and the local byte enables are encoded to provide the address and is output with an I/O Read or Write command during the PCI Address cycle. Writes--The PCI 9080 continues to accept writes and returns READYo# until the Write FIFO is full. It then holds off READYo# until space becomes available in the Write FIFO. A programmable Direct Master FIFO "almost full" status output is provided (DMPAF#). For writes, data is loaded into the Write FIFO and READYo# returned to the Local Bus. For reads, the PCI 9080 holds off READYo# while gathering an Lword from the PCI Bus. Reads--The PCI 9080 holds off READYo# while gathering an Lword from the PCI Bus. Programmable Prefetch modes are available if prefetch is enabled: prefetch, 4, 8, 16, or continuous until the Direct Master cycle ends. The Read cycle is terminated when the Local BLAST# input is asserted. Unused Read data is then flushed from the FIFO. The PCI 9080 does not prefetch Read data for Single Cycle Direct Master reads (Local BLAST# input asserted during first Data phase). In this case, the PCI 9080 reads a single PCI Lword. For Direct Master Single Cycle reads, the PCI 9080 asserts the same PCI Bus byte enables as asserted on the Local Bus. For Multiple Cycle reads, the PCI 9080 reads entire Lwords (all PCI byte enables are asserted), regardless of local byte enables. If the Prefetch Limit bit DMPBAM[11] is enabled, the PCI 9080 does not prefetch past a 4 KB boundary. Also, the Local Bus must not cross a 4 KB boundary during a Burst read. The PCI 9080 never prefetches beyond the region specified for Direct Master accesses. 3.6.1.4 IO/CFG Access When the I/O Remap Select bit is set to a value of 1, these PCI Address bits [31:16] are forced to a value of 0 (DMPBAM[13]). 3.6.1.6 CFG (PCI Configuration Type 0 or Type 1 Cycles) If the Configuration Enable bit is set, a CFG access is made to the PCI Bus. In addition to enabling the Configuration bit of DMCFGA[31], the user must provide all register information. The register number (bits [7:2]) or the device number (bits [15:11]) must be modified and a new CFG Read/Write cycle must be performed before other registers or devices can be accessed. If the PCI Configuration Address register selects a Type 0 command, bits [10:0] from the register are copied to address bits [10:0]. Bits [15:11] (device number) are translated into a single bit being set in PCI Address bits [31:11]. PCI Address bits [31:11] can be used as a device select. For a Type 1 command, bits [23:0] are copied from the register to bits [23:0] of the PCI Address. PCI Address bits [31:24] are 0. A Configuration Read or Write command code is output with the address during the PCI Address cycle (DMCFGA). For writes, Local data is loaded into the Write FIFO and READYo# is returned. For reads, the PCI 9080 holds off READYo# while gathering an Lword from the PCI Bus. When a Local Direct Master I/O access to the PCI Bus is made, the Configuration Enable bit of the PCI Configuration Address register determines if I/O or Configuration access is to be made to the PCI Bus. Local Burst accesses are broken into Single PCI I/O Address/Data cycles. The PCI 9080 does not prefetch Read data for I/O and CFG reads. For Direct Master I/O or Configuration cycles, the PCI 9080 asserts the same PCI Bus byte enables as asserted on the Local Bus. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 21 Section 3 Functional Description Example 1--To perform a Type 0 Configuration cycle to PCI device on AD[21]: 1. The PCI 9080 must be configured to allow Direct Master access to the PCI Bus. The PCI 9080 must also be set to respond to I/O Space accesses. Set PCICR[2,0] as follows: * Bit 0 = I/O Space = 1 * Bit 2 = Master Enable = 1 2. The board designer selects the Direct Master range. For this example, use a range of 1 MB: * DMRR = FFF00000h 3. The board designer determines local Base Address for Direct Master to PCI IO/CFG. For this example, use 40000000h: * DMLBAI = 40000000h 4. The PCI Address (Remap) for Direct Master to PCI Memory register must enable Direct Master I/O access. Set DMPBAM[1] as follows: * Bit 1 = Direct Master I/O Access Enable = 1 5. The PCI Bus must know which PCI device and PCI Configuration register the PCI Configuration cycle is accessing. For this example, access the PCI device on AD[21], as well as PCIBAR0, the PCI Base Address 0 for Memory-Mapped Configuration register (the fourth register, counting from 0--use Table 4-5, "PCI Configuration Registers," for reference). Set DMCFGA[31, 23:0] as follows: 22 The Register Number (bits [7:2]) or Device Number (bits [15:11]) must be modified and a new CFG Read/Write cycle must be performed before other registers or devices can be accessed. 3.6.1.7 Direct Bus Master Lock The PCI 9080 supports direct Local-to-PCI Bus exclusive accesses (locked atomic operations). A locked operation must start with the Local Bus input LLOCK# being asserted during a Direct Master Bus Read cycle. Refer to the timing in Section 8, "Timing Diagrams." 20 1 MB = 2 = 000FFFFFh The value to program into the range register is the inverse of 000FFFFFh, which is FFF00000h: * Direct Data Transfer Modes * Bits 1:0 = Configuration Type 0 = 00b * Bits 7:2 = Register Number = The fourth register, and therefore must program a 4 into this bit, beginning with bit 2 = 000100b * Bits 10:8 = Function Number = 000b * Bits 15:11 = Device Number = n-11, where n is the value in AD[n]=21-11 = 10 = 01010b * Bits 23:16 = Bus Number = 00000000b * Bit 31 = Configuration Enable = 1 3.6.1.8 Master/Target Abort The PCI 9080 Master/Target abort logic enables a Local Bus Master to perform a Direct Master Bus poll of devices to determine whether the devices exist (typically when the Local Bus performs Configuration cycles to the PCI Bus). If a PCI Master, Target Abort, or Retry Time-out is encountered during a transfer, the PCI 9080 asserts LSERR# if enabled (INTCSR[1:0]) (can be used as an NMI). If the Local Bus Master is waiting for a READYo#, it is asserted along with BTERMo#. The Local Master's interrupt handler can take the appropriate application specific action. It can then clear the Abort bits in the PCI Status Configuration register (PCISR) to clear the LSERR# interrupt and re-enable Direct Master transfers. If a Local Bus Master is attempting a Burst read from a nonresponding PCI device (Master/Target abort), it receives the READYo# and BTERMo# for the first cycle only. If the Local processor cannot terminate its Burst cycle, it may cause the Local processor to hang. The Local Bus must then be reset from the PCI Bus or by a local watchdog timer asserting RESETi#. If the Local Bus Master cannot terminate its cycle with BTERMo#, it should not perform Burst cycles when attempting to determine whether a PCI device exists. 3.6.1.9 Write and Invalidate The PCI 9080 can be programmed to perform Write and Invalidate cycles to the PCI for DMA and Direct Master transfers. The PCI 9080 supports Write and Invalidate transfers for cache line sizes of 8 or 16 Lwords. The size is specified in the PCI Cache Line Size register. If a size other than 8 or 16 is specified, the PCI 9080 performs Write transfers rather than Write and Invalidate transfers. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Direct Data Transfer Modes Section 3 Functional Description 3.6.1.9.1 DMA Write and Invalidate 3.6.1.9.2 Direct Master Write and Invalidate DMA Write and Invalidate transfers are enabled when the Write and Invalidate Enable bit of a DMA controller is set in its Mode register and the Memory Write and Invalidate Enable bit is set in the PCI Command register. Direct Master Write and Invalidate transfers are enabled when the Invalidate Enable bit is set in the PCI Base Address (Remap) register for Direct Master to PCI Memory and the Memory Write and Invalidate Enable bit is set in the PCI Command register (PCICR). In Write and Invalidate mode, the PCI 9080 waits until the number of Lwords required for the specified cache line size have been read from the Local Bus before starting the PCI access. This ensures that a complete cache line write can be completed in one PCI Bus ownership. If a Target disconnects before a cache line is completed, the PCI 9080 completes the remainder of that cache line using normal writes before resuming Write and Invalidate transfers. If a Write and Invalidate cycle is in progress, the PCI 9080 continues to burst if another cache line has been read from the Local Bus before the cycle completes. Otherwise, the PCI 9080 terminates the burst and waits for the next cache line to be read from the Local Bus. If the final transfer is not a complete cache line, the PCI 9080 completes the DMA transfer, using normal writes. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved In Write and Invalidate mode, if the start address of the Direct Master transfer is on a cache line boundary, the PCI 9080 waits until the number of Lwords required for specified cache line size have been written from the Local Bus before starting PCI Write and Invalidate access. This ensures that a complete cache line write can be completed in one PCI Bus ownership. If the start address is not on a cache line boundary, the PCI 9080 starts a normal PCI Write access. The PCI 9080 terminates a cycle at a cache line boundary if it is performing a normal write or if it is performing a Write and Invalidate cycle and another cache line of data is not available. If an entire cache line is available by the time the PCI 9080 regains use of the PCI Bus, the PCI 9080 resumes Write and Invalidate cycles. Otherwise, it continues with a normal write. If a Target disconnects before a cache line is completed, the PCI 9080 completes the remainder of that cache line using normal writes. 23 Section 3 Functional Description Direct Data Transfer Modes Local Processor PCI Bus Master 1 Initialize Local Direct Master Access Registers Local Range for Direct Master to PCI Local Base Address for Direct Master to PCI Memory PCl Base Address (Remap) for Direct Master to PCI CFG or I/O 0 = I/O 1 = CFG Local Base Address for Direct Master to PCI IO/CFG CFG Type if CFG Enabled PCI CFG Address Register for Direct Master to PCI IO/CFG PCI Command Register 3 2 PCI Bus Access Local Bus Access FIFOs 32 LW Deep Write 16 LW Deep Read Local Base Address for Direct Master to PCI Memory Space Bit 13 = 1 PCI I/O LA[31:16] = 0 Local Base Address for Direct Master to PCI Memory Space Local Memory Range Memory Command PCI Base Address Local Base Address for Direct Master to PCI IO/CFG I/O Command Range PCI Address Space PCI CFG Command Type 0 or 1 CFG Address Register 0 = I/O 1 = CFG Figure 3-8. Local Master Direct Master Access of PCI Bus 24 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description Direct Data Transfer Modes 3.6.2 Direct Slave Operation (PCI Master to Local Bus Access) The PCI 9080 supports both Burst Memory-Mapped Transfer accesses and I/O-Mapped, Single-Transfer accesses to the Local Bus from the PCI Bus. PCI Base Address registers are provided to set up the location of the adapter in PCI memory and I/O space. In addition, local mapping registers allow address translation from PCI Address space to Local Address Space. Three spaces are available: * Space 0 * Space 1 * Expansion ROM space Expansion ROM space is intended to support a bootable ROM device for the host. Each Local space can be programmed to operate 8-, 16, or 32-bit Local Bus width. The PCI 9080 has an internal wait state generator and external wait state input, READYi#, which can be disabled or enabled with the Internal Configuration register. The Local Bus, independent of the PCI Bus, can: * Burst as long as data is available Continuous Burst (mode) * Burst four Lwords at a time * Perform continuous single cycle, with or without wait state(s) For Single Cycle Direct Slave reads, the PCI 9080 reads a single Local Bus Lword or partial Lword. The PCI 9080 disconnects after one transfer for all Direct Slave I/O accesses. For the highest Data transfer rate, the PCI 9080 supports posted writes and can be programmed to prefetch data during PCI Burst reads. The prefetch size, when enabled, can be from one to 16 Lwords, or until the PCI stops requesting. The PCI 9080 prefetches, if enabled, and drops the Local Bus after the Prefetch Counter is reached. In Continuous Prefetch mode, the PCI 9080 prefetches as long as any FIFO space is available and terminates the prefetch when the PCI terminates the request. If Read prefetching is disabled, the PCI 9080 disconnects after one Read transfer. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 3.6.2.1 PCI 2.1 Mode The PCI 9080 can be programmed through the Local Arbitration and PCI Mode register to perform delayed reads, as specified in PCI Specification v2.1. Local Bus PCI Bus PCI Read request PCI 9080 tells Host to "Retry" Read cycle later PCI Bus is free to perform other cycles during this time PCI host returns to fetch Read data again Read data is now ready for the Host Spec v2.1 mode set in Internal registers Data stored in 16 Lword Internal FIFO PCI 9080 requests Read data from Local Bus Local memory returns requested data to PCI 9080 PCI 9080 returns prefetched data immediately Figure 3-9. PCI Specification v2.1 Delayed Reads Note: The figure represents a sequence of Bus cycles. In addition to delayed read, the PCI 9080 supports the following PCI Specification v2.1 features: * No write while read is pending (Retry for reads) * Write and flush pending read The PCI 9080 also supports Read Ahead mode (refer to Figure 3-10), where prefetched data can be read from the internal PCI 9080 FIFO instead of from the Local Bus. The address must be subsequent to the previous address and must be 32-bit aligned (next address = current address + 4). 25 Section 3 Functional Description Direct Data Transfer Modes Local Bus PCI Bus Master Slave Slave Master PCI 9080 PCI 9080 prefetches data from Local Bus device IRDY#, AD (data) Read data PCI Master read returns with "Sequential Address" Read data FRAME#, C/BE#, AD (addr) Prefetched data stored in Internal FIFO PCI 9080 returns prefetched data immediately from Internal FIFO without reading again from Local Bus DEVSEL#, TRDY# PCI 9080 LHOLD LHOLDA Local Bus Read Ahead mode set via Internal register PCI Bus PCI Read request LA, ADS#, LW/R# PCI 9080 prefetches more data if FIFO space is available LD, BLAST# READYi# PCI 9080 prefetches more data from Local memory Figure 3-11. Direct Slave Write Master Note: The figure represents a sequence of Bus cycles. For Direct Slave writes, the PCI (Master) writes data to the Local Bus (Slave). Direct Slave is the "Command from the PCI Host," which has the highest priority. Direct Slave or Direct Master pre-empts DMA; however, Direct Slave does not pre-empt Direct Master (refer to Section 3.6.2.3.1, "Backoff"). Slave Master FRAME#, C/BE#, AD (addr) IRDY# PCI Bus The PCI 9080 can be programmed to keep the PCI Bus by generating a wait state(s), thereby de-asserting TRDY#, if the Write FIFO becomes full. The PCI 9080 can also be programmed to keep the Local Bus, thereby asserting LHOLD, if the Direct Slave Write FIFO becomes empty or the Direct Slave Read FIFO becomes full. The Local Bus is dropped in either case when the Local Bus Latency Timer is enabled and expires. (Refer to Figure 3-11 and Figure 3-12.) Slave DEVSEL# PCI 9080 LHOLD LHOLDA Local Bus Figure 3-10. PCI 9080 Read Ahead Mode LA, ADS#, LW/R#, BLAST# READYi#, LD TRDY#, AD (data) Figure 3-12. Direct Slave Read Note: The figures represent a sequence of Bus cycles. For Direct Slave reads, the PCI (Master) reads data from the Local Bus (Slave). The PCI 9080 supports on-the-fly Endian conversion for Space 0, Space 1, and Expansion ROM space. The Local Bus can be Big/Little Endian by either using the BIGEND# input pin or the programmable internal register configuration. When BIGEND# is asserted, it overrides the internal register configuration. Note: 26 The PCI Bus is always Little Endian. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description Direct Data Transfer Modes 3.6.2.2 PCI-to-Local Address Mapping 8-Bit Bus--For an 8-bit bus, BE1# and BE0# are encoded to provide LA1 and LA0, respectively. Note: Not applicable if I2O mode. * BE3# not used Three Local Address spaces--Space 0, Space 1, and Expansion ROM--are accessible from the PCI Bus. Each is defined by a set of three registers: * BE2# not used * BE1# Address bit 1 (LA1) * Local Address Range * BE0# Address bit 0 (LA0) * Local Base Address * PCI Base Address Each PCI-to-Local Address space is defined as part of reset initialization as described in the next section. A fourth register, Bus Region Descriptor for PCI-to-Local Accesses, defines the Local Bus characteristics for both regions (refer to Figure 3-13). 3.6.2.2.1 Byte Enables LBE[3:0]# (pins 139-142) are encoded based on the configured bus width, as follows: 32-Bit Bus--For a 32-bit bus, the four byte enables indicate which of the four bytes are active during a Data cycle. * BE3# Byte Enable 3--LD[31:24] * BE2# Byte Enable 2--LD[23:16] * BE1# Byte Enable 1--LD[15:8] * BE0# Byte Enable 0--LD[7:0] 16-Bit Bus--For a 16-bit bus, BE3#, BE1# and BE0# are encoded to provide BHE#, LA1, and BLE#, respectively. * BE3# Byte High Enable (BHE#)--LD[15:8] * BE2# not used * BE1# Address bit 1 (LA1) * BE0# Byte Low Enable (BLE#)-- LD[7:0] PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 3.6.2.2.2 Local Bus Initialization Software Range--Specifies which PCI Address bits to use for decoding a PCI access to Local Bus space. Each Prefetch Limit bit corresponds to a PCI Address bit. Bit 31 corresponds to Address bit 31. Write 1 to all bits that must be included in decode and 0 to all others. Remap PCI-to-Local Addresses into a Local Address Space--Bits in this register remap (replace) the PCI Address bits used in decode as the Local Address bits. Local Bus Region Descriptor--Specifies the Local Bus characteristics. 3.6.2.2.3 PCI Initialization Software PCI reset software determines how much address space is required by writing a value of all ones (1) to a PCI Base Address register and then reading back the value. The PCI 9080 return zeroes in Don't Care Address bits, effectively specifying the address space required. The PCI software then maps the Local Address space into the PCI Address space by programming the PCI Base Address register. (Refer to Figure 3-13.) 27 Section 3 Functional Description Direct Data Transfer Modes Local Processor PCI Bus Master 1 Initialize Local Direct Access Registers 2 Initialize PCI Base Address Registers Range for PCI-to-Local Address Space 0 Local Base Address (Remap) for PCI-to-Local Address Space 0 Bus Region Descriptors for PCI-to-Local Accesses Range for PCI-to-Local Expansion ROM Local Base Address (Remap) for PCI-to-Local Expansion ROM Bus Region Descriptors for PCI-to-Local Accesses Local Bus Hardware Characteristics PCI Base Address to Local Address Space 0 PCI Base Address to Local Expansion ROM 3 4 PCI Bus Access Local Bus Access FIFOs 32 LW Deep Write 16 LW Deep Read PCI Address Space PCI Base Address Local Memory Local Base Address Range Figure 3-13. Direct Slave Access of Local Bus 28 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description Direct Data Transfer Modes Example 2--A 1 MB Local Address Space 12300000h through 123FFFFFh is accessible from the PCI Bus at PCI Addresses 78900000h through 789FFFFFh. a. Local initialization software sets the Range and Local Base Address registers, as follows: * * Range--FFF00000h (1 MB, decode the upper 12 PCI Address bits) Local Base Address (remap)--123XXXXXh (Local Base Address for PCI-to-Local accesses) (bit 0, the Space Enable bit, must be set to 1 to be recognized by the Host) b. PCI Initialization software writes all ones to the PCI Base Address, then reads it back again. * The PCI 9080 returns a value FFF00000h. The PCI software then writes to PCI Base Address register * PCI Base Address--789XXXXXh (PCI Base Address for access to Local Address Space) For PCI direct access to the Local Bus, the PCI 9080 has a 32-Lword (128 byte) Write FIFO and a 16-Lword (64 byte) Read FIFO. The FIFOs enable the Local Bus to operate independently of the PCI Bus. The PCI 9080 can be programmed to return a Retry response or to throttle TRDY# for any PCI Bus transaction attempting to write to the PCI 9080 Local Bus when the FIFO is full. For PCI Read transactions from the PCI 9080 Local Bus, the PCI 9080 holds off TRDY# while gathering the Local Bus Lword to be returned. For Read accesses mapped to the PCI memory space, the PCI 9080 prefetches up to 16 Lwords (has Continuous Prefetch mode) from the Local Bus. Unused Read data is flushed from the FIFO. For Read accesses mapped to the PCI I/O space, the PCI 9080 does not prefetch Read data. Rather, it breaks each read of the Burst cycle into a Single Address/Data cycle on the Local Bus. 3.6.2.3 Deadlock and BREQo Deadlock can occur when a Master on the PCI Bus wants to access the PCI 9080 Local Bus at the same time a Master on the PCI 9080 Local Bus requires access to the PCI Bus. Two types of deadlock situations can occur: * Partial Deadlock--Master on Local Bus is performing a direct Bus Master access to a PCI Bus device other than the PCI Bus device concurrently trying to access the Local Bus. * Full Deadlock--Master on Local Bus is performing a direct Bus Master access to the same PCI Bus device concurrently trying to access the Local Bus. This applies only to Direct ("pass through") Master and Slave accesses through the PCI 9080. Deadlock does not occur in transfers through the PCI 9080 DMA controller or the mailboxes. For partial deadlock, the PCI access to the Local Bus times out (the Target Retry Timer, which is programmable through the Local Bus Region Descriptor register for PCI-to-Local accesses) and the PCI 9080 responds with a PCI Retry. PCI specification requires that a PCI Master release its request for the PCI Bus (de-asserts REQ#) for a minimum of two PCI clocks after receiving a Retry. This allows the PCI Bus arbiter to grant the PCI Bus to the PCI 9080 so that it can complete its Direct Master access and free up the Local Bus. Possible solutions are described below for cases in which the PCI Bus arbiter does not function as described (PCI Bus architecture dependent), waiting for a time-out is undesirable, or a full deadlock condition exists. For full deadlock, the only solution is to back off the Local Master. The period of time the PCI 9080 holds off TRDY# can be programmed (the Target Retry Timer) in the Local Bus Region Descriptor register (LBRD0). The PCI 9080 issues a Retry to the PCI Bus transaction Master when the programmed time period expires. This occurs when the PCI 9080 cannot gain control of the Local Bus and return TRDY# within the programmed time period. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 29 Section 3 Functional Description 3.6.2.3.1 Backoff The PCI 9080 contains a pin (BREQo) that indicates a possible deadlock condition exists. The PCI 9080 starts the BREQo timer (programmable through registers) when it detects the following conditions: * A Master on the PCI Bus is trying to access memory or an I/O device on the Local Bus and is not gaining access (for example, LHOLDA not received). * A Master on the Local Bus is performing a direct Bus Master Read access to the PCI Bus or a Master on the Local Bus is performing a direct Bus Master Write access to the PCI Bus and the PCI 9080 Direct Master Write FIFO cannot accept another Write cycle. If the timer expires and the PCI 9080 has not received the LHOLDA signal, the PCI 9080 asserts BREQo. External bus logic can use this as a signal to perform Backoff. A Backoff cycle is device/bus architecture dependent. External logic (arbiter) can assert the necessary signals to cause the Local Master to release the Local Bus (Backoff). After backing off the Local Master, it can grant the bus to the PCI 9080 (by asserting LHOLDA). Once BREQo is asserted, READYo# for the current Data cycle is never asserted (the Local Bus Master must perform Backoff). When the PCI 9080 detects LHOLDA, It proceeds with the PCI Master to Local Bus access. When this access is complete and the PCI 9080 releases the Local Bus, the external logic can release Backoff and the Local Master can resume the cycle interrupted by the Backoff cycle. The Write FIFO of the PCI 9080 retains all the data it has acknowledged (that is, the last data for which READYo# was asserted). After the Backoff condition ends, the Local Master restarts the last cycle with ADS#. For writes, the data following this ADS# should be the data that was not acknowledged by the PCI 9080 prior to the Backoff cycle (for instance, the last data for which there was no READYo# asserted). If a PCI Read cycle is completed when the Local Bus is backed off, the Local Bus Master receives that data if Local Master restarts the same last cycle (data is not read twice). A new read is performed, if the resumed Local Bus cycle is not the same as the backed-off cycle. 30 Direct Data Transfer Modes 3.6.2.3.2 Software/Hardware Solution for Systems without Backoff Capability For adapters that do not support Backoff, a possible deadlock solution is as follows. PCI Host software, external Local Bus hardware, general purpose output USERO and general purpose input (USERI) can be used by PCI Host software to prevent deadlock. USERO can be set to request that the external arbiter not grant the bus to any Local Bus Master except the PCI 9080. A status output from the local arbiter can be connected to general-purpose input USERI to indicate that no Local Bus Master owns the Local Bus. The PCI Host to determine that no Local Bus Master currently owns the Local Bus can read the input. PCI Host can then perform a Direct Slave access. When the host is done, it clears USERO. For devices that support pre-empt, USERO can be used to pre-empt the current Bus Master device. The current Local Bus Master device completes its current cycle and gives up the Local Bus (de-asserts LHOLD). 3.6.2.3.3 Software Solutions to Deadlock PCI Host software and Local Bus software can use a combination of mailbox registers, doorbell registers, interrupts, direct Local-to-PCI accesses and direct PCI-to-Local accesses to avoid deadlock. 3.6.2.4 Direct Slave Lock The PCI 9080 supports direct PCI-to-Local Bus exclusive accesses (locked atomic operations). A PCI locked operation to Local Bus results in the entire address Space 0, Space 1 and Expansion ROM space being locked until they are released by the PCI Bus Master. The PCI 9080 asserts LLOCKo# during the first clock of an atomic operation (Address cycle) and deasserts it a minimum of one clock, following the last Bus access for the atomic operation. LLOCKo# is deasserted after the PCI 9080 detects PCI FRAME# and PCI LOCK# de-asserted at the same time. Refer to the timing diagrams in Section 8, "Timing Diagrams." Locked operations are enabled or disabled with the Local Bus Region Descriptor register for PCI-to-Local accesses. It is the responsibility of external arbitration logic to monitor the LLOCKo# pin and enforce the meaning for an atomic operation. For example, if a Local Master initiates a locked operation, the local arbiter may choose to not grant use of the Local Bus to other Masters until the locked operation is complete. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description DMA Operation 3.6.3 Direct Slave Priority 3.7 DMA Operation Direct Slave accesses have higher priority than DMA accesses. The PCI 9080 supports two independent DMA channels capable of transferring data from the Local Bus to the PCI Bus or from the PCI Bus to the Local Bus. Each channel consists of a DMA controller and a programmable FIFO. Both channels support Chaining and Non-chaining transfers, Demand mode DMA, and End of Transfer (EOT) pins. Master mode must be enabled in the PCI Command register. Direct Slave accesses pre-empt DMA transfers. When the PCI 9080 DMA controller owns the Local Bus, its LHOLD output and LHOLDA input are asserted and its LDSHOLD output is de-asserted. When a Direct Slave access occurs, the PCI 9080 gives up the Local Bus within two Lword transfers by de-asserting LHOLD and floating its Local Bus outputs. After the PCI 9080 samples its LHOLDA input de-asserted, it requests the Local Bus for a Direct Slave transfer by asserting LHOLD and LDSHOLD. When the PCI 9080 receives LHOLDA, it drives the bus and performs the Direct Slave transfer. Upon completion of the Direct Slave transfer, the PCI 9080 gives up the Local Bus by de-asserting both LHOLD and LDSHOLD and floating its Local Bus outputs. After the PCI 9080 samples its LHOLDA deasserted and its local pause timer is zero, it requests the Local Bus for a DMA transfer by re-asserting LHOLD. When it receives LHOLDA, it drives the bus and continues with the DMA transfer. 3.7.1 Non-Chaining Mode DMA The host processor or the Local processor sets the Local Address, PCI Address, transfer count and transfer direction. The host or Local processor then sets a control bit to initiate the transfer. The PCI 9080 arbitrates the PCI and Local Buses and transfer data. Once the transfer is complete, the PCI 9080 sets the Channel Done bit to a value of 1 and generates an interrupt to the Local processor or the PCI Host (programmable). DMA Done bit in the internal DMA register can be pooled to indicate the status of DMA transfer. DMA registers are accessible from the PCI Bus and Local Bus. (Refer to Figure 3-14.) Set DMA Mode to Non-Chaining PCI Host Memory Mode Register Set up Transfer Parameters Memory Block to Transfer PCI Address Register Local Address Register Transfer Size (byte count) Register Descriptor Pointer Register (set direction only) Command/Status Register Local Memory Memory Block to Transfer Set the Enable and Go bits in the DMA Command/Status Register to Initiate DMA Transfer Figure 3-14. Non-Chaining DMA Initialization PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 31 Section 3 Functional Description DMA Operation The Local processor or PCI requires DMA. The PCI 9080 is Master on both the PCI and Local Buses. Direct Slave or Direct Master pre-empts DMA. The PCI 9080 releases the Local Bus if one of the following occurs (refer to Figure 3-16): * FIFO is empty The PCI 9080 releases the PCI Bus if one of the following occurs (refer to Figure 3-15): * Terminal count is reached * * Local Bus Latency Timer (MARBR[7:0]) expires FIFO is full * * BREQ# input is asserted Terminal count is reached * * Direct Slave request is pending PCI Latency Timer (PCILTR[7:0]) expires-- normally programmed by the Host PCI BIOS-- and PCI GNT# de-asserts * PCI Host asserts STOP * Direct Master request pending Slave Slave Master Master DMA Start DMA Start LHOLD LHOLDA DMA Start GNT# GNT# FRAME#, C/BE#, AD (addr) IRDY# IRDY# DEVSEL#, TRDY# , AD (data) PCI 9080 LHOLD Local Bus PCI Bus REQ# REQ# PCI 9080 LD Local Bus DMA Start LA, ADS#, LW/R# Slave Master Master PCI Bus Slave DEVSEL#, TRDY# AD (addr & data) LHOLDA LA, ADS#, LW/R#, BLAST# Figure 3-16. DMA, Local-to-PCI READYi# Figure 3-15. DMA, PCI-to-Local Note: The figures represent a sequence of Bus cycles. 32 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description DMA Operation 3.7.2 Chaining Mode DMA In Chaining mode DMA, the Host Processor or the Local Processor sets up descriptor blocks in local or host memory that are composed of a PCI Address, Local Address, transfer count, transfer direction, and address of the next descriptor block (refer to Figure 3-18). Host or Local Processor then sets up the address of the initial descriptor block in the Descriptor Pointer register of the PCI 9080 and initiates the transfer by setting a control bit. The PCI 9080 loads the first descriptor block and initiates the Data transfer. The PCI 9080 continues to load descriptor blocks and transfer data until it detects the End of Chain bit is set in the Next Descriptor Pointer register. The PCI 9080 can be programmed to interrupt the Local processor by setting the Interrupt after Terminal Count bit or PCI Host upon completion of each block transfer and after all block transfers are complete (done) (refer to Figure 3-17). If chaining descriptors are located in Local memory, the DMA controller can be programmed to clear the transfer size at the completion of each DMA (DMAMODE0[16] and DMAMODE1[16]). Notes: In Chaining mode DMA, the descriptor includes PCI Address, Local Address, Transfer Size and the Next Descriptor Pointer (DMAPADR0-DMADPR0). The Descriptor Pointer register contains the End of Chain bit, Direction of Transfer, Next Descriptor Address, and Next Descriptor Location. The DMA descriptor can be on Local or PCI memory, or both (first descriptor on Local memory, and second descriptor on PCI memory). Local or Host Memory Set DMA Mode to Chaining Mode Register First PCI Address First Local Address Set up First Descriptor Pointer Register (First only requires Descriptor Pointer) First Transfer Size (byte count) Next Descriptor Pointer PCI Address Descriptor Pointer Register Local Address PCI Host Memory First Memory Block to Transfer Transfer Size (byte count) Next Descriptor Pointer Command/Status Register Set the Enable and Go bits in DMA Command/Status Register to Initiate DMA Transfer End of Chain Specification Bit Next Memory Block to Transfer First Memory Block to Transfer Next Memory Block to Transfer Figure 3-17. Chaining DMA Initialization PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 33 Section 3 Functional Description PCI 9080 initiates read from PCI Bus PCI 9080 initiates read from PCI Bus PCI 9080 initiates read from PCI Bus PCI 9080 initiates read from PCI Bus DMA Operation Setup chains DMA for PCI-to-Local 3.7.3 DMA Data Transfers PCI 9080 retrieves chaining information from Local memory The PCI 9080 DMA controller can be programmed to transfer data from the Local Bus side to the PCI Bus side or from the PCI Bus side to the Local Bus side. Refer to Figure 3-19 and Figure 3-20 for a description of the operation. PCI 9080 writes data to Local Bus PCI 9080 PCI 9080 writes data to Local Bus PCI 9080 retrieves chaining information from Local memory PCI 9080 writes data to Local Bus PCI 9080 writes data to Local Bus Read and Write Cycles continue... Figure 3-18. Chaining Mode DMA from PCI-to-Local Note: The figure represents a sequence of Bus cycles. 34 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description DMA Operation 3.7.3.1 Local-to-PCI Bus DMA Transfer PCI Interrupt Generation (Programmable) * * Local Interrupt Generation (Programmable) * * Done Chaining: Terminal Count for Current Descriptor Unload FIFO with PCI Bus Write Cycles Chaining Mode Descriptors: FIFO PCI Arbitration Local Bus Arbitration At start of each block transfer--in Chaining mode only--loads DMA registers by reading four Lwords from address specified in Next Descriptor Pointer register. Chaining Mode Descriptors: At start of each block transfer-- in Chaining mode only--loads DMA registers by reading four Lwords from address specified in Next Descriptor Pointer register. GNT# PCI Bus Arbitration: Load FIFO with Local Bus Read Cycles Done Chaining: Terminal Count for Current Descriptor REQ# LHOLDA LHOLD Local Bus Arbitration: Releases control of Local Bus whenever FIFO becomes full, terminal count is reached, Local latency timer expires, BREQ input is asserted, or Direct PCI-to-Local Bus request is pending. Releases control of PCI Bus whenever FIFO becomes empty, PCI latency timer expires and PCI GRANT de-asserts, PCI Disconnect is received, or Direct Local-to-PCI Bus request is pending. Rearbitrates for control of Local Bus when preprogrammed number of empty entries in FIFO become available. If Local latency timer has expired, waits until pause timer expires. Rearbitrates for control of PCI Bus when preprogrammed number of entries in FIFO become available, or after two PCI clocks if disconnect is received. Figure 3-19. Local-to-PCI Bus DMA Data Transfer Operation 3.7.3.2 PCI-to-Local Bus DMA Transfer Local Interrupt Generation (Programmable) PCI Interrupt Generation (Programmable) * * Done Chaining: Terminal Count for Current Descriptor * * Load FIFO with PCI Bus Read Cycles Chaining Mode Descriptors: FIFO PCI Arbitration Local Bus Arbitration At start of each block transfer--in Chaining mode only--loads DMA registers by reading four Lwords from address specified in Next Descriptor Pointer register. PCI Bus Arbitration: Unload FIFO with Local Bus Write Cycles Done Chaining: Terminal Count for Current Descriptor Chaining Mode Descriptors: At start of each block transferin -- Chaining mode only--loads DMA registers by reading four Lwords from address specified in Next Descriptor Pointer register. GNT# REQ# LHOLDA LHOLD Releases control of PCI Bus whenever FIFO becomes full, terminal count is reached, PCI latency timer expires and PCI GRANT de-asserts, PCI Disconnect is received, or Direct Local-to-PCI Bus request is pending. Rearbitrates for control of PCI Bus when preprogrammed number of empty entries in FIFO become available, or after two PCI clocks if disconnect is received. Local Bus Arbitration: Releases control of Local Bus whenever FIFO becomes empty, Local latency timer expires, BREQ input is asserted, or Direct PCI-to-Local Bus request is pending. Rearbitrates for control of Local Bus when preprogrammed number of entries become available in FIFO or PCI terminal count is reached. If Local latency timer has expired, waits until pause timer expires. Figure 3-20. PCI-to-Local Bus DMA Data Transfer Operation PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 35 Section 3 Functional Description DMA Operation 3.7.3.3 Unaligned Transfers 3.7.5 DMA Priority For unaligned Local-to-PCI transfers, the PCI 9080 reads a partial Lword from the Local Bus. It continues to read Lwords from the Local Bus. Lwords are assembled, aligned to the PCI Bus address and loaded into the FIFO. DMA Channel 0 priority, DMA Channel 1 priority, or rotating priority can be specified in the DMA Arbitration register. For PCI-to-Local transfers, Lwords are read from the PCI Bus and loaded into the FIFO. On the Local Bus, the Lwords are assembled from the FIFO, aligned to the Local Bus address and written to the Local Bus. On both the Local and PCI Buses, the byte enables for writes determine LA[1:0] for the start of a transfer. For the last transfer, the byte enables specify the bytes to be written. All reads are Lwords. 3.7.4 Demand Mode DMA DMA Mode register bit 15 (BLAST mode for Demand mode DMA), determines the number of Lwords transferred after a DMA controllers DREQ[1:0]# input is de-asserted. If BLAST# output is not required for the last Lword of the DMA transfer (bit 15 = 1), the DMA controller releases the data bus after it receives an external READYi# or the internal wait state counter decrements to a value of 0 for the current Lword. If DMA controller is currently bursting data, which is not the last Data phase for the burst, BLAST# output is not asserted. If BLAST# output is required for the last Lword of the DMA transfer (bit 15 = 0), the DMA controller transfers one or two Lwords. If DREQ[1:0]# is de-asserted during the Address phase of the first transfer in a PCI 9080 Local Bus ownership (ADS#, LHOLDA asserted), the DMA controller completes the current Lword. If DREQ[1:0]# is de-asserted during any phase other than the Address phase of the first transfer in a PCI 9080 Local Bus ownership, the DMA controller completes the current Lword, and one additional Lword (this allows BLAST# output to be asserted during the final Lword). If the DMA FIFO is full or empty after the Data phase in which DREQ[1:0]# is de-asserted, the second Lword is not transferred. DREQ[1:0]# controls only the number of Lword transfers. For an 8-bit bus, the PCI 9080 gives up the bus after the last byte for the Lword is transferred. For a 16-bit bus, the PCI 9080 gives up the bus after the last word for the Lword is transferred. 36 3.7.6 DMA Arbitration The PCI 9080 DMA controller releases control of the Local Bus (de-asserts LHOLD) when one of the following occurs: * FIFOs are full in a Local-to-PCI transfer * FIFOs are empty in a PCI-to-Local transfer * Local Bus Latency Timer expires (if enabled) * BREQ input is asserted (BREQ can be enabled or disabled, or gated with a latency timer before the PCI 9080 gives up the Local Bus) * Direct Slave access is pending * EOT input is received (if enabled) The DMA controller releases control of the PCI Bus when one of the following occurs: * FIFOs are full or empty * PCI Latency Timer expires and loses the PCI GNT# signal * Target Disconnect response is received DMA controller de-asserts its PCI Bus request (REQ#) for a minimum of two PCI clocks. 3.7.6.1 End of Transfer (EOT0# or EOT1#) Input DMA Mode register bit 15 (BLAST mode for EOT), determines the number of Lwords transferred after a DMA controller EOT[1:0]# input is asserted. If BLAST# output is not required for the last Lword of the DMA transfer (bit 15 = 1), the DMA controller releases the data bus and terminates DMA after it receives an external READYi# or the internal wait state counter decrements to a value of 0 for the current Lword. If the DMA controller is currently bursting data, which is not the last Data phase for the burst, BLAST# output is not asserted. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description Vendor and Device ID Registers If BLAST# output is required for the last Lword of the DMA transfer (bit 14 = 0), the DMA controller transfers one or two Lwords. If EOT[1:0]# is asserted, the DMA controller completes the current Lword, and one additional Lword (this allows BLAST# output to be asserted during the final Lword). If the DMA FIFO is full or empty after the Data phase in which EOT[1:0]# is asserted, the second Lword is not transferred. The DMA controller terminates a transfer on an Lword boundary after EOT[1:0]# is asserted. For an 8-bit bus, the PCI 9080 terminates after the last byte for the Lword is transferred. For a 16-bit bus, the PCI 9080 terminates after the last word for the Lword is transferred. 3.8 Vendor and Device ID Registers Three Vendor and Device ID registers are supported: * PCIIDR, which contains the normal Device and Vendor IDs. This register can be loaded from the serial EEPROM or from Local processors. * PCISVID, which contains the Subsystem and Subvendor IDs. This register can be loaded from the serial EEPROM or from Local processors. * PCIHIDR, which contains the hardcoded PLX Vendor and Device IDs. 3.9 Doorbell Registers 3.7.6.2 DMA Abort A DMA transfer can be aborted. The abort process is as follows: 1. DMA Channel must be enabled (DMACSR0[0]=1). 2. DMA Channel must be started (DMACSR0[1]=1). 3. Wait for the Channel Done bit to be set to zero (DMACSR0[4]=0). 4. Disable the DMA Channel (DMACSR0[0] =0). 5. Abort DMA by programming the Channel Abort bit (DMACSR0[2]=1). 6. Wait until the Channel Done bit is set (DMACSR0[4]=1). Note: One to two Data transfers occur after the Abort bit is set. Aborting when no DMA cycles are in progress causes the next DMA to abort. There are two 32-bit doorbell interrupt/status registers in the PCI 9080. One is assigned to the PCI Bus interface and the other is assigned to the Local Bus interface. The Local processor can generate a PCI Bus interrupt by writing any number other than all zeroes to the PCIto-Local Doorbell register (P2LDBELL). A PCI Host can generate a Local Bus interrupt by writing any number other than all zeroes to the Local-toPCI Doorbell register (L2PDBELL). 3.10 Mailbox Registers There are eight 32-bit mailbox registers in the PCI 9080 that can be written to and read from both buses. These registers can be used to pass command and status information directly between Local and PCI Bus devices. A Local interrupt can be generated, if enabled, when the PCI Host writes to one of the first four mailbox registers. 3.7.6.3 Local Latency and Pause Timers A Local Bus Latency Timer and Local Bus Pause Timer are programmable with the DMA Arbitration register. If the Local Latency Timer expires, the PCI 9080 completes the current Lword transfer and releases LHOLD. After its programmable Pause Timer expires, it reasserts LHOLD. When it receives LHOLDA, it continues the transfer. The PCI Bus transfer continues until the FIFO is empty for a Local-to-PCI transfer or until it is full for a PCI-to-Local transfer. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 3.11 User Input and Output The PCI 9080 supports user input and output pins, USERI[31] and USERO[27], respectively. User output data can be logged by writing to CNTRL[16]. User input data can be read from CNTRL[17]. 37 Section 3 Functional Description Interrupts 3.12 Interrupts Parity Error [1] Master Abort 256 Retrys [12] OR [0] OR LSERR# Target Abort Messaging Queue DMA Ch 0 Done X2 DMA Ch 0 Terminal Count X3 OR X4 Doorbells [17] Mailboxes [7] BIST [23] Messaging Queue X9 X1 OR DMA Ch 0 Done DMA Ch 0 Terminal Count X2 OR LINTo# X4 X3 Doorbells [9] Master Abort 256 Retrys [16] [12] OR [10] Target Abort LINTi# OR [8] X5 DMA Ch 1 Done X6 DMA Ch 1 Terminal Count X7 OR X6 DMA Ch 1 Terminal Count X7 OR X8 INTA# [11] Messaging Queue DMA Ch 1 Done X8 The # X1 = X2 = X3 = X4 = X5 = X6 = X7 = X8 = X9 = represent the bit # of register (LOC [E8h]) Bits [7:6] of register (LOC [168h]) Bit 10 of register (LOC [100h]) Bit 2 of register (LOC [E110h]) Bit 18 of register (LOC [E8h]) & Bit 17 of register (LOC [100h]) Bits [5:4] of register (LOC [168h]) Bit 10 of register (LOC [114h]) Bit 2 of register (LOC [124h]) Bit 19 of register (LOC [E8h]) and Bit 17 of register (LOC [114h]) Bit 3 of register (LOC [B0h]) & Bit 3 of register (LOC [B4h]) For X4 and X8, if bit 17='0', then LINTo# is generated and if bit 17='1', then INTA# is generated. Figure 3-21. Interrupt and Error Sources 3.12.1 PCI Interrupts (INTA#) 3.12.1.1 Local Interrupt Input A PCI 9080 PCI Interrupt (INTA#) can be generated by one of the following: Asserting Local Bus input pin LINTi# can generate a PCI Bus interrupt. PCI Host processor can read the PCI 9080 Interrupt Control/Status register to determine that an interrupt is pending due to the LINTi# pin being asserted. * Local-to-PCI Doorbell register * Local interrupt input * Master/Target abort status condition * DMA Ch 0/Ch 1 Done * DMA Ch 0/Ch 1 Terminal Count reached * Messaging Outbound Post Queue is not empty INTA#, or individual sources of an interrupt, can be enabled or disabled with the PCI 9080 Interrupt Control/Status register (INTCSR). This register also provides interrupt status for each interrupt source. The PCI 9080 PCI Bus interrupt is level output. Disabling an Interrupt Enable bit or clearing the cause(s) of the interrupt can clear an interrupt. 38 The interrupt remains asserted as long as the LINTi# pin is asserted and the Local interrupt input is enabled. Adapter specific action can be taken by the PCI Host processor to cause the Local Bus to release LINTi#. 3.12.1.2 Master/Target Abort Interrupt The PCI 9080 sets the Master Abort or Target Abort Status bit in the PCI Configuration register when it detects a Master or Target abort. These status bits cause PCI INTA# to be asserted if interrupts are enabled. The interrupt remains asserted as long as the Master or Target Abort bits remain set in the PCI Status PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description Interrupts Configuration register (PCISR) and Master/Target Abort Interrupt is enabled. Use a PCI Type 0 Configuration access or a Local access to clear the Master Abort and Target Abort Interrupt bits in the PCI Status Configuration register. To prevent race conditions when the PCI Bus is accessing the Doorbell register (or any Configuration register), the PCI 9080 automatically de-asserts READYo# to prevent Local Bus accesses. Interrupt Control/Status register Bits (INTCSR[26:24]) are latched at the time of a Target abort interrupt or Master abort interrupt. They provide information as to who was Master when an abort occurred. The PCI 9080 updates these bits whenever an abort occurs. 3.12.2.2 PCI-to-Local Doorbell Interrupt 3.12.2 Local interrupts (LINTo#) A PCI 9080 Local interrupt (LINTo#) can be generated by one of the following: * PCI-to-Local Doorbell/Mailboxes Register access * PCI BIST interrupt, the DMA done interrupt * DMA terminal count is reached * DMA abort interrupt or the Messaging Outbound Post Queue is not empty LINTo#, or individual sources of an interrupt, can be enabled or disabled with the PCI 9080 Interrupt Control/Status register (INTCSR). The Interrupt Control/Status register also provides interrupt status for each source of the interrupt. The PCI 9080 Local interrupt is a level output. An interrupt can be cleared by disabling the Interrupt Enable bit of a source or by clearing the cause of an interrupt. A PCI Bus Master can generate a Local Bus interrupt by writing to the PCI-to-Local Doorbell register (P2LDBELL). Local processor can then read the PCI 9080 Interrupt Control/Status register (INTCSR) to determine that a doorbell interrupt is pending. It can then read the PCI 9080 PCI-to-Local Doorbell register. Each bit in the PCI-to-Local Doorbell register is individually controlled. The PCI Bus can only set bits in the Doorbell register. From the PCI Bus, writing 1 to any bit position sets that bit and writing 0 to a bit position has no effect. Bits in the PCI-to-Local Doorbell register can only be cleared from the Local Bus. From the Local Bus, writing 1 to any bit position clears that bit and writing 0 to a bit position has no effect. Note: If Local Bus cannot clear Doorbell Interrupt, do not use the PCI-to-Local Doorbell register. The interrupt remains asserted as long any of the PCI-to-Local Doorbell register bits are set and the Local Doorbell Interrupt is enabled. To prevent race conditions when the Local Bus is accessing the Doorbell register (or any Configuration register), the PCI 9080 automatically issues a Retry to the PCI Bus. 3.12.2.1 Local-to-PCI Doorbell Interrupt A Local Bus Master can generate a PCI Bus interrupt by writing to the Local-to-PCI Doorbell register (L2PDBELL). PCI Host processor can then read the PCI 9080 Interrupt Control/Status register (INTCSR) to determine that a doorbell interrupt is pending. It can then read the PCI 9080 Local-to-PCI Doorbell register. Each bit in the Local-to-PCI Doorbell register is individually controlled. The Local Bus can only set bits in the Doorbell register. From the Local Bus, writing 1 to any bit position sets that bit and writing 0 to a bit position has no effect. Bits in the Local-to-PCI Doorbell register can only be cleared from the PCI Bus. From the PCI Bus, writing 1 to any bit position clears that bit and writing 0 to a bit position has no effect. 3.12.2.3 Built-In Self Test Interrupt (BIST) A PCI Bus Master can generate a Local Bus interrupt by performing a PCI Type 0 Configuration write to a bit in the PCI BIST register. The Local processor can then read the PCI 9080 Interrupt Control/Status register (INTCSR) to determine that a BIST interrupt is pending. The interrupt remains asserted as long as the bit is set and the BIST interrupt is enabled. The Local Bus then resets the bit when BIST is complete. PCI Host software may fail the device if the bit is not reset after two seconds. Note: The PCI 9080 does not have an internal BIST. The interrupt remains asserted as long as any of the Local-to-PCI Doorbell register bits are set and PCI Doorbell Interrupt is enabled. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 39 Section 3 Functional Description 3.12.2.4 DMA Channel 0/1 Interrupts A DMA channel can generate a PCI or Local Bus interrupt when done (transfer complete) or after a transfer is complete for a descriptor in Chaining mode. A bit in the DMA mode register determines whether to generate a PCI or Local interrupt. The local or PCI processor can then read the PCI 9080 Interrupt Control/Status register (INTCSR) to determine whether a DMA channel interrupt is pending. A Done Status Bit in the Control/Status register can be used to determine whether the interrupt is * A done interrupt * The result of a transfer for a descriptor in a chain that is not yet complete The mode register of a channel enables a Done Interrupt. In Chaining mode, a bit in the Next Descriptor Pointer register of the channel (loaded from Local memory) specifies whether to generate an interrupt at the end of the transfer for the current descriptor. A DMA channel interrupt is cleared by writing a 1 to the Clear Interrupt bit in the DMA Command/Status register (DMACSR0[3] and DMACSR1[3]). 3.12.3 PCI SERR# (PCI NMI) The PCI 9080 generates an SERR# pulse if parity checking is enabled in the PCI Command register and it detects an address parity error or the Generate SERR# bit in the Interrupt Control/Status register (INTCSR) is 0 and a 1 is written. SERR# output can be enabled or disabled with the PCI Command register. I2O Compatible Message Unit If parity error checking is enabled in the PCI Command register, the PCI 9080 sets the Master Detected Parity Error Status bit in the PCI Status Configuration register (PCISR) if it detects one of the following: * Parity error during a PCI 9080 Master Read * PCI Bus signal PERR# being asserted during a PCI 9080 Master Write The PCI 9080 sets a Parity Error bit in the PCI Status Configuration register (PCISR) if it detects one of the following: * Data parity error during a PCI 9080 Master Read * Data parity error during a Slave Write access to the PCI 9080 * Address parity error The PCI 9080 Interrupt Control/Status register (INTCSR) can be used to individually enable or disable LSERR# for an abort or parity error. LSERR# is a level output that remains asserted as long as the Abort or Parity Error Status bits are set. 3.13 I2O Compatible Message Unit The Messaging Unit supplies two paths for messages, two inbound FIFOs to receive messages from the primary PCI Bus and two outbound FIFOs to pass messages to the primary PCI Bus. Refer to I2O Architecture Specification v1.5 for details. Figure 3-22 and Figure 3-23 illustrate information about the I2O architecture. Message Frames No hardware changes are required on host side Physical System Memory Host CPU 3.12.4 Local LSERR# (Local NMI) LSERR# interrupt output is asserted if the following occurs: * PCI Bus Target Abort or Master Abort Status bit is set in the PCI Status Configuration register * Parity Error Status bit is set in the PCI Status Configuration register * Messaging Outbound Free Queue overflows PCI Bus Inbound Queue Outbound Queue IOP Local Memory IOP CPU Message Frames IOP = Intelligent I/O Processor IOP Must Have * CPU * Memory * Messaging Unit Figure 3-22. I2O System Architecture 40 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description I2O Compatible Message Unit Current Architecture I O Architecture FIFO by writing the free MFA into the Outbound Queue Port location. OS Specific Module OSM Memory for the circular FIFOs must be allocated in Local Bus (IOP) memory. The base address of the queues is contained in the Queue Base Address register (QBAR). Each FIFO entry is a 32-bit data value. Each read and write of the queue must be a single 32-bit access. 2 Messaging Layer Hardware Device Module Hardware HDM OSM = Operating System Master HDM = Hardware Device Module Hardware Figure 3-23. I2O Software Architecture 3.13.1 Inbound Messages Inbound messages reside in a pool of message frames (minimum of 64-byte frames) allocated in shared Local Bus (IOP) memory. The Inbound Message Queue is comprised of a pair of rotating FIFOs implemented in Local memory. The Inbound Free List FIFO holds the message frame addresses (MFA) of available message frames in Local memory. The Inbound Post List FIFO holds the message frame addresses (MFA) of all currently posted messages. The inbound circular FIFOs are accessed by external PCI agents through the Inbound Queue Port location in the PCI Address space. The Inbound Queue Port, when read by an external PCI agent, returns the Inbound Free List FIFO MFA. An external PCI agent places a message frame into the Inbound Post List FIFO by writing its MFA to the Inbound Queue Port location. 3.13.2 Outbound Messages Outbound messages reside in a pool of message frames (minimum 64-byte frames) allocated in shared PCI Bus (Host System) memory. The Outbound Message Queue is comprised of a pair of rotating FIFOs implemented in Local memory. The Outbound Free List FIFO holds the message frame addresses (MFA) of available message frames in system memory. The Outbound Post List FIFO holds the MFA of all currently posted messages. The outbound circular FIFOs are accessed by external PCI agents through the Outbound Queue Port location in the PCI Address space. The Outbound Queue Port, when read by an external PCI agent, returns the Outbound Post List FIFO MFA. An external PCI agent places free message frames into the Outbound Free List PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved The circular FIFOs range in size from 4 KB entries to 64 KB entries. All four FIFOs must be contiguous and of the same size. Therefore, the total amount of Local memory needed for circular FIFOs ranges from 64 KB to 1 MB. The FIFO size is specified in the Messaging Queue Configuration register (MQCR). The starting address of each FIFO is based on the Queue Base Address and the FIFO size, as listed in Table 3-7. Table 3-7. Queue Starting Address FIFO Starting Address Inbound Free List QBAR Inbound Post List QBAR + (1 * FIFO Size) Outbound Post List QBAR + (2 * FIFO Size) Outbound Free List QBAR + (3 * FIFO Size) 3.13.3 I2O Pointer Management The FIFOs always reside in shared Local Bus (IOP) memory and are allocated and initialized by the IOP. Before enabling I2O (Messaging Queue Configuration register bit 0 set to 1), the Local processor must initialize the following registers with the initial offset, according to the configured FIFO size: * Inbound Post and Free Head Pointer registers * Inbound Post and Free Tail Pointer registers * Outbound Post and Free Head Pointer registers * Outbound Post and Free Tail Pointer registers The Messaging Unit (MU) automatically adds the Queue Base Address to the offset in each head and tail pointer register. The software can then enable I2O. After initialization, the local software should not write to the pointers managed by the MU hardware. The empty flags are set if the queues are disabled (MQCR[0] = 0) and head and tail pointers are equal. This occurs independently of how the head and tail pointers are set. 41 Section 3 Functional Description An empty flag is cleared, signifying not empty, only if the queues are enabled and the pointers become not equal. If an empty flag is cleared and the queues are enabled, the empty flag is set only if the tail pointer is incremented and the head and tail pointers become equal. Full flags are always cleared when the queues are disabled or the head and tail pointers are not equal. A full flag is set when the queues are enabled, the head pointer is incremented, and the head and tail pointers become equal. Each circular FIFO has a head pointer and a tail pointer, which are offsets from the Queue Base Address. Writes to a FIFO occur at the head of the FIFO and reads occur from the tail. The head and tail pointers are incremented by either the Local processor or the MU hardware. The unit that writes to the FIFO also maintains the pointer. The pointers are incremented after a FIFO access. Both pointers wrap around to the first address of the circular FIFO when they reach the FIFO size, so that the head and tail pointers "chase" each other around and around in the circular FIFO. MU wraps the pointers automatically for the pointers that it maintains. IOP software must wrap the pointers that it maintains. Whenever they are equal, the FIFO is empty. To prevent overflow conditions, I2O specifies that the number of message frames allocated should be less than or equal to the number of entries in a FIFO. (Refer to Figure 3-24 for additional information.) Each inbound MFA is specified by I2O as the offset from the start of shared Local Bus (IOP) memory region 0 to the start of the message frame. Each outbound MFA is specified as the offset from the Host memory location 0x00000000h to the start of the message frame in the shared Host memory. Since the MFA is an actual address, the message frames need not be contiguous. The IOP allocates and initializes inbound message frames in shared IOP memory using any suitable memory allocation technique. The Host allocates and 42 I2O Compatible Message Unit initializes outbound message frames in shared Host memory using any suitable memory allocation technique. Message frames are a minimum of 64 bytes in length. I2O uses a "push" (write-preferred) memory model. That means that the IOP writes messages and data to the shared Host memory, and the Host writes messages and data to shared IOP memory. Software should make use of Burst and DMA transfers whenever possible to ensure efficient use of the PCI Bus for message passing. Additional information on message passing implementation may be found in the I2O Architecture Specification v1.5. 3.13.4 Inbound Free List FIFO The Local processor allocates inbound message frames in its shared memory and can place the address of a free (available) message frame into the Inbound Free List FIFO by writing its MFA into the FIFO location pointed to by the Queue Base register + Inbound Free Head Pointer register. The Local processor must then increment the Inbound Free Head Pointer register. A PCI Master (Host or another IOP) can obtain the MFA of a free message frame by reading the Inbound Queue Port Address (40h of the first PCI Memory Base Address register). If the FIFO is empty (that is, no free inbound message frames are currently available, and the head and tail pointers are equal), the MU returns a value of -1 (FFFFFFFFh). If the FIFO is not empty (that is, the head and tail pointers are not equal), the MU reads the MFA pointed to by the Queue Base register + Inbound Free Tail Pointer register, returns its value and increments the Inbound Free Tail Pointer register. If the Inbound Free Queue is not empty, and queue prefetching is enabled (QSR[3], the next entry in the FIFO is read from the Local Bus into a prefetch register. The prefetch register then provides the data for the next PCI read from this queue, thus reducing the number of PCI wait states. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description I2O Compatible Message Unit High Address Local Memory Write Outbound Queue Port External PCI Agent Outbound Read Incremented by PCI 9080 hardware Free Head Pointer List Tail Pointer FIFO Incremented by local processor Local Processor Outbound Queue Read Write Outbound Incremented by local processor Post Head Pointer List Tail Pointer FIFO Incremented by PCI 9080 hardware Write Inbound Queue Port External PCI Agent Inbound Read Incremented by PCI 9080 hardware Post Head Pointer List Tail Pointer FIFO Incremented by local processor Local Processor Inbound Queue Read Write Inbound Incremented by local processor Free Head Pointer List Tail Pointer FIFO Incremented by PCI 9080 hardware Low Address Local Memory Figure 3-24. Circular FIFO Operation PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 43 Section 3 Functional Description 3.13.5 Inbound Post List FIFO A PCI Master (Host or another IOP) can write a message into an available message frame in shared Local Bus (IOP) memory. It can then post that message by writing the message frame address (MFA) to the Inbound Queue Port Address (40h of the first PCI Memory Base Address register). When the port is written, the MU writes the MFA to the Inbound Post List FIFO location pointed to by the Queue Base register + FIFO Size + Inbound Post Head Pointer register. After the MU writes the MFA to the Inbound Post List FIFO, it increments the Inbound Post Head Pointer register. The Inbound Post Tail Pointer register points to the Inbound Post List FIFO location which holds the MFA of the oldest posted message. The Local processor maintains the tail pointer. After a Local processor reads the oldest MFA, it can remove the MFA from the Inbound Post List FIFO by incrementing the Inbound Post Tail Pointer register. The PCI 9080 generates a Local interrupt when the Inbound Post List FIFO is not empty. The Inbound Post List FIFO Interrupt bit in the Queue Status/Control register (QSR) indicates the interrupt status. The interrupt clears when the Inbound Post List FIFO is empty. The interrupt can be masked by the Inbound Post List FIFO Interrupt Mask bit (QSR[4]). To prevent race conditions from the time the PCI Write transaction is received until the data is written in Local memory and the Inbound Post Head Pointer register is incremented, any PCI Direct Slave access to the PCI 9080 is issued a Retry. 3.13.6 Outbound Post List FIFO A Local Master (IOP) can write a message into an available message frame in shared Host memory. It can then post that message by writing the message frame address (MFA) to the Outbound Post List FIFO location pointed to by the Queue Base register + Outbound Post Head Pointer register + (2 * FIFO Size). The Local processor should then increment the Outbound Post Head Pointer register. A PCI Master can obtain the MFA of the oldest posted message by reading the Outbound Queue Port Address (44h of the first PCI Memory Base Address register). If the FIFO is empty (that is, no more outbound messages are posted, and the head and tail pointers are equal), the MU returns a value of -1 (FFFFFFFFh). If the Outbound Post List FIFO is not empty (that is, the head and tail pointers are not equal), the MU reads the MFA pointed 44 I2O Compatible Message Unit to by the Queue Base register + (2 * FIFO Size) + Outbound Post Tail Pointer register, returns its value and increments the Outbound Post Tail Pointer register. The PCI 9080 generates a PCI Interrupt when the Outbound Post Head Pointer register is not equal to the Outbound Post Tail Pointer register. The Outbound Post List FIFO Interrupt bit of the Outbound Post List FIFO Interrupt Status (OPLFIS) register indicates the interrupt status. When the pointers become equal, both the interrupt and the Outbound Post List FIFO Interrupt bit are automatically cleared. The pointers become equal when a PCI Master (Host or another IOP) reads enough FIFO entries to empty the FIFO. The Outbound Post List FIFO Interrupt Mask (OPLFIM) register can mask the interrupt. 3.13.7 Outbound Post Queue To reduce read latency, prefetching from the tail of the queue occurs whenever the queue is not empty and the tail pointer is incremented (queue has been read from), or when the queue is empty and the head pointer is incremented (queue has been written to). When the host CPU reads the Outbound Post Queue, the data is immediately available. 3.13.8 Inbound Free Queue To reduce read latency, prefetching from the tail of the queue occurs whenever the queue is not empty and the tail pointer is incremented (queue has been read from), or when the queue is empty and the head pointer is incremented (queue has been written to). When the host CPU reads the Inbound Free Queue, the data is immediately available. 3.13.9 Outbound Free List FIFO A PCI Master (Host or other IOP) allocates outbound message frames in its shared memory and can place the address of a free (available) message frame into the Outbound Free List FIFO by writing the message frame address (MFA) to the Outbound Queue Port Address (44h of the first PCI Memory Base Address register). When the port is written, the MU writes the MFA to the Outbound Free List FIFO location pointed to by the Queue Base register + (3 * FIFO Size) + Outbound Free Head Pointer register. After the MU writes the MFA to the Outbound Free List FIFO, it increments the Outbound Free Head Pointer register. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 3 Functional Description I2O Compatible Message Unit When the IOP needs a free outbound message frame, it must first check whether any free frames are available. If the Outbound Free List FIFO is empty (that is, the outbound free head and tail pointers are equal), the IOP must wait for the Host to place additional outbound free message frames in the Outbound Free List FIFO. If the Outbound Free List FIFO is not empty (that is, the head and tail pointers are not equal), the IOP can obtain the MFA of the oldest free outbound message frame by reading the location pointed to by the Queue Base register + (3 * FIFO Size) + Outbound Free Tail Pointer register. After the IOP reads the MFA, it must increment the Outbound Free Tail Pointer register. To prevent overflow conditions, I2O specifies that the number of message frames allocated should be less than or equal to the number of entries in a FIFO. MU also checks for overflows of the Outbound Free List FIFO. When the head pointer is incremented and becomes equal to the tail pointer, the Outbound Free List FIFO is full, and the MU generates a local LSERR (NMI) interrupt. The interrupt is recorded in the Queue Status Control (QSR) register. From the time that the PCI Write transaction is received until the data is written into Local memory and the Outbound Free Head Pointer register is incremented, any PCI Direct Slave access to the PCI 9080 is issued a Retry. Table 3-8. Circular FIFO Summary FIFO Name PCI Port Generate PCI Interrupt? Generate Local Interrupt Head Pointer Maintained by Tail Pointer Maintained by Inbound Free List FIFO Inbound Queue Port (Host Read) No No Local processor MU hardware Inbound Post List FIFO Inbound Queue Port (Host Write) No Yes, when the Port is written MU hardware Local processor Outbound Post List FIFO Outbound Queue Port (Host Read) Yes, when the FIFO is not empty No Local processor MU hardware Outbound Free List FIFO Outbound Queue Port (Host Write) No Yes, (LSERR) when the FIFO is full MU hardware Local processor 3.13.10 I2O Enable Sequence To enable I2O, the Local processor should perform the following: * Initialize Space 1 address and range * Initialize all FIFOs and message frame memory * Set the PCI class code in PCICCR to be an I2O device with programming interface 01h * Set the I2O Enable bit * Set the Local Init Done bit Note: NB# must be pulled up so the PCI 9080 issues retries to all PCI accesses until the Local Init Done bit is set in CNTRL by the Local processor. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved The I2O Enable bit in the Queue Status register (QSR) causes remapping of resources for use in I2O mode. When this bit is set, all Memory-Mapped Configuration registers (such as queue ports 40h and 44h) and Space 1 share PCIBAR0. PCI accesses to offset 00h-FFh of PCIBAR0 result in accesses to the internal Configuration registers of the PCI 9080. Accesses above offset FFh of PCIBAR0 result in Local Space accesses, beginning at offset 100h from the Local Space 1 Remap register (LAS1BA). Therefore space located at offset 00h-FFh from LAS1BA is not addressable by way of PCIBAR0. Programmer's Note: Because PCI accesses to offset 00h-FFh of PCIBAR0 result in internal Configuration accesses, Inbound Free MFAs must be greater than FFh. 45 This page intentionally left blank. 46 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 4. REGISTERS 4.1 New Register Definitions Summary Refer to descriptions in the following sections for a full explanation. Table 4-1. New Registers Definitions Summary PCI Offset Local Offset Register 08h or ACh 88h or 12Ch MARBR Bits Description 23 Add PCIREQMODE output. 28 Read Ahead mode. 18h 98h LBRD0 15 Single Read mode removed. 28h A8h DMPBAM 10 Extend almost full flag to five bits (fifth bit not contiguous). 11 Add CDMPFLIMIT output; do not prefetch past 4 KB boundary for Direct Master. 12, 3 13 15:14 30h B0h 34h 40h Direct Master Read prefetch size control. I/O Remap select. Direct Master write delay. OPLFIS all New Outbound Post List FIFO Interrupt Status register. B4h OPLFIM all New Outbound Post List FIFO Interrupt Mask register. N/A IQP all New Inbound Queue Port register. 44h N/A OQP all New Outbound Queue Port register. 68h E8h INTCSR 4 Move DMA0INTSEL output to DMAMODE0. Change to Reserved. 5 Move DMA1INTSEL output to DMAMODE1. Change to Reserved. 3 Mailbox interrupt enable on F, not on PCI 9060. 31:28 100h DMAMODE0 94h 114h DMAMODE1 17 Add C1_INTSEL output. 0=Local int., 1=PCI int. C0h 140h MQCR all New Messaging Queue Configuration register. C4h 144h QBAR all New Queue Base Address register. C8h 148h IFHPR all New Inbound Free Head Pointer. CCh 14Ch IFTPR all New Inbound Free Tail Pointer. D0h 150h IPHPR all New Inbound Post Head Pointer. D4h 154h IPTPR all New Inbound Post Tail Pointer. D8h 158h OFHPR all New Outbound Free Head Pointer. DCh 15Ch OFTPR all New Outbound Free Tail Pointer. E0h 160h OPHPR all New Outbound Post Head Pointer. E4h 164h OPTPR all New Outbound Post Tail Pointer. E8h 168h QSR all New I2O Queue Status register. F0h 170h LAS1RR all New Local Address Space 1 Range Register for PCI-to-Local. F4h 174h LAS1BA all New Local Address Space 1 Local Base Address (Remap). F8h 178h LBRD1 all New Local Address Space 1 Bus Region Descriptor. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 16 Mailbox interrupts on SD, not on PCI 9060. 80h Clear byte count in chaining descriptor. 17 Add C0_INTSEL output. 0=Local int., 1=PCI int. 16 Clear byte count in chaining descriptor. 47 Section 4 Registers New Register Definitions Summary 4.1.1 Register Differences between PCI 9080 and PCI 9060, PCI 9060ES, and PCI 9060SD Table 4-2. Register Differences between PCI 9080 and PCI 9060 Register PCI/Local Offset Bits PCIIDR 00/00 31:16 Default changed from PCI 9060 to PCI 9080 Description PCICR 04/04 4 Memory Write and Invalidate now supported PCISR 06/06 6 User-definable bit added PCICLSR 0C/0C 7:0 Cache line size is now used for Memory Write and Invalidate PCIBAR0 10/10 8:6 Register Bank size changed from 128 to 256 PCIBAR1 14/14 8:6 Register Bank size changed from 128 to 256 PCIBAR3 1C/1C 31:0 Base address register for Local Address Space 1 PCISVID 2C/2C 15:0 Subsystem Vendor ID register PCISID 2E/2E 15:0 Subsystem ID register MARBR 08, AC/88, 12C 31:0 21 22 Direct Slave Lock Enable 23 PCI Request Mode 24 PCI Specification v2.1 Mode 25 PCI Read/No Write Mode 26 PCI Read with Write Flush Mode 27 Get Local Bus Latency Timer with BREQ 28 PCI Read/No Flush Mode 7:0 Big/Little Endian Descriptor register BIGEND 0C/8C EROMBA 14/94 5 LBRD0 18/98 1:0 10 28/A8 BREQo Timer Resolution control Local Bus width now programmable in S mode Read Prefetch Count Enable 14:11 Read Prefetch Count 17:16 Local Bus width now programmable in S mode 25 DMPBAM Mode/Arbitration register now accessible from the PCI Bus Local Bus Direct Slave Give up Bus Mode 12, 3 10, 8:5 Extra Long Serial EEPROM Load Direct Master Read Prefetch Size Control Programmable Almost Full Flag increased by two bits 11 Direct Master Prefetch Limit 13 I/O Remap select 15:14 Direct Master Write Delay LAS1RR F0/170 31:0 Local Address Space 1 Range register LAS1BA F4/174 31:0 Local Address Space 1 Local Base Address register (Remap) LBRD1 F8/178 31:0 Local Address Space 1 Bus Region Descriptor register MBOX0 40, 78/C0 31:0 MBOX0 moved to PCI Address 78 when Messaging Queue is enabled MBOX1 44, 7C/C4 31:0 MBOX1 moved to PCI Address 7C when Messaging Queue is enabled 48 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers New Register Definitions Summary Table 4-2. Register Differences between PCI 9080 and PCI 9060 (continued) Register INTCSR PCI/Local Offset Bits 68/E8 3 Mailbox Interrupt Enable Description 28 Mailbox 0 Interrupt Status 29 Mailbox 1 Interrupt Status 30 Mailbox 2 Interrupt Status 31 Mailbox 3 Interrupt Status PCIHIDR 70/F0 31:0 PCI Permanent Configuration ID register PCIHREV 74/F4 7:0 PCI Permanent Revision ID register DMAMODE0 80/100 13 Write and Invalidate Mode for DMA Channel 0 transfers 13 DMA Write and Invalidate Mode 14 DMA EOT[1:0]# (End of Transfer) Input Pin Enable 15 DMA Stop Data Transfer Mode 16 DMA Clear Count Mode 17 DMA Interrupt Select DMADPR0 90/110 0 DMA Descriptor Location Selector (PCI or Local) DMAMODE1 94/114 13 DMA Write and Invalidate Mode 14 DMA EOT[1:0]# (End of Transfer) Input Pin Enable 15 DMA Stop Data Transfer Mode 16 DMA Clear Count Mode 17 DMA Interrupt Select DMADPR1 A4/124 0 DMA Descriptor Location Selector (PCI or Local) DMACSR0 A8/128 4 DMA Channel 0 Done DMACSR1 A9/129 4 DMA Channel 1 Done DMATHR B0/130 15:0 Changed thresholds to accommodate 32-word Write FIFOs OPQIS 30/B0 31:0 Outbound Post Queue Interrupt Status register OPQIM 34/B4 31:0 Outbound Post Queue Interrupt Mask register IQP 40 31:0 Inbound Queue Port OQP 44 31:0 Outbound Queue Port MQCR C0/140 31:0 Messaging Queue Configuration register QBAR C4/144 31:0 Queue Base Address register IFHPR C8/148 31:0 Inbound Free Head Pointer register IFTPR CC/14C 31:0 Inbound Free Tail Pointer register IPHPR D0/150 31:0 Inbound Post Head Pointer register IPTPR D4/154 31:0 Inbound Post Tail Pointer register OFHPR D8/158 31:0 Outbound Free Head Pointer register OFTPR DC/15C 31:0 Outbound Free Tail Pointer register OFHPR E0/160 31:0 Outbound Post Head Pointer register OPTPR E4/164 31:0 Outbound Post Tail Pointer register QSR E8/168 7:0 Queue Status/Control register PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 49 Section 4 Registers New Register Definitions Summary Table 4-3. Register Differences between PCI 9080 and PCI 9060ES Register PCI/Local Offset Bits PCIIDR 00/00 31:16 Description Default changed from PCI 906E to PCI 9080 PCISR 06/06 6 PCICLSR 0C/0C 7:0 User-definable bit added Cache line size is now used for Memory Write and Invalidate PCIBAR0 10/10 8:6 Register Bank size changed from 128 to 256 PCIBAR1 14/14 8:6 Register Bank size changed from 128 to 256 PCIBAR3 1C/1C 31:0 Base address register for Local Address Space 1 PCISVID 2C/2C 15:0 Subsystem Vendor ID register PCISID 2E/2E 15:0 Subsystem ID register MARBR 08, AC/88, 12C 20:19 DMA Channel Priority BIGEND 0C/8C 23 PCI Request Mode 25 PCI Read/No Write Mode 26 PCI Read with Write Flush Mode 27 Get Local Bus Latency Timer with BREQ 28 PCI Read/No Flush Mode 5 Direct Slave Big Endian Mode 6 DMA Channel 1 Big Endian Mode 7 DMA Channel 0 Big Endian Mode BREQo Timer Resolution control EROMBA 14/94 5 LBRD0 18/98 1:0 15 17:16 25 DMPBAM 28/A8 12, 3 10, 8:5 11 13 15:14 Local Bus width now programmable in S mode Single Read Access Mode removed Local Bus width now programmable in S mode Extra Long Serial EEPROM Load Direct Master Read Prefetch Size Control Programmable Almost Full Flag increased by one bit Direct Master Prefetch Limit I/O Remap Slect Direct Master Write Delay LAS1RR F0/170 31:0 Local Address Space 1 Range register LAS1BA F4/174 31:0 Local Address Space 1 Local Base Address register (Remap) LBRD1 F8/178 31:0 Local Address Space 1 Bus Region Descriptor register MBOX0 40, 78/C0 31:0 MBOX0 moved to PCI Address 78 when the Messaging Queue is enabled MBOX1 44, 7C/C4 31:0 MBOX1 moved to PCI Address 7C when the Messaging Queue is enabled MBOX4 50/D0 31:0 MBOX4 added MBOX5 54/D4 31:0 MBOX5 added MBOX6 58/D8 31:0 MBOX6 added MBOX7 5C/DC 31:0 MBOX7 added P2LDBELL 60/E0 31:8 24 more Doorbell bits added to PCI-to-Local Doorbell register L2PDBELL 64/E4 31:8 INTCSR 68/E8 3 50 24 more Doorbell bits added to Local-to-PCI Doorbell register Mailbox Interrupt Enable PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers New Register Definitions Summary Table 4-3. Register Differences between PCI 9080 and PCI 9060ES (continued) Register PCI/Local Offset Bits INTCSR 68/E8 18 Description DMA Channel 0 Interrupt Enable 19 DMA Channel 1 Interrupt Enable 21 DMA Channel 0 Interrupt Status 22 DMA Channel 1 Interrupt Status 25 DMA Channel 0 active during abort 26 DMA Channel 1 active during abort 28 Mailbox 0 Interrupt Status 29 Mailbox 1 Interrupt Status 30 Mailbox 2 Interrupt Status 31 Mailbox 3 Interrupt Status CNTRL 6C/EC 3:0 Read command for DMA 7:4 Write command for DMA PCIHREV 74/F4 7:0 PCI Permanent Revision ID register DMAMODE0 80/100 31:0 DMA Channel 0 Mode register DMAPADR0 84/104 31:0 DMA Channel 0 PCI Address register DMALADR0 88/108 31:0 DMA Channel 0 Local Address register DMASIZ0 8C/10C 31:0 DMA Channel 0 Size register DMADPR0 90/110 31:0 DMA Channel 0 Descriptor Pointer register DMAMODE1 94/114 31:0 DMA Channel 1 Mode register DMAPADR1 98/108 31:0 DMA Channel 1 PCI Address register DMALADR1 9C/11C 31:0 DMA Channel 1 Local Address register DMASIZ1 A0/120 31:0 DMA Channel 1 Size register DMADPR1 A4/124 31:0 DMA Channel 1 Descriptor Pointer register DMACSR0 A8/128 7:0 DMA Channel 0 Command/Status DMACSR1 A9/129 7:0 DMA Channel 1 Command/Status DMATHR B0/130 31:0 DMA Threshold register OPQIS 30/B0 31:0 Outbound Post Queue Interrupt Status register OPQIM 34/B4 31:0 Outbound Post Queue Interrupt Mask register 40 31:0 Inbound Queue Port IQP OQP 44 31:0 Outbound Queue Port MQCR C0/140 31:0 Messaging Queue Configuration register QBAR C4/144 31:0 Queue Base Address register IFHPR C8/148 31:0 Inbound Free Head Pointer register IFTPR CC/14C 31:0 Inbound Free Tail Pointer register IPHPR D0/150 31:0 Inbound Post Head Pointer register IPTPR D4/154 31:0 Inbound Post Tail Pointer register OFHPR D8/158 31:0 Outbound Free Head Pointer register OFTPR DC/15C 31:0 Outbound Free Tail Pointer register OFHPR E0/160 31:0 Outbound Post Head Pointer register OPTPR E4/164 31:0 Outbound Post Tail Pointer register QSR E8/168 7:0 Queue Status/Control register PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 51 Section 4 Registers New Register Definitions Summary Table 4-4. Register Differences between PCI 9080 and PCI 9060SD Register PCI/Local Offset Bits PCIIDR 00/00 31:16 Description Default changed from PCI 906D to PCI 9080 PCISR 06/06 6 PCIBAR0 10/10 8:6 Register Bank size changed from 128 to 256 User-definable bit added PCIBAR1 14/14 8:6 Register Bank size changed from 128 to 256 PCISVID 2C/2C 15:0 Subsystem Vendor ID register PCISID 2E/2E 15:0 Subsystem ID register MARBR 08, AC/88, 12C 31:0 Mode/Arbitration register now accessible from the PCI Bus BIGEND EROMBA 0C/8C 14/94 23 PCI Request Mode 28 PCI Read/No Flush Mode 1 Direct Master Big Endian Mode 7 DMA Channel 0 Big Endian Mode 3:0 Direct Slave BREQo Delay Clocks 4 5 LBRD0 18/98 1:0 15 17:16 Local Bus BREQo Enable BREQo Timer Resolution control Local Bus width now programmable in S mode Single Read Access Mode removed Local Bus width now programmable in S mode DMRR 1C/9C 31:16 Local Range register for Direct Master to PCI DMLBAM 20/A0 31:0 Local Bus Base Address register for Direct Master to PCI Memory DMLBAI 24/A4 31:0 Local Bus Base Address register for Direct Master to PCI IO/CFG DMPBAM 28/A8 31:0 PCI Base Address (Remap) register for Direct Master to PCI Memory LAS1RR F0/170 31:0 Local Address Space 1 Range register was at 30/B0 in PCI 9060SD LAS1BA F4/174 31:0 Local Address Space 1 Local Base Address register (Remap) was at 34/B4 in PCI 9060SD LBRD1 F8/178 31:0 Local Address Space 1 Bus Region Descriptor register was at 38/B8 in PCI 9060SD LBRD1 F8/178 15 Single Read Access Mode removed MBOX0 40,78/C0 31:0 MBOX0 moved to PCI Address 78 when the Messaging Queue is enabled MBOX1 44, 7C/C4 31:0 MBOX1 moved to PCI Address 7C when the Messaging Queue is enabled MBOX4 50/D0 31:0 MBOX4 added MBOX5 54/D4 31:0 MBOX5 added MBOX6 58/D8 31:0 MBOX6 added MBOX7 5C/DC 31:0 MBOX7 added INTCSR 68/E8 18 DMA Channel 0 Interrupt Enable 21 DMA Channel 0 Interrupt Active PCIHREV 52 74/F4 24 Direct Master active during abort 25 DMA Channel 0 active during abort 7:0 PCI Permanent Revision ID register PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers New Register Definitions Summary Table 4-4. Register Differences between PCI 9080 and PCI 9060SD (continued) Register PCI/Local Offset Bits Description DMAMODE0 80/100 31:0 DMA Channel 0 Mode register DMAPADR0 84/104 31:0 DMA Channel 0 PCI Address register DMALADR0 88/108 31:0 DMA Channel 0 Local Address register DMASIZ0 8C/10C 31:0 DMA Channel 0 Transfer Size register DMADPR0 90/110 31:0 DMA Channel 0 Descriptor Pointer register DMACSR0 A8/128 7:0 DMA Channel 0 Command/Status register DMATHR B0/130 15:0 DMA Channel 0 Thresholds OPQIS 30/B0 31:0 Outbound Post Queue Interrupt Status register OPQIM 34/B4 31:0 Outbound Post Queue Interrupt Mask register IQP 40 31:0 Inbound Queue Port OQP 44 31:0 Outbound Queue Port MQCR C0/140 31:0 Messaging Queue Configuration register QBAR C4/144 31:0 Queue Base Address register IFHPR C8/148 31:0 Inbound Free Head Pointer register IFTPR CC/14C 31:0 Inbound Free Tail Pointer register IPHPR D0/150 31:0 Inbound Post Head Pointer register IPTPR D4/154 31:0 Inbound Post Tail Pointer register OFHPR D8/158 31:0 Outbound Free Head Pointer register OFTPR DC/15C 31:0 Outbound Free Tail Pointer register OFHPR E0/160 31:0 Outbound Post Head Pointer register OPTPR E4/164 31:0 Outbound Post Tail Pointer register QSR E8/168 7:0 Queue Status/Control register PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 53 Section 4 Registers Register Address Mapping 4.2 Register Address Mapping Table 4-5. PCI Configuration Registers PCI CFG Register Address (Offset from Chip Select Address) To ensure software compatibility with other versions of the PCI 9080 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 24 23 16 15 8 7 PCI/Local Writable Serial EEPROM Writable 0 00h 00h Device ID Vendor ID Local Y 04h 04h Status Command Y N 08h 08h 0Ch 0Ch Class Code BIST Header Type PCI Latency Timer Revision ID Local Y Cache Line Size Y [15:0], Local N 10h 10h PCI Base Address 0 for Memory-Mapped Configuration Registers (PCIBAR0) Y N 14h 14h PCI Base Address 1 for I/O Mapped Configuration Registers (PCIBAR1) Y N 18h 18h PCI Base Address 2 for Local Address Space 0 (PCIBAR2) Y N 1Ch 1Ch PCI Base Address 3 for Local Address Space 1 (PCIBAR3) Y N 20h 20h Unused Base Address (PCIBAR4) N N 24h 24h Unused Base Address (PCIBAR5) N N N N Local Y 28h 28h 2Ch 2Ch 30h 30h PCI Base Address for Local Expansion ROM Y Y 34h 34h Reserved N N N N Y [7:0], Local Y 38h 38h 3Ch 3Ch Note: 54 Local Access Cardbus CIS Pointer (Not Supported) Subsystem ID Subsystem Vendor ID Reserved Max_Lat Min_Gnt Interrupt Pin Interrupt Line Refer to PCI Specification v2.1 for definitions of these registers. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers Register Address Mapping Table 4-6. Local Configuration Registers PCI (Offset from Base Address) Local Access (Offset from Chip Select Address) To ensure software compatibility with other versions of the PCI 9080 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 PCI/Local Writable Serial EEPROM Writable 0 00h 80h Range for PCI-to-Local Address Space 0 Y Y 04h 84h Local Base Address (Remap) for PCI-to-Local Address Space 0 Y Y 08h 88h Mode/Arbitration Register Y Y 0Ch 8Ch Big/Little Endian Descriptor Register Y Y 10h 90h Range for PCI-to-Local Expansion ROM Y Y 14h 94h Local Base Address (Remap) for PCI-to-Local Expansion ROM and BREQo control Y Y 18h 98h Local Bus Region Descriptors (Space 0 and Expansion ROM) for PCI-to-Local Accesses Y Y 1Ch 9Ch Range for Direct Master to PCI Y Y 20h A0h Local Base Address for Direct Master to PCI Memory Y Y 24h A4h Local Base Address for Direct Master to PCI IO/CFG Y Y 28h A8h PCI Base Address (Remap) for Direct Master to PCI Y Y 2Ch ACh PCI Configuration Address Register for Direct Master to PCI IO/CFG Y Y F0h 170h Range for PCI-to-Local Address Space 1 Y Y F4h 174h Local Base Address (Remap) for PCI-to-Local Address Space 1 Y Y F8h 178h Local Bus Region Descriptor (Space 1) for PCI-to-Local Accesses Y Y PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 55 Section 4 Registers Register Address Mapping Table 4-7. Runtime Registers PCI (Offset from Base Address) Local Access (Offset from Chip Select Address) To ensure software compatibility with other versions of the PCI 9080 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 PCI/Local Writable Serial EEPROM Writable 0 40h C0h Mailbox Register 0 (refer to Note) Y Y 44h C4h Mailbox Register 1 (refer to Note) Y Y 48h C8h Mailbox Register 2 Y N 4Ch CCh Mailbox Register 3 Y N 50h D0h Mailbox Register 4 Y N 54h D4h Mailbox Register 5 Y N 58h D8h Mailbox Register 6 Y N 5Ch DCh Mailbox Register 7 Y N 60h E0h PCI-to-Local Doorbell Register Y N 64h E4h Local-to-PCI Doorbell Register Y N 68h E8h Interrupt Control / Status Y N 6Ch ECh Serial EEPROM Control, PCI Command Codes, User I/O Control, Init Control Y N 70h F0h Device ID Vendor ID N N 74h F4h Unused Revision ID N N 78h C0h Mailbox Register 0 (see Note) Y N 7Ch C4h Mailbox Register (see Note) Y N Note: Mailbox registers 0 and 1 are always accessible at addresses 78h/C0h and 7Ch/C4. When the I2O feature is disabled (QSR[0]=0), Mailbox registers 0 and 1 are also accessible at PCI Addresses 40h and 44h for PCI 9060 compatibility. When the I2O feature is enabled, the Inbound and Outbound Queue pointers are accessed at addresses 40h and 44h, replacing the Mailbox registers in PCI Address space. 56 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers Register Address Mapping Table 4-8. DMA Registers PCI (Offset from Base Address) Local Access (Offset from Chip Select Address) To ensure software compatibility with other versions of the PCI 9080 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 PCI/Local Writable Serial EEPROM Writable 0 80h 100h DMA Ch 0 Mode Y N 84h 104h DMA Ch 0 PCI Address Y N 88h 108h DMA Ch 0 Local Address Y N 8Ch 10Ch DMA Ch 0 Transfer Byte Count Y N 90h 110h DMA Ch 0 Descriptor Pointer Y N 94h 114h DMA Ch 1 Mode Y N 98h 118h DMA Ch 1 PCI Address Y N 9Ch 11Ch DMA Ch 1 Local Address Y N A0h 120h DMA Ch 1 Transfer Byte Count Y N A4h 124h DMA Ch 1 Descriptor Pointer Y N A8h 128h Y N ACh 12Ch Mode/Arbitration Register Y N B0h 130h DMA Threshold Register Y N PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Reserved DMA Channel 1 Command/Status Register DMA Channel 0 Command/Status Register 57 Section 4 Registers Register Address Mapping Table 4-9. Messaging Queue Registers PCI (Offset from Base Address) Local Access (Offset from Chip Select Address) To ensure software compatibility with other versions of the PCI 9080 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 PCI/Local Writable Serial EEPROM Writable 0 30h B0h Outbound Post Queue Interrupt Status N N 34h B4h Outbound Post Queue Interrupt Mask Y N 40h -- Inbound Queue Port PCI N 44h -- Outbound Queue Port PCI N C0h 140h Messaging Unit Configuration Register Y N C4h 144h Queue Base Address Register Y N C8h 148h Inbound Free Head Pointer Register Y N CCh 14Ch Inbound Free Tail Pointer Register Y N D0h 150h Inbound Post Head Pointer Register Y N D4h 154h Inbound Post Tail Pointer Register Y N D8h 158h Outbound Free Head Pointer Register Y N DCh 15Ch Outbound Free Tail Pointer Register Y N E0h 160h Outbound Post Head Pointer Register Y N E4h 164h Outbound Post Tail Pointer Register Y N E8h 168h Queue Status/Control Register Y N Notes: When I2O messaging is enabled (QSR[0]=1), the PCI Master (Host or another IOP) uses the Inbound Queue Port to read Message Frame Addresses (MFAs) from the Inbound Free List FIFO and to write MFAs to the Inbound Post List FIFO. The PCI Master (Host or another IOP) uses the Outbound Queue Port to read MFAs from the Outbound Post List FIFO and to write MFAs to the Outbound Free List FIFO. Each Inbound MFA is specified by I2O as offset from PCI Base Address 0 (programmed in register PCIBAR0 at offset 10h) to start of message frame. This means that all inbound message frames should reside in PCI Base Address 0 memory space. Each Outbound Message Frame Address (MFA) is specified by I2O as offset from system address 0x00000000h. The Outbound MFA is the physical 32-bit address of a frame in shared PCI system memory. The Inbound and Outbound Queues may reside in Local Address Space 0 or 1 by programming the QSR register. The queues need not be in shared memory. 58 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers PCI Configuration Registers 4.3 PCI Configuration Registers All registers may be written to or read from in Byte, Word, or Lword accesses. Table 4-10. (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register Bit Description Read Write Value after Reset 15:0 Vendor ID. Identifies device manufacturer. Defaults to PCI SIG issued vendor ID of PLX (10B5h) if no serial EEPROM is present and pin NB# (no Local Bus initialization) is asserted low. Yes Local/ Serial EEPROM 10B5h or 0 31:16 Device ID. Identifies particular device. Defaults to PLX part number for PCI interface chip (PCI 9080) if no serial EEPROM is present and pin NB# (no Local Bus initialization) is asserted low. Yes Local/ Serial EEPROM 9080h or 0 Read Write Value after Reset Table 4-11. (PCICR; PCI:04h, LOC:04h) PCI Command Register Bit Description 0 I/O Space. Value of 1 allows device to respond to I/O Space accesses. Value of 0 disables device from responding to I/O Space accesses. Yes Yes 0 1 Memory Space. Value of 1 allows device to respond to Memory Space accesses. Value of 0 disables device from responding to Memory Space accesses. Yes Yes 0 2 Master Enable. Value of 1 allows device to behave as Bus Master. Value of 0 disables device from generating Bus Master accesses. This bit must be set for the PCI 9080 to perform Direct Master or DMA cycles. Yes Yes 0 3 Special Cycle. Not supported. Yes No 0 4 Memory Write and Invalidate. Value of 1 enables Memory Write and Invalidate. Value of 0 disables Memory Write and Invalidate. (Refer to DMA Mode Registers for Direct Master, DMAMODE0, and DMAMODE1[13], as well as (DMPBAM[13], DMAMODE0[13], and DMAMODE1[13], respectively). Yes Yes 0 5 VGA Palette Snoop. Not supported. Yes No 0 6 Parity Error Response. Value of 0 indicates parity error is ignored and operation continues. Value of 1 indicates parity checking is enabled. Yes Yes 0 7 Wait Cycle Control. Controls whether device performs address/data stepping. Value of 0 indicates device never does stepping. Value of 1 indicates device always does stepping. Yes No 0 Note: Hardcoded to 0. 8 SERR# Enable. Value of 1 enables SERR# driver. Value of 0 disables SERR# driver. Yes Yes 0 9 Fast Back-to-Back Enable. Indicates type of fast back-to-back transfers Master can perform on bus. Value of 1 indicates fast back-to-back transfers can occur to any agent on bus. Value of 0 indicates fast back-to-back transfers can only occur to same agent as previous cycle. Yes No 0 Reserved. Yes No 0 15:10 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 59 Section 4 Registers PCI Configuration Registers Table 4-12. (PCISR; PCI:06h, LOC:06h) PCI Status Register Bit Description Read Write Value after Reset 5:0 Reserved. Yes No 0 6 If high, supports User Definable Features. This bit can only be written from the Local Bus. Read-only from the PCI Bus. Yes Local 0 7 Fast Back-to-Back Capable. When set to 1, indicates adapter can accept fast back-to-back transactions. Value of 0 indicates adapter cannot. Yes No 1 8 Master Data Parity Error Detected. This bit is set to 1 when three conditions are met: 1) The PCI 9080 asserted PERR# itself or observed PERR# asserted; 2) The PCI 9080 was Bus Master for operation in which error occurred; 3) Parity Error Response bit in Command Register is set. Writing 1 clears the bit (0). Yes Yes/Clr 0 DEVSEL Timing. Indicates timing for DEVSEL# assertion. Value of 01 indicates medium decode. Yes No 01 10:9 Note: Hardcoded to 01. 11 Target Abort. When set to 1, indicates the PCI 9080 has signaled a Target abort. Writing a 1 clears the bit (0). Yes Yes/Clr 0 12 Received Target Abort. When set to 1, indicates the PCI 9080 has received Target abort signal. Writing a 1 clears the bit (0). Yes Yes/Clr 0 13 Master Abort. When set to 1, indicates the PCI 9080 has generated Master abort signal. Writing a 1 clears the bit (0). Yes Yes/Clr 0 14 Signaled System Error. When set to 1, indicates the PCI 9080 has reported a system error on SERR# signal. Writing a 1 clears the bit (0). Yes Yes/Clr 0 15 Detected Parity Error. When set to 1, indicates the PCI 9080 has detected a PCI Bus parity error, even if parity error handling is disabled (Parity Error Response bit in Command register is clear). One of three conditions can cause this bit to be set. 1) The PCI 9080 detected parity error during PCI Address phase; 2) The PCI 9080 detected a data parity error when it was Target of a write; 3) The PCI 9080 detected a data parity error when performing Master Read operation. Writing a 1 clears the bit (0). Yes Yes/Clr 0 Read Write Value after Reset Yes Local/ Serial EEPROM Current Rev # Read Write Value after Reset Table 4-13. (PCIREV; PCI:08h, LOC:08h) PCI Revision ID Register Bit Description 7:0 Revision ID. Silicon revision of the PCI 9080. Table 4-14. (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code Register 60 Bit Description 7:0 Register Level Programming Interface. 00h = Queue Ports at 40h and 44h. 01h = Queue Ports at 40h and 44h, and Int Status and Int Mask at 30h and 34h, respectively. Yes Local/ Serial EEPROM 00 15:8 Subclass Code. 80h = Other Bridge Device, 00h = I2O Device. Yes Local/ Serial EEPROM 80h 23:16 Base Class Code. 06h = Bridge Device, 0Eh = I2O controller. Yes Local/ Serial EEPROM 06h PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers PCI Configuration Registers Table 4-15. (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size Register Bit Description 7:0 System cache line size in units of 32-bit words. Read Write Value after Reset Yes Yes 0 Read Write Value after Reset Yes Yes 0 Read Write Value after Reset Table 4-16. (PCILTR; PCI:0Dh, LOC:0Dh) PCI Latency Timer Register Bit Description 7:0 PCI Latency Timer. Units of PCI Bus clocks that specify amount of time the PCI 9080, as a Bus Master, can burst data on the PCI Bus. Table 4-17. (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type Register Bit Description 6:0 Configuration Layout Type. Specifies layout of bits 10h through 3Fh in configuration space. Only one encoding 0 is defined. All other encodings are reserved. Yes Local 0 Header Type. Value of 1 indicates multiple functions. Value of 0 indicates single function. Yes Local 0 Read Write Value after Reset 7 Table 4-18. (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) Register Bit Description 3:0 Value of 0 indicates device passed its test. Nonzero values indicate device failed. Device specific failure codes can be encoded in nonzero value. Yes Local 0 5:4 Reserved. Device returns 0. Yes No 0 PCI writes 1 to invoke BIST. Generates interrupt to Local Bus. Local Bus resets the bit when BIST is complete. Software should fail device if BIST is not complete after two seconds. Yes Yes 0 Yes Local 0 6 Refer to Runtime registers for interrupt control/status. 7 Returns 1 if device supports BIST. Returns 0 if device is not BIST compatible. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 61 Section 4 Registers PCI Configuration Registers Table 4-19. (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses to Local, Runtime, and DMA Registers Bit 0 Description Memory Space Indicator. Value of 0 indicates register maps into memory space. Value of 1 indicates register maps into I/O space. Note: 2:1 Read Write Value after Reset Yes No 0 Yes No 0 Yes No 0 Yes No 0 Yes Yes 0 Hardcoded to 0. Location of Register. Location values: 00--Locate anywhere in 32-bit memory address space 01--Locate below 1 MB memory address space 10--Locate anywhere in 64-bit memory address space 11--Reserved Note: 3 Note: 7:4 Hardcoded to 0. Memory Base Address. Memory base address for access to Local, Runtime, and DMA registers (default is 256 bytes). Note: 31:8 Hardcoded to 0. Prefetchable. Value of 1 indicates there are no side effects on reads. Does not affect operation of the PCI 9080. Hardcoded to 0. Memory Base Address. Memory base address for access to Local, Runtime, and DMA registers. Note: For I2O, Inbound message frame pool must reside in address space pointed to by PCIBAR0. Message Frame Address (MFA) is defined by I2O as offset from this base address to start of message frame. Table 4-20. (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses to Local, Runtime, and DMA Registers Bit 0 Description Memory Space Indicator. Value of 0 indicates register maps into memory space. Value of 1 indicates register maps into I/O space. Note: 1 Write Value after Reset Yes No 1 Hardcoded to 1. Reserved. Yes No 0 7:2 I/O Base Address. Base Address for I/O access to Local, Runtime, and DMA registers. (Default is 256 bytes) Yes No 0 31:8 I/O Base Address. Base Address for I/O access to Local, Runtime, and DMA registers. Yes Yes 0 Note: 62 Read Hardcoded to 0. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers PCI Configuration Registers Table 4-21. (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to Local Address Space 0 Bit 0 Description Memory Space Indicator. Value of 0 indicates register maps into memory space. Value of 1 indicates register maps into I/O space. Read Write Value after Reset Yes No 0 Yes Mem: No 0 (Specified in LAS0RR register.) 2:1 Location of Register (If Memory Space). Location values: 00--Locate anywhere in 32-bit memory address space 01--Locate below 1-MB memory address space 10--Locate anywhere in 64-bit memory address space 11--Reserved I/O: No for bit 1, Yes for bit 2 (Specified in LAS0RR register.) If I/O Space, bit 1 is always 0 and bit 2 is included in the base address. 3 Prefetchable (If Memory Space). Value of 1 indicates there are no side effects on reads. Reflects value of LAS0RR[3] and provides only status to system. Does not affect operation of the PCI 9080. The prefetching features of this address space are controlled by the associated Bus Region Descriptor register. Yes Mem: No 0 I/O: Yes (Specified in LAS0RR register.) If I/O Space, bit 3 is included in the base address. 31:4 Note: Memory Base Address. Memory base address for access to Local Address Space 0. Yes Yes 0 PCIBAR2 can be enabled or disabled by setting or clearing LAS0BA[0]. Table 4-22. (PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses to Local Address Space 1 Bit 0 Description Memory Space Indicator. Value of 0 indicates register maps into memory space. Value of 1 indicates register maps into I/O space. Read Write Value after Reset Yes No 0 Yes Mem: No 0 (Specified in LAS1RR register.) 2:1 Location of register. Location values: 00--Locate anywhere in 32-bit memory address space 01--Locate below 1-MB memory address space 10--Locate anywhere in 64-bit memory address space 11--Reserved I/O: No for bit 1, Yes for bit 2 (Specified in LAS1RR register.) If I/O Space, bit 1 is always 0 and bit 2 is included in the base address. 3 Prefetchable (If Memory Space). Value of 1 indicates there are no side effects on reads. Reflects value of LAS1RR[3] and only provides status to the system. Does not affect operation of the PCI 9080. The prefetching features of this address space are controlled by the associated Bus Region Descriptor register. Yes Mem: No 0 I/O: Yes (Specified in LAS1RR register.) If I/O Space, bit 3 is included in the base address. 31:4 Note: Memory Base Address. Memory base address for access to Local Address Space 1. Yes Yes 0 PCIBAR3 can be enabled or disabled by setting or clearing LAS1BA[0]. If QSR[0] is set, PCIBAR3 returns 0. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 63 Section 4 Registers PCI Configuration Registers Table 4-23. (PCIBAR4; PCI:20h, LOC:20h) PCI Base Address Register Bit Read Write Value after Reset Yes No 0 Read Write Value after Reset Yes No 0 Read Write Value after Reset Yes No 0 Read Write Value after Reset Yes Local/ Serial EEPROM 10B5 Read Write Value after Reset Yes Local/ Serial EEPROM 9080h Read Write Value after Reset Address Decode Enable. Value of 1 indicates device accepts accesses to Expansion ROM address. Value of 0 indicates device does not accept accesses to Expansion ROM space. Should be set to 1 by PCI Host if Expansion ROM is present. Yes Yes 0 10:1 Reserved. Yes No 0 31:11 Expansion ROM Base Address (upper 21 bits). Yes Yes 0 Read Write Value after Reset Yes Yes 0 31:0 Description Reserved. Table 4-24. (PCIBAR5; PCI:24h, LOC:24h) PCI Base Address Register Bit 31:0 Description Reserved. Table 4-25. (PCICIS; PCI:28h, LOC:28h) PCI Cardbus CIS Pointer Register Bit 31:0 Description Cardbus Information Structure Pointer for PCMCIA. Not supported. Table 4-26. (PCISVID; PCI:2Ch, LOC:2Ch) PCI Subsystem Vendor ID Register Bit 15:0 Description Subsystem Vendor ID (unique add-in board Vendor ID). Table 4-27. (PCISID; PCI:2Eh, LOC:2Eh) PCI Subsystem ID Register Bit 15:0 Description Subsystem ID (unique add-in board Device ID). Table 4-28. (PCIERBAR; PCI:30h, LOC:30h) PCI Expansion ROM Base Register Bit 0 Description Table 4-29. (PCIILR; PCI:3Ch, LOC:3Ch) PCI Interrupt Line Register 64 Bit Description 7:0 Interrupt Line Routing Value. Indicates which input of system interrupt controller(s) to which the interrupt line of device is connected. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers PCI Configuration Registers Table 4-30. (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Register Bit Description 7:0 Interrupt Pin Register. Indicates which interrupt pin device uses. The following values are decoded: Read Write Value after Reset Yes Local/ Serial EEPROM 1 Read Write Value after Reset Yes Local/ Serial EEPROM 0 Read Write Value after Reset Yes Local/ Serial EEPROM 0 0 = No Interrupt Pin 1 = INTA# 2 = INTB# 3 = INTC# 4 = INTD# Note: The PCI 9080 supports only one PCI interrupt pin (INTA#). Table 4-31. (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Register Bit Description 7:0 Min_Gnt. Specifies how long a burst period device needs, assuming clock rate of 33 MHz. Value is multiple of 1/4 s increments. Table 4-32. (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat Register Bit Description 7:0 Max_Lat. Specifies how often device must gain access to PCI Bus. Value is multiple of 1/4 s increments. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 65 Section 4 Registers Local Configuration Registers 4.4 Local Configuration Registers Table 4-33. (LAS0RR; PCI:00h, LOC:80h) Local Address Space 0 Range Register for PCI-to-Local Bus Bit 0 2:1 Description Read Write Value after Reset Memory Space Indicator. Value of 0 indicates Local address Space 0 maps into PCI memory space. Value of 1 indicates address Space 0 maps into PCI I/O space. Yes Yes 0 If mapped into memory space, encoding is as follows: Yes Yes 0 2/1 Meaning 00 01 10 11 Locate anywhere in 32-bit PCI Address space Locate below 1 MB in PCI Address space Locate anywhere in 64-bit PCI Address space Reserved If mapped into I/O space, bit 1 must be set to 0. Bit 2 is included with bits [31:3] to indicate decoding range. 3 If mapped into memory space, value of 1 indicates reads are prefetchable (does not affect operation of the PCI 9080, but is used for system status). If mapped into I/O space, included with bits [31:2] to indicate decoding range. Yes Yes 0 31:4 Specifies which PCI Address bits to use for decoding PCI access to Local Bus Space 0. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to Address bit 31. Write 1 to all bits to be included in decode and 0 to all others (used in conjunction with PCI Configuration register 18h). Default is 1 MB. Yes Yes FFF0000h Notes: Range (not Range register) must be power of 2. "Range register value" is inverse of range. User should limit all I/O spaces to 256 bytes per PCI Specification v2.1. Table 4-34. (LAS0BA; PCI:04h, LOC:84h) Local Address Space 0 Local Base Address (Remap) Register Bit 0 Description Space 0 Enable. Value of 1 enables decoding of PCI Addresses for Direct Slave access to Local Space 0. Value of 0 disables decoding. If set to 0, PCI BIOS may not allocate (assign) base address for Space 0. Note: 1 Write Value after Reset Yes Yes 0 Must be set to 1 for any Direct Slave access to Space 0. Reserved. Yes No 0 3:2 If Local Space 0 is mapped into memory space, bits are not used. If mapped into I/O space, bit is included with bits [31:4] for remapping. Yes Yes 0 31:4 Remap of PCI Address to Local Address Space 0 into a Local Address Space. Remap (replace) PCI Address bits used in decode as Local Address bits. Yes Yes 0 Note: 66 Read Remap Address value must be multiple of Range (not Range register). PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers Local Configuration Registers Table 4-35. (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/Arbitration Register Bit Description Read Write Value after Reset 7:0 Local Bus Latency Timer. Number of Local Bus Clock cycles before de-asserting HOLD and releasing the Local Bus. Also used with bit 27 to delay BREQ input to give up the Local Bus only when this timer expires. Yes Yes 00 15:8 Local Bus Pause Timer. Number of Local Bus Clock cycles before reasserting HOLD after releasing the Local Bus. Yes Yes 00 Yes Yes 0 Note: 16 Applicable only to DMA operation. Local Bus Latency Timer Enable. Value of 1 enables latency timer. 17 Local Bus Pause Timer Enable. Value of 1 enables pause timer. Yes Yes 0 18 Local Bus BREQ Enable. Value of 1 enables Local Bus BREQ input. When BREQ input is active, the PCI 9080 de-asserts HOLD and releases Local Bus. Yes Yes 0 20:19 DMA Channel Priority. Value of 00 indicates rotational priority scheme. Value of 01 indicates Channel 0 has priority. Value of 10 indicates Channel 1 has priority. Value of 11 is reserved. Yes Yes 0 21 Local Bus Direct Slave Give up Bus Mode. When set to 1, the PCI 9080 de-asserts HOLD and releases the Local Bus when the Direct Slave Write FIFO becomes empty during a Direct Slave Write or when the Direct Slave Read FIFO becomes full during a Direct Slave Read. Yes Yes 1 22 Direct Slave LLOCKo# Enable. Value of 1 enables PCI Direct Slave locked sequences. Value of 0 disables Direct Slave locked sequences. Yes Yes 0 23 PCI Request Mode. Value of 1 causes the PCI 9080 to de-assert REQ when it asserts FRAME during a Master cycle. Value of 0 causes the PCI 9080 to leave REQ asserted for the entire Bus Master cycle. Yes Yes 0 24 PCI Specification v2.1 Mode. When set to 1, the PCI 9080 operates in Delayed Transaction mode for Direct Slave Reads. The PCI 9080 issues a Retry and prefetches Read data. Yes Yes 0 25 PCI Read No Write Mode. Value of 1 forces Retry on Writes if Read is pending. Value of 0 allows Writes to occur while Read is pending. Yes Yes 0 26 PCI Read with Write Flush Mode. Value of 1 submits request to flush pending a Read cycle if a Write cycle is detected. Value of 0 submits request to not effect pending Reads when a Write cycle occurs (PCI Specification v2.1 compatible). Yes Yes 0 27 Gate Local Bus Latency Timer with BREQ. If set to 0, the PCI 9080 gives up the Local Bus during Direct Slave or DMA transfer after the current cycle (if enabled and BREQ is sampled). If set to 1, the PCI 9080 gives up the Local Bus only if BREQ is sampled and the Local Bus Latency Timer is enabled and expired during a Direct Slave or DMA transfer. Yes Yes 0 28 PCI Read No Flush Mode. Value of 1 submits a request to not flush the Read FIFO if a PCI Read cycle completes (Read Ahead mode). Value of 0 submits a request to flush the Read FIFO if a PCI Read cycle completes. Yes Yes 0 29 If set to 0, reads from PCI Configuration register address 00h and returns Device ID and Vendor ID. If set to 1, reads from PCI Configuration Register address 00h and returns Subsystem ID and Subsystem Vendor ID. Yes Yes 0 Reserved. Yes No 0 31:30 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 67 Section 4 Registers Local Configuration Registers Table 4-36. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register Bit Read Write Value after Reset 0 Configuration Register Big Endian Mode. Value of 1 specifies use of Big Endian data ordering for Local accesses to the Configuration registers. Value of 0 specifies Little Endian ordering. Big Endian mode can be specified for Configuration Register accesses by asserting BIGEND# pin during Address phase of access. Yes Yes 0 1 Direct Master Big Endian Mode. Value of 1 specifies use of Big Endian data ordering for Direct Master accesses. Value of 0 specifies Little Endian ordering. Big Endian mode can be specified for Direct Master accesses by asserting the BIGEND# input pin during Address phase of access. Yes Yes 0 2 Direct Slave Address Space 0 Big Endian Mode. Value of 1 specifies use of Big Endian data ordering for Direct Slave accesses to Local Address Space 0. Value of 0 specifies Little Endian ordering. Yes Yes 0 3 Direct Slave Address Expansion ROM 0 Big Endian Mode. Value of 1 specifies use of Big Endian data ordering for Direct Slave accesses to Expansion ROM. Value of 0 specifies Little Endian ordering. Yes Yes 0 4 Big Endian Byte Lane Mode. Value of 1 specifies that in Big Endian mode, use byte lanes [31:16] for a 16-bit Local Bus and byte lanes [31:24] for an 8-bit Local Bus. Value of 0 specifies that in Big Endian mode, byte lanes [15:0] be used for a 16-bit Local Bus and byte lanes [7:0] for an 8-bit Local Bus. Yes Yes 0 5 Direct Slave Address Space 1 Big Endian Mode. Value of 1 specifies use of Big Endian data ordering for Direct Slave accesses to Local Address Space 1. Value of 0 specifies Little Endian ordering. Yes Yes 0 6 DMA Channel 1 Big Endian Mode. Value of 1 specifies use of Big Endian data ordering for DMA Channel 1 accesses to the Local Address Space. Value of 0 specifies Little Endian ordering. Yes Yes 0 7 DMA Channel 0 Big Endian Mode. Value of 1 specifies use of Big Endian data ordering for DMA Channel 0 accesses to the Local Address Space. Value of 0 specifies Little Endian ordering. Yes Yes 0 Reserved. Yes No 0 31:8 68 Description PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers Local Configuration Registers Table 4-37. (EROMRR; PCI:10h, LOC:90h) Expansion ROM Range Register Read Write Value after Reset 10:0 Bit Reserved. Yes No 0 31:11 Specifies which PCI Address bits to use for decoding PCI-to-Local Bus Expansion ROM. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to Address bit 31. Write 1 to all bits to be included in decode and 0 to all others (used in conjunction with PCI Configuration register 30h). Default is 64 KB. Yes Yes FFFF00h Note: Description Range (not Range register) must be power of 2. "Range register value" is inverse of range. Table 4-38. (EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) Register and BREQo Control Bit Description Read Write Value after Reset 3:0 Direct Slave BREQo (Backoff Request Out) Delay Clocks. Number of Local Bus clocks in which Direct Slave HOLD request is pending and a Local Direct Master access is in progress and not being granted the bus (LHOLDA) before asserting BREQo. Once asserted, BREQo remains asserted until the PCI 9080 receives LHOLDA (LSB = 8 or 64 clocks). Yes Yes 0 4 Local Bus BREQo Enable. Value of 1 enables the PCI 9080 to assert BREQo output. Yes Yes 0 5 BREQo Timer-Resolution. Value of 1 changes LSB of the BREQo timer from 8 to 64 clocks. Yes Yes 0 10:6 Reserved. Yes No 0 31:11 Remap of PCI Expansion ROM Space into a Local Address Space. Remap (replace) PCI Address bits used in decode as Local Address bits. Yes Yes 0 Note: Remap Address value must be multiple of Range (not Range register). PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 69 Section 4 Registers Local Configuration Registers Table 4-39. (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor Register Bit Description Read Write Value after Reset 1:0 Memory Space 0 Local Bus Width. Value of 00 indicates bus width of 8 bits. Value of 01 indicates bus width of 16 bits. Value of 10 or 11 indicates bus width of 32 bits. Yes Yes S = 01 J = 11 C = 11 5:2 Memory Space 0 Internal Wait States (data to data; 0-15 wait states). Yes Yes 0 6 Memory Space 0 Ready Input Enable. Value of 1 enables Ready input. Value of 0 disables Ready input. Yes Yes 0 7 Memory Space 0 BTERM# Input Enable. Value of 1 enables BTERM# input. Value of 0 disables BTERM# input. If set to 0, the PCI 9080 bursts four Lword maximum at a time. Yes Yes 0 8 Memory Space 0 Prefetch Disable. If mapped into memory space, value of 0 enables Read prefetching. Value of 1 disables prefetching. If prefetching is disabled, the PCI 9080 disconnects after each memory read. Yes Yes 0 9 Expansion ROM Space Prefetch Disable. Value of 0 enables Read prefetching. Value of 1 disables prefetching. If prefetching is disabled, the PCI 9080 disconnects after each memory read. Yes Yes 0 10 Read Prefetch Count Enable. When set to 1 and memory prefetching is enabled, the PCI 9080 prefetches up to the number of Lwords specified in prefetch count. When set to 0, the PCI 9080 ignores the count and continues prefetching until terminated by PCI Bus. Yes Yes 0 Prefetch Counter. Number of Lwords to prefetch during Memory Read cycles (0-15). Count of zero selects prefetch of 16 Lwords. Yes Yes 0 Reserved. Yes No 0 17:16 Expansion ROM Space Local Bus Width. Value of 00 indicates bus width of 8 bits. Value of 01 indicates bus width of 16 bits. Value of 10 or 11 indicates bus width of 32 bits. Yes Yes S = 01 J = 11 C = 11 21:18 14:11 15 70 Expansion ROM Space Internal Wait States (data to data; 0-15 wait states). Yes Yes 0 22 Expansion ROM Space Ready Input Enable. Value of 1 enables Ready input. Value of 0 disables Ready input. Yes Yes 0 23 Expansion ROM Space Bterm Input Enable. Value of 1 enables BTERM# input. Value of 0 disables Bterm input. If set to 0, the PCI 9080 bursts four Lword maximum at a time. Yes Yes 0 24 Memory Space 0 Burst Enable. Value of 1 enables bursting. Value of 0 disables bursting. If burst is disabled, Local Bus performs continuous single cycles for Burst PCI Read/Write cycles. Yes Yes 0 25 Extra Long Load from Serial EEPROM. Value of 1 loads Subsystem ID and Local Address Space 1 registers. Value of 0 indicates not to load them. Yes No 0 26 Expansion ROM Space Burst Enable. Value of 1 enables bursting. Value of 0 disables bursting. If burst is disabled, Local Bus performs continuous single cycles for Burst PCI Read/Write cycles. Yes Yes 0 27 Direct Slave PCI Write Mode. Value of 0 indicates the PCI 9080 should disconnect when the Direct Slave Write FIFO is full. Value of 1 indicates the PCI 9080 should de-assert TRDY# when the Write FIFO is full. Yes Yes 0 31:28 PCI Target Retry Delay Clocks. Contains value (multiplied by 8) of the number of PCI Bus clocks after receiving PCI -to-Local Read or Write access and not successfully completing a transfer. Only pertains to Direct Slave Writes when bit 27 is set to 1. Yes Yes 4 (32 clocks) PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers Local Configuration Registers Table 4-40. (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register for Direct Master to PCI Read Write Value after Reset 15:0 Bit Reserved (64 KB increments). Yes No 0 31:16 Specifies which Local Address bits to use for decoding Local-to-PCI Bus access. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to Address bit 31. Write 1 to all bits that must be included in decode and 0 to all others. Used for Direct Master Memory, I/O, or Configuration accesses. Yes Yes 0 Note: Description Range (not Range register) must be power of 2. "Range register value" is inverse of range. Table 4-41. (DMLBAM; PCI:20h, LOC:A0h) Local Bus Base Address Register for Direct Master to PCI Memory Bit Description Read Write Value after Reset 15:0 Reserved. Yes No 0 31:16 Assigns value to bits to use for decoding Local-to-PCI Memory access. Yes Yes 0 Note: Local Base Address value must be multiple of Range (not Range register). Table 4-42. (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register for Direct Master to PCI IO/CFG Bit Description Read Write Value after Reset 15:0 Reserved. Yes No 0 31:16 Assigns value to bits to use for decoding Local-to-PCI I/O or Configuration access. Used for Direct Master I/O and Configuration accesses. Yes Yes 0 Notes: Local Base Address value must be multiple of Range (not Range register). Refer to DMPBAM[13] for I/O Remap Address option. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 71 Section 4 Registers Local Configuration Registers Table 4-43. (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master to PCI Memory Bit Read Write Value after Reset 0 Description Direct Master Memory Access Enable. Value of 1 enables decode of Direct Master Memory accesses. Value of 0 disables decode of Direct Master Memory accesses. Yes Yes 0 1 Direct Master I/O Access Enable. Value of 1 enables decode of Direct Master I/O accesses. Value of 0 disables decode of Direct Master I/O accesses. Yes Yes 0 2 LLOCK# Input Enable. Value of 1 enables LLOCK# input, enabling PCI-locked sequences. Value of 0 disables LLOCK# input. Yes Yes 0 Direct Master Read Prefetch Size control. Values: Yes Yes 00 Direct Master PCI Read Mode. Value of 0 indicates the PCI 9080 should release PCI Bus when the Read FIFO becomes full. Value of 1 indicates the PCI 9080 should keep PCI Bus and de-assert IRDY when the Read FIFO becomes full. Yes Yes 0 10, 8:5 Programmable Almost Full Flag. When the number of entries in the 32-word Direct Master Write FIFO exceeds this value, output pin DMPAF# is asserted low. Yes Yes 000 9 Write and Invalidate Mode. When set to 1, the PCI 9080 waits for 8 or 16 Lwords to be written from the Local Bus before starting PCI access. When set, all Local Direct Master to PCI Write accesses must be 8- or 16-Lword bursts. Yes Yes 0 12, 3 00 = The PCI 9080 continues to prefetch Read data from the PCI Bus until the Direct Master access is finished. May result in additional four unneeded Lwords being prefetched from the PCI Bus. 01 = Prefetch up to four Lwords from the PCI Bus 10 = Prefetch up to eight Lwords from the PCI Bus 11 = Prefetch up to 16 Lwords from the PCI Bus If PCI memory prefetch is not wanted, performs Direct Master Single cycle. Direct Master Burst reads must not exceed programmed limit. 4 Use in conjunction with PCICR[4] and Section 3.6.1.9.2, "Direct Master Write and Invalidate"). 11 Direct Master Prefetch Limit. If set to 1, don't prefetch past 4 KB (4098 bytes) boundaries. Yes Yes 0 13 I/O Remap Select. When set to 1, forces PCI Address bits [31:16] to all zeros. When set to 0, uses bits [31:16] of this register as PCI Address bits [31:16]. Yes Yes 0 Direct Master Write Delay. Used to delay PCI Bus request after Direct Master Burst Write cycle has started. Values: Yes Yes 00 Yes Yes 0 15:14 00 = No delay; start cycle immediately 01 = Delay 4 PCI clocks 10 = Delay 8 PCI clocks 11 = Delay 16 PCI clocks 31:16 Note: 72 Remap of Local-to-PCI Space into PCI Address Space. Remap (replace) Local Address bits used in decode as PCI Address bits. Used for Direct Master Memory and I/O accesses. Remap Address value must be multiple of Range (not Range register). PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers Local Configuration Registers Table 4-44. (DMCFGA; PCI:2Ch, LOC:ACh) PCI Configuration Address Register for Direct Master to PCI IO/CFG Bit Description Read Write Value after Reset 1:0 Configuration Type (00=Type 0, 01=Type 1). Yes Yes 0 7:2 Register Number. If different register Read/Write is needed, value must be programmed and new PCI Configuration cycle must be generated. Yes Yes 0 10:8 Function Number. Yes Yes 0 15:11 Device Number. Yes Yes 0 23:16 Bus Number. Yes Yes 0 30:24 31 Reserved. Yes No 0 Configuration Enable. Value of 1 allows Local-to-PCI I/O accesses to be converted to a PCI Configuration cycle. Parameters in this table are used to generate PCI configuration address. Yes Yes 0 Note: Refer to Configuration Cycle Generation example in Section 3.6.1.6, "CFG (PCI Configuration Type 0 or Type 1 Cycles)." Table 4-45. (LAS1RR; PCI:F0h, LOC:170h) Local Address Space 1 Range Register for PCI-to-Local Bus Bit 0 2:1 Description Read Write Value after Reset Memory Space Indicator. Value of 0 indicates Local Address Space 1 maps into PCI memory space. Value of 1 indicates Address Space 1 maps into PCI I/O space. Yes Yes 0 If mapped into memory space, encoding is as follows: Yes Yes 0 2/1 Meaning 00 01 10 11 Locate anywhere in 32-bit PCI Address space Locate below 1 MB in PCI Address space Locate anywhere in 64-bit PCI Address space Reserved If mapped into I/O space, bit 1 must be set to 0. Bit 2 is included with bits [31:3] to indicate decoding range. 3 If mapped into memory space, value of 1 indicates reads are prefetchable (does not affect operation of the PCI 9080, but is used for system status). If mapped into I/O space, bit is included with bits [31:2] to indicate decoding range. Yes Yes 0 31:4 Specifies which PCI Address bits to use for decoding PCI access to Local Bus Space 1. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to Address bit 31. Write 1 to all bits that must be included in decode and 0 to all others (used in conjunction with PCI Configuration Register Ch 1). Default is 1 MB. Yes Yes FFF0000h Notes: Range (not Range register) must be power of 2. "Range register value" is inverse of range. User should limit all I/O spaces to 256 bytes per PCI Specification v2.1. If the QSR bit 0 is set, defines PCI Base Address 0. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 73 Section 4 Registers Local Configuration Registers Table 4-46. (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap) Register Bit Description 0 Space 1 Enable. Value of 1 enables decoding of PCI Addresses for Direct Slave access to Local Space 1. Value of 0 disables decoding. If set to 0, PCI BIOS may not allocate (assign) base address for Space 1. Note: 1 Read Write Value after Reset Yes Yes 0 Must be set to 1 for any Direct Slave access to Space 1. Reserved. Yes No 0 3:2 If Local Space 1 is mapped into memory space, bits are not used. If mapped into I/O space, bit is included with bits [31:4] for remapping. Yes Yes 0 31:4 Remap of PCI Address to Local Address Space 1 into a Local Address Space. Remap (replace) PCI Address bits used in decode as Local Address bits. Yes Yes 0 Note: Remap Address value must be multiple of Range (not Range register). Table 4-47. (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor Register 74 Bit Description 1:0 Memory Space 1 Local Bus Width. Value of 00 indicates bus width of 8 bits. Value of 01 indicates bus width of 16 bits. Value of 10 or 11 indicates bus width of 32 bits. 5:2 Read Write Value after Reset Yes Yes S = 01 J = 11 C = 11 Memory Space 1 Internal Wait States (data to data; 0-15 wait states). Yes Yes 0 6 Memory Space 1 Ready Input Enable. Value of 1 enables Ready input. Value of 0 disables Ready input. Yes Yes 0 7 Memory Space 1 BTERM# Input Enable. Value of 1 enables BTERM# input. Value of 0 disables BTERM# input. If set to 0, the PCI 9080 bursts four Lword maximum at a time. Yes Yes 0 8 Memory Space 1 Burst Enable. Value of 1 enables bursting. Value of 0 disables bursting. If burst is disabled, Local Bus performs continuous single cycles for Burst PCI Read/Write cycles. Yes Yes 0 9 Memory Space 1 Prefetch Disable. If mapped into memory space, value of 0 enables Read prefetching. Value of 1 disables prefetching. If prefetching is disabled, the PCI 9080 disconnects after each memory read. Yes Yes 0 10 Read Prefetch Count Enable. When set to 1 and memory prefetching is enabled, the PCI 9080 prefetches up to the number of Lwords specified in prefetch count. When set to 0, the PCI 9080 ignores the count and continues prefetching until terminated by PCI Bus. Yes Yes 0 14:11 Prefetch Counter. Number of Lwords to prefetch during memory Read cycles (0-15). Yes Yes 0 31:15 Reserved. Yes No 0 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers Runtime Registers 4.5 Runtime Registers Table 4-48. (MBOX0; PCI:40h or 78h, LOC:C0h) Mailbox Register 0 Bit 31:0 Description 32-Bit Mailbox Register. Read Write Value after Reset Yes Yes 0 Note: Mailbox register 0 is replaced by the Inbound Queue Port when the I2O feature is enabled (QSR[0] is set). Mailbox register 0 is always accessible at PCI Address 78h and Local Address C0h. Table 4-49. (MBOX1; PCI:44h or 7Ch, LOC:C4h) Mailbox Register 1 Bit 31:0 Description 32-Bit Mailbox Register. Read Write Value after Reset Yes Yes 0 Note: Mailbox register 1 is replaced by Outbound Queue Port when I2O feature is enabled (QSR[0] is set). Mailbox register 1 is always accessible at PCI Address 7Ch and Local Address C4h. Table 4-50. (MBOX2; PCI:48h, LOC:C8h) Mailbox Register 2 Bit 31:0 Description 32-Bit Mailbox Register. Read Write Value after Reset Yes Yes 0 Read Write Value after Reset Yes Yes 0 Read Write Value after Reset Yes Yes 0 Read Write Value after Reset Yes Yes 0 Read Write Value after Reset Yes Yes 0 Read Write Value after Reset Yes Yes 0 Table 4-51. (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 3 Bit 31:0 Description 32-Bit Mailbox Register. Table 4-52. (MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4 Bit 31:0 Description 32-Bit Mailbox Register. Table 4-53. (MBOX5; PCI:54h, LOC:D4h) Mailbox Register 5 Bit 31:0 Description 32-Bit Mailbox Register. Table 4-54. (MBOX6; PCI:58h, LOC:D8h) Mailbox Register 6 Bit 31:0 Description 32-Bit Mailbox Register. Table 4-55. (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 7 Bit 31:0 Description 32-Bit Mailbox Register. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 75 Section 4 Registers Runtime Registers Table 4-56. (P2LDBELL; PCI:60h, LOC:E0h) PCI-to-Local Doorbell Register Bit 31:0 Description Doorbell Register. PCI Master can write to this register and generate a Local interrupt to the Local processor. The Local processor can then read this register to determine which Doorbell bit was asserted. PCI Master sets doorbell by writing 1 to a particular bit. Local processor can clear Doorbell bit by writing 1 to that bit position. Read Write Value after Reset Yes Yes/Clr 0 Read Write Value after Reset Yes Yes/Clr 0 Table 4-57. (L2PDBELL; PCI:64h, LOC:E4h) Local-to-PCI Doorbell Register Bit 31:0 76 Description Doorbell Register. Local processor can write to this register and generate PCI interrupt. PCI Master can then read this register to determine which Doorbell bit was asserted. Local processor sets doorbell by writing 1 to a particular bit. PCI Master can clear Doorbell bit by writing 1 to that bit position. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers Runtime Registers Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register Bit Read Write Value after Reset 0 Description Enable Local Bus LSERR#. Value of 1 enables the PCI 9080 to assert LSERR# interrupt output when PCI Bus Target Abort or Master Abort Status bit is set in PCI Status Configuration register. Yes Yes 0 1 Enable Local Bus LSERR# when PCI parity error occurs during a PCI 9080 Master Transfer or a PCI 9080 Slave access or an Outbound Free List FIFO Overflow Init. Yes Yes 0 2 Generate PCI Bus SERR#. When set to 0, writing 1 generates PCI Bus SERR#. Yes Yes 0 3 Mailbox Interrupt Enable. Value of 1 enables a Local interrupt to be generated when PCI Bus writes to Mailbox registers 0 through 3. To clear a Local interrupt, the Local Master must read the Mailbox. Used in conjunction with Local interrupt enable. Yes Yes 0 7:4 Reserved. Yes No 0 8 PCI Interrupt Enable. Value of 1 enables PCI interrupts. Yes Yes 1 9 PCI Doorbell Interrupt Enable. Value of 1 enables doorbell interrupts. Used in conjunction with PCI interrupt enable. Clearing doorbell interrupt bits that caused interrupt also clears interrupt. Yes Yes 0 10 PCI Abort Interrupt Enable. Value of 1 enables Master abort or Master detect of Target abort to generate PCI interrupt. Used in conjunction with PCI interrupt enable. Clearing abort status bits also clears PCI interrupt. Yes Yes 0 11 PCI Local Interrupt Enable. Value of 1 enables Local interrupt input to generate a PCI interrupt. Use in conjunction with PCI interrupt enable. Clearing the Local Bus cause of interrupt also clears interrupt. Yes Yes 0 12 Retry Abort Enable. Value of 1 enables the PCI 9080 to treat 256 Master consecutive retries to a Target as a Target Abort. Value of 0 enables the PCI 9080 to attempt Master Retries indefinitely. Yes Yes 0 13 Value of 1 indicates PCI doorbell interrupt is active. Yes No 0 14 Value of 1 indicates PCI abort interrupt is active. Yes No 0 15 Value of 1 indicates Local interrupt is active (LINTi#). Yes No 0 Note: For diagnostic purposes only. 16 Local Interrupt Output Enable. Value of 1 enables Local interrupt output. Yes Yes 1 17 Local Doorbell Interrupt Enable. Value of 1 enables doorbell interrupts. Used in conjunction with Local interrupt enable. Clearing local doorbell interrupt bits that caused interrupt also clears interrupt. Yes Yes 0 18 Local DMA Channel 0 Interrupt Enable. Value of 1 enables DMA Channel 0 interrupts. Used in conjunction with Local interrupt enable. Clearing DMA status bits also clears interrupt. Yes Yes 0 19 Local DMA Channel 1 Interrupt Enable. Value of 1 enables DMA Channel 1 interrupts. Used in conjunction with Local interrupt enable. Clearing DMA status bits also clears interrupt. Yes Yes 0 20 Value of 1 indicates local doorbell interrupt is active. Yes No 0 21 Value of 1 indicates DMA Ch 0 interrupt is active. Yes No 0 22 Value of 1 indicates DMA Ch 1 interrupt is active. Yes No 0 23 Value of 1 indicates BIST interrupt is active. Writing 1 to bit 6 of PCI Configuration BIST Register generates BIST (Built-In Self-Test) interrupt. Clearing bit 6 clears interrupt. For description of self-test, refer to PCI BISTR. Yes No 0 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 77 Section 4 Registers Runtime Registers Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register (continued) 78 Bit Description Read Write Value after Reset 24 Value of 0 indicates Direct Master was Bus Master during a Master or Target abort. (Not valid until abort occurs.) Yes No 1 25 Value of 0 indicates DMA CH 0 was Bus Master during a Master or Target abort. (Not valid until abort occurs.) Yes No 1 26 Value of 0 indicates DMA CH 1 was Bus Master during a Master or Target abort. (Not valid until abort occurs.) Yes No 1 27 Value of 0 indicates Target Abort was generated by the PCI 9080 after 256 consecutive Master retries to Target. (Not valid until abort occurs.) Yes No 1 28 Value of 1 indicates PCI wrote data to MailBox #0. Enabled only if MBOXINTENB is enabled (bit 3 high). Yes No 0 29 Value of 1 indicates PCI wrote data to MailBox #1. Enabled only if MBOXINTENB is enabled (bit 3 high). Yes No 0 30 Value of 1 indicates PCI wrote data to MailBox #2. Enabled only if MBOXINTENB is enabled (bit 3 high). Yes No 0 31 Value of 1 indicates PCI wrote data to MailBox #3. Enabled only if MBOXINTENB is enabled (bit 3 high). Yes No 0 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers Runtime Registers Table 4-59. (CNTRL; PCI:6Ch, LOC:ECh) Serial EEPROM Control, PCI Command Codes, User I/O Control, Init Control Register Bit Description 3:0 PCI Read Command Code for DMA. Sent out during DMA Read cycles. Read Write Value after Reset Yes Yes 1110 7:4 PCI Write Command Code for DMA. Sent out during DMA Write cycles. Yes Yes 0111 11:8 PCI Memory Read Command Code for Direct Master. Sent out during Direct Master Read cycles. Yes Yes 0110 15:12 PCI Memory Write Command Code for Direct Master. Sent out during Direct Master Write cycles. Yes Yes 0111 16 General Purpose Output. Value of 1 causes USERO output to go high. Value of 0 causes USER0 output to go low. Yes Yes 1 17 General Purpose Input. Value of 1 indicates USERI input pin is high. Value of 0 indicates USERI pin is low. Yes No -- Reserved. Yes No 0 24 Serial EEPROM Clock for Local or PCI Bus Reads or Writes to Serial EEPROM. Toggling this bit generates serial EEPROM clock. (Refer to manufacturer's data sheet for particular serial EEPROM being used.) Yes Yes 0 25 Serial EEPROM Chip Select. For Local or PCI Bus Reads or Writes to serial EEPROM, setting this bit to 1 provides serial EEPROM chip select. Yes Yes 0 26 Write Bit to serial EEPROM. For Writes, this output bit is input to serial EEPROM. Clocked into serial EEPROM by serial EEPROM clock. Yes Yes 0 27 Read Serial EEPROM Data. For Reads, this input bit is output of serial EEPROM. Clocked out of serial EEPROM by serial EEPROM clock. Yes No -- 28 Serial EEPROM Present. Value of 1 indicates serial EEPROM is present. Yes No 0 29 Reload Configuration Registers. When set to 0, writing 1 causes the PCI 9080 to reload Local Configuration registers from serial EEPROM. Yes Yes 0 30 PCI Adapter Software Reset. Value of 1 holds Local Bus logic in the PCI 9080 reset and LRESETo# asserted. Contents of PCI Configuration registers and Shared Run Time registers are not reset. Software Reset can only be cleared from the PCI Bus. (Local Bus remains reset until this bit is cleared.) Yes Yes 0 31 Local Init Status. Value of 1 indicates Local Init done. Responses to PCI accesses are Retrys until this bit is set. While input pin NB# is asserted low, this bit is forced to 1. Yes Yes 0 Read Write Value after Reset Yes No 10B5h Yes No 9080h Read Write Value after Reset Yes No Current Rev # 23:18 Table 4-60. (PCIHIDR; PCI:70h, LOC:F0h) PCI Permanent Configuration ID Register Bit Description 15:0 Permanent Vendor ID. Identifies device manufacturer. 31:16 Permanent Device ID. Identifies particular device. Note: Note: Hardcoded to PCI SIG issued vendor ID of PLX (10B5h). Hardcoded to PLX part number for PCI interface chip PCI 9080. Table 4-61. (PCIHREV; PCI:74h, LOC:F4h) PCI Permanent Revision ID Register Bit Description 7:0 Permanent Revision ID. Note: Hardcoded to silicon revision of the PCI 9080. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 79 Section 4 Registers DMA Registers 4.6 DMA Registers Table 4-62. (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode Register Bit Description Read Write Value after Reset 1:0 Local Bus Width. Value of 00 indicates bus width of 8 bits. Value of 01 indicates bus width of 16 bits. Value of 10 or 11 indicates bus width of 32 bits. Yes Yes S = 01 J = 11 C = 11 5:2 Internal Wait States (data to data). Yes Yes 0 6 Ready Input Enable. Value of 1 enables Ready input. Value of 0 disables Ready input. Yes Yes 0 7 BTERM# Input Enable. Value of 1 enables BTERM# input. Value of 0 disables BTERM# input. If set to 0, the PCI 9080 bursts four Lword maximum at a time. Yes Yes 0 8 Local Burst Enable. Value of 1 enables bursting. Value of 0 disables local bursting. If burst is disabled, Local Bus performs continuous single cycles for Burst PCI Read/Write cycles. Yes Yes 0 9 Chaining. Value of 1 indicates Chaining mode is enabled. For Chaining mode, DMA source address, destination address and byte count are loaded from memory in PCI or Local Address Spaces. Value of 0 indicates Non-chaining mode is enabled. Yes Yes 0 10 Done Interrupt Enable. Value of 1 enables interrupt when done. Value of 0 disables interrupt when done. If DMA Clear Count mode is enabled, interrupt does not occur until byte count is cleared. Yes Yes 0 11 Local Addressing Mode. Value of 1 indicates Local Address LA[31:2] to be held constant. Value of 0 indicates Local Address is incremented. Yes Yes 0 12 Demand Mode. Value of 1 causes DMA controller to operate in Demand mode. In Demand mode, DMA controller transfers data when its DREQ[1:0]# input is asserted. Asserts DACK[1:0]# to indicate current Local Bus transfer is in response to DREQ[1:0]# input. DMA controller transfers Lwords (32 bits) of data. May result in multiple transfers for 8- or 16-bit bus. Yes Yes 0 13 Write and Invalidate Mode for DMA Transfers. When set to 1, the PCI 9080 performs Write and Invalidate cycles to PCI Bus. The PCI 9080 supports Write and Invalidate sizes of 8 or 16 Lwords. Size specified in PCI Cache Line Size Register. If size other than 8 or 16 is specified, the PCI 9080 performs Write transfers rather than Write and Invalidate transfers. Transfers must start and end at Cache Line boundaries. Yes Yes 0 14 DMA EOT (End of Transfer) Enable. Value of 1 enables EOT[1:0]# input pin. Value of 0 disables EOT[1:0]# input pin. (Refer to Section 3.7.6.1, "End of Transfer (EOT0# or EOT1#) Input.") Yes Yes 0 15 DMA Stop Data Transfer Mode. Value of 0 sends BLAST to terminate DMA transfer. Value of 1 indicates EOT asserted or DREQ[1:0]# de-asserted during Demand mode DMA terminates a DMA transfer. (Refer to Section 3.7.6.1, "End of Transfer (EOT0# or EOT1#) Input.") Yes Yes 0 16 DMA Clear Count Mode. When set to 1, if it is in Local memory, byte count in each chaining descriptor is cleared when corresponding DMA transfer completes. Yes Yes 0 17 DMA Channel 0 Interrupt Select. Value of 1 routes DMA Channel 0 interrupt to PCI interrupt. Value of 0 routes DMA Channel 0 interrupt to Local Bus interrupt. Yes Yes 0 Reserved. Yes No 0 Note: 31:18 80 If the chaining descriptor is in PCI memory, the count is not cleared. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers DMA Registers Table 4-63. (DMAPADR0; PCI:84h, LOC:104h) DMA Channel 0 PCI Address Register Bit 31:0 Description PCI Address Register. Indicates from where in PCI memory space the DMA transfers (reads or writes) start. Read Write Value after Reset Yes Yes 0 Read Write Value after Reset Yes Yes 0 Table 4-64. (DMALADR0; PCI:88h, LOC:108h) DMA Channel 0 Local Address Register Bit 31:0 Description Local Address Register. Indicates from where in Local memory space the DMA transfers (reads or writes) start. Table 4-65. (DMASIZ0; PCI:8Ch, LOC:10Ch) DMA Channel 0 Transfer Size (Bytes) Register Read Write Value after Reset 22:0 Bit Description DMA Transfer Size (Bytes). Indicates number of bytes to transfer during DMA operation. Yes Yes 0 31:23 Reserved. Yes No 0 Read Write Value after Reset Table 4-66. (DMADPR0; PCI:90h, LOC:110h) DMA Channel 0 Descriptor Pointer Register Bit Description 0 Descriptor Location. Value of 1 indicates PCI Address space. Value of 0 indicates Local Address Space. Yes Yes 0 1 End of Chain. Value of 1 indicates end of chain. Value of 0 indicates not end of chain descriptor. (Same as Non-chaining Mode.) Yes Yes 0 2 Interrupt after Terminal Count. Value of 1 causes interrupt to be generated after terminal count for this descriptor is reached. Value of 0 disables interrupts from being generated. Yes Yes 0 3 Direction of Transfer. Value of 1 indicates transfers from the Local Bus to PCI Bus. Value of 0 indicates transfers from the PCI Bus to Local Bus. Yes Yes 0 Next Descriptor Address. Quad word aligned (bits [3:0] = 0000). Yes Yes 0 31:4 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 81 Section 4 Registers DMA Registers Table 4-67. (DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode Register Bit Description Read Write Value after Reset 1:0 Local Bus Width. Value of 00 indicates bus width of 8 bits. Value of 01 indicates bus width of 16 bits. Value of 10 or 11 indicates bus width of 32 bits. Yes Yes S = 01 J = 11 C = 11 5:2 Internal Wait States (data to data). Yes Yes 0 6 Ready Input Enable. Value of 1 enables Ready input. Value of 0 disables Ready input. Yes Yes 0 7 BTERM# Input Enable. Value of 1 enables BTERM# input. Value of 0 disables BTERM# input. If set to 0, the PCI 9080 bursts four Lword maximum at a time. Yes Yes 0 8 Local Burst Enable. Value of 1 enables bursting. Value of 0 disables local bursting. If burst is disabled, Local Bus performs continuous single cycles for Burst PCI Read/Write cycles. Yes Yes 0 9 Chaining. Value of 1 indicates Chaining mode enabled. For Chaining mode, DMA source address, destination address and byte count are loaded from memory in PCI or Local address spaces. Value of 0 indicates Non-chaining mode enabled. Yes Yes 0 10 Done Interrupt Enable. Value of 1 enables interrupt when done. Value of 0 disables interrupt when done. If DMA Clear Count mode is enabled, interrupt does not occur until byte count is cleared. Yes Yes 0 11 Local Addressing Mode. Value of 1 indicates Local Address LA[31:2] to be held constant. Value of 0 indicates Local Address is incremented. Yes Yes 0 12 Demand Mode. Value of 1 causes DMA controller to operate in Demand mode. In Demand mode, DMA controller transfers data when its DREQ[1:0]# input is asserted. Asserts DACK[1:0]# to indicate current Local Bus transfer is in response to DREQ[1:0]# input. DMA controller transfers Lwords (32 bits) of data. May result in multiple transfers for 8- or 16-bit bus. Yes Yes 0 13 Write and Invalidate Mode for DMA Transfers. When set to 1, the PCI 9080 performs Write and Invalidate cycles to PCI Bus. The PCI 9080 supports Write and Invalidate sizes of 8 or 16 Lwords. Size is specified in PCI Cache Line Size Register. If size other than 8 or 16 is specified, the PCI 9080 performs Write transfers rather than Write and Invalidate transfers. Transfers must start and end at Cache Line boundaries. Yes Yes 0 14 DMA EOT (End of Transfer) Enable. Value of 1 enables EOT[1:0]# input pin. Value of 0 disables EOT[1:0]# input pin. (Refer to Section 3.7.6.1, "End of Transfer (EOT0# or EOT1#) Input.") Yes Yes 0 15 DMA Stop Data Transfer Mode. Value of 0 BLAST terminates DMA transfer. Value of 1 indicates EOT. In demand DMA mode, if set to 1, assertion of EOT causes DMA controller to terminate following current Data phase (blast may or may not be asserted). If not set, and EOT asserted, DMA controller completes current Data phase and potentially a following Data phase in which blast is asserted. (Refer to Section 3.7.6.1, "End of Transfer (EOT0# or EOT1#) Input.") Yes Yes 0 16 DMA Clear Count Mode. When set to 1, byte count in each chaining descriptor, if it is in Local memory, is cleared when corresponding DMA transfer completes. Yes Yes 0 DMA Channel 1 Interrupt Select. Value of 1 routes DMA Channel 1 interrupt to PCI interrupt. Value of 0 routes DMA Channel 1 interrupt to Local Bus interrupt. Yes Yes 0 Reserved. Yes No 0 Note: 17 31:18 82 If a chaining descriptor is in PCI memory, the count is not cleared. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers DMA Registers Table 4-68. (DMAPADR1; PCI:98h, LOC:118h) DMA Channel 1 PCI Address Register Bit 31:0 Description PCI Data Address Register. Indicates from where in PCI memory space the DMA transfers (reads or writes) start. Read Write Value after Reset Yes Yes 0 Read Write Value after Reset Yes Yes 0 Table 4-69. (DMALADR1; PCI:9Ch, LOC:11Ch) DMA Channel 1 Local Address Register Bit 31:0 Description Local Data Address Register. Indicates from where in Local memory space the DMA transfers (reads or writes) start. Table 4-70. (DMASIZ1; PCI:A0h, LOC:120h) DMA Channel 1 Transfer Size (Bytes) Register Read Write Value after Reset 22:0 Bit Description DMA Transfer Size (Bytes). Indicates number of bytes to transfer during DMA operation. Yes Yes 0 31:23 Reserved. Yes No 0 Read Write Value after Reset Table 4-71. (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer Register Bit Description 0 Descriptor Location. Value of 1 indicates PCI Address space. Value of 0 indicates Local Address Space. Yes Yes 0 1 End of Chain. Value of 1 indicates end of chain. Value of 0 indicates not end of chain descriptor. (Same as Non-chaining mode.) Yes Yes 0 2 Interrupt after Terminal Count. Value of 1 causes interrupt to be generated after terminal count for this descriptor is reached. Value of 0 disables interrupts from being generated. Yes Yes 0 3 Direction of Transfer. Value of 1 indicates transfers from the Local Bus to PCI Bus. Value of 0 indicates transfers from the PCI Bus to Local Bus. Yes Yes 0 Next Descriptor Address. Quad word aligned (bits [3:0] = 0000). Yes Yes 0 Read Write Value after Reset 31:4 Table 4-72. (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Register Bit Description 0 Channel 0 Enable. Value of 1 enables channel to transfer data. Value of 0 disables channel from starting DMA transfer and if in process of transferring data suspend transfer (pause). Yes Yes 0 1 Channel 0 Start. Value of 1 causes channel to start transferring data if channel is enabled. No Yes/Set 0 2 Channel 0 Abort. Value of 1 causes channel to abort current transfer. Channel Enable bit must be cleared. Channel Complete bit is set when abort is complete. No Yes/Set 0 3 Clear Interrupt. Writing 1 to this bit clears Channel 0 interrupts. No Yes/Clr 0 4 Channel 0 Done. Value of 1 indicates channel's transfer is complete. Value of 0 indicates channel's transfer is not complete. Yes No 1 Reserved. Yes No 0 7:5 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 83 Section 4 Registers DMA Registers Table 4-73. (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Register Bit Read Write Value after Reset 0 Channel 1 Enable. Value of 1 enables channel to transfer data. Value of 0 disables channel from starting DMA transfer and if in process of transferring data suspend transfer (Pause). Yes Yes 0 1 Channel 1 Start. Value of 1 causes channel to start transferring data if channel is enabled. No Yes/Set 0 2 Channel 1 Abort. Value of 1 causes channel to abort current transfer. Channel Enable bit must be cleared. Channel Complete bit set when abort is complete. No Yes/Set 0 3 Clear Interrupt. Writing 1 to this bit clears Channel 1 interrupts. No Yes/Clr 0 4 Channel 1 Done. Value of 1 indicates this channel's transfer is complete. Value of 0 indicates channel's transfer is not complete. Yes No 1 Reserved. Yes No 0 Read Write Value after Reset Yes Yes 0 Yes Yes 0 7:5 Description Table 4-74. (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration Register Same as Mode/Arbitration register (MARBR). Table 4-75. (DMATHR; PCI:B0h, LOC:130h) DMA Threshold Register Bit Description 3:0 DMA Channel 0 PCI-to-Local Almost Full (C0PLAF). Number of full entries (divided by two, minus one) in the FIFO before requesting Local Bus for writes. 7:4 DMA Channel 0 Local-to-PCI Almost Empty (C0LPAE). Number of empty entries (divided by two, minus one) in the FIFO before requesting Local Bus for reads. (C0PLAF+1) + (C0PLAE+1) should be FIFO Depth of 32. (C0LPAF+1) + (C0LPAE+1) should be FIFO depth of 32. 11:8 DMA Channel 0 Local-to-PCI Almost Full (C0LPAF). Number of full entries (divided by two, minus one) in the FIFO before requesting PCI Bus for writes. Yes Yes 0 15:12 DMA Channel 0 PCI-to-Local Almost Empty (C0PLAE). Number of empty entries (divided by two, minus one) in the FIFO before requesting PCI Bus for reads. Yes Yes 0 19:16 DMA Channel 1 PCI-to-Local Almost Full (C1PLAF). Number of full entries (minus one) in the FIFO before requesting Local Bus for writes. Yes Yes 0 Yes Yes 0 (C1PLAF+1) + (C1PLAE+1) should be FIFO depth of 16. 23:20 DMA Channel 1 Local-to-PCI Almost Empty (C1LPAE). Number of empty entries (minus one) in the FIFO before requesting Local Bus for reads. (C1PLAF) + (C1PLAE) should be FIFO depth of 16. 27:24 DMA Channel 1 Local-to-PCI Almost Full (C1LPAF). Number of full entries (minus one) in the FIFO before requesting PCI Bus for writes. Yes Yes 0 31:28 DMA Channel 1 PCI-to-Local Almost Empty (C1PLAE). Number of empty entries (minus one) in the FIFO before requesting PCI Bus for reads. Yes Yes 0 Note: If the number of entries needed is x, then the value is one less than half the number of entries (DMA Channel 0 only). 84 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers Messaging Queue Registers 4.7 Messaging Queue Registers Table 4-76. (OPLFIS; PCI:30h, LOC:B0) Outbound Post List FIFO Interrupt Status Register Bit Description Read Write Value after Reset 2:0 Reserved. Yes No 0 Outbound Post List FIFO Interrupt. Set when the Outbound Post List FIFO is not empty. Not affected by the Interrupt Mask bit. Yes No 0 Reserved. Yes No 0 Read Write Value after Reset Yes No 0 Outbound Post List FIFO Interrupt Mask. Interrupt is masked when set. Yes Yes 1 Reserved. Yes No 0 Read Write Value after Reset PCI PCI 0 Read Write Value after Reset PCI PCI 0 3 31:4 Table 4-77. (OPLFIM; PCI:34h, LOC:B4) Outbound Post List FIFO Interrupt Mask Register Bit Description 2:0 Reserved. 3 31:4 Table 4-78. (IQP; PCI:40h) Inbound Queue Port Register Bit 31:0 Description Value written by the PCI Master is stored into the Inbound Post List FIFO, which is located in Local memory at an address pointed to by Queue Base Address + FIFO Size + Inbound Post Head Pointer. From the time of a PCI write until a Local Memory write and update of the Inbound Post Queue Head Pointer, further accesses to this register result in a Retry. A Local interrupt is generated when the Inbound Post List FIFO is not empty. When the port is read by a PCI Master, the value is read from the Inbound Free List FIFO, which is located in Local memory at an address pointed to by Queue Base Address + Inbound Free Tail Pointer. If the FIFO is empty, a value of FFFFFFFh is returned. Table 4-79. (OQP; PCI:44h) Outbound Queue Port Register Bit 31:0 Description Value written by the PCI Master is stored into the Outbound Free List FIFO, which is located in Local memory at an address pointed to by Queue Base Address + (3*FIFO Size) + Outbound Free Head Pointer. From the time of the PCI write until the Local Memory write and update of the Outbound Free Head Pointer, further accesses to this register result in a Retry. If the FIFO fills up, a local LSERR interrupt is generated. When the port is read by a PCI Master, the value is read from the Outbound Post List FIFO, which is located in Local memory at an address pointed to by Queue Base Address + (2*FIFO Size) + Outbound Post Tail Pointer. If the FIFO is empty, a value of FFFFFFFh is returned. A PCI interrupt is generated if the Outbound Post List FIFO is not empty. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 85 Section 4 Registers Messaging Queue Registers Table 4-80. (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration Register Bit 0 5:1 31:6 Description Read Write Value after Reset Queue Enable. Value of 1 allows accesses to the Inbound and Outbound Queue Ports. If cleared to 0, writes are accepted but ignored, and reads return FFFFFFFF. Complete all pointer initializations and frame allocations before enabling this bit. Yes Yes 0 Circular FIFO Size. Defines size of one of the circular FIFOs. Each of the four FIFOs are the same size. Each FIFO entry is one 32-bit word. Yes Yes 00001 Yes No 0 Read Write Value after Reset FIFO Size Encoding Max entries 5:1 per FIFO FIFO Size Total FIFO Memory 00001 00010 00100 01000 10000 16 KB 32 KB 64 KB 128 KB 256 KB 64 KB 128 KB 256 KB 512 KB 1 MB 4K entries 8K entries 16K entries 32K entries 64K entries Reserved. Table 4-81. (QBAR; PCI:C4h, LOC:144h) Queue Base Address Register Bit Description 19:0 Reserved. Yes No 0 31:20 Queue Base Address. Local memory base address of Inbound and Outbound Queues (four contiguous and equal size FIFOs). Queue base address must be aligned on 1 MB boundary. Yes Yes 0 Read Write Value after Reset Table 4-82. (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer Register Bit Description 1:0 Reserved. Yes No 0 19:2 Inbound Free Head Pointer. Local Memory Offset for the Inbound Free List FIFO. Initialized as (0*FIFO Size) and maintained by local CPU software. Yes Yes 0 31:20 Queue Base Address. Yes No 0 Read Write Value after Reset Table 4-83. (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer Register 86 Bit Description 1:0 Reserved. Yes No 0 19:2 Inbound Free Tail Pointer. Local Memory Offset for the Inbound Free List FIFO. Initialized as (0*FIFO Size) by local CPU software. Maintained by MU hardware and incremented modulo the FIFO size. Yes Yes 0 31:20 Queue Base Address. Yes No 0 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 4 Registers Messaging Queue Registers Table 4-84. (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer Register Bit Description Read Write Value after Reset 1:0 Reserved. Yes No 0 19:2 Inbound Post Head Pointer. Local Memory Offset for the Inbound Post List FIFO. Initialized as (1*FIFO Size) by local CPU software. Maintained by MU hardware and incremented modulo the FIFO size. Yes Yes 0 31:20 Queue Base Address. Yes No 0 Table 4-85. (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer Register Bit Description Read Write Value after Reset 1:0 Reserved. Yes No 0 19:2 Inbound Post Tail Pointer. Local Memory Offset for the Inbound Post List FIFO. Initialized as (1*FIFO Size) and maintained by local CPU software. Yes Yes 0 31:20 Queue Base Address. Yes No 0 Table 4-86. (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer Register Bit Description Read Write Value after Reset 1:0 Reserved. Yes No 0 19:2 Outbound Free Head Pointer. Local Memory Offset for the Outbound Free List FIFO. Initialized as (3*FIFO Size) by local CPU software. Maintained by MU hardware and incremented modulo the FIFO size. Yes Yes 0 31:20 Queue Base Address. Yes No 0 Read Write Value after Reset Table 4-87. (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer Register Bit Description 1:0 Reserved. Yes No 0 19:2 Outbound Free Tail Pointer. Local Memory Offset for the Outbound Free List FIFO. Initialized as (3*FIFO Size) and maintained by local CPU software. Yes Yes 0 31:20 Queue Base Address. Yes No 0 Read Write Value after Reset Table 4-88. (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer Register Bit Description 1:0 Reserved. Yes No 0 19:2 Outbound Post Head Pointer. Local Memory Offset for the Outbound Post List FIFO. Initialized as (2*FIFO Size) and maintained by local CPU software. Yes Yes 0 31:20 Queue Base Address. Yes No 0 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 87 Section 4 Registers Messaging Queue Registers Table 4-89. (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer Register Bit Description Read Write Value after Reset 1:0 Reserved. Yes No 0 19:2 Outbound Post Tail Pointer. Local Memory Offset for the Outbound Post List FIFO. Initialized as (2*FIFO Size). Maintained by MU hardware and incremented modulo the FIFO size. Yes Yes 0 31:20 Queue Base Address. Yes No 0 Read Write Value after Reset Yes Yes 0 Table 4-90. (QSR; PCI:E8h, LOC:168h) Queue Status/Control Register Bit 0 Description I2O Decode Enable. When set, replaces Mailbox registers 0 and 1 with the Inbound and Outbound Queue Port registers and redefines Space 1 as PCI Base Address 0 to be accessed by PCIBAR0. Former Space 1 registers F0, F4, and F8 should be programmed to configure their shared I2O memory space, defined as PCI Base Address 0. 1 Queue Local Space Select. When set to 0, use Local Address Space 0 Bus Region descriptor for Queue accesses. When set to 1, use Local Address Space 1 Bus Region descriptor for Queue accesses. Yes Yes 0 2 Outbound Post List FIFO Prefetch Enable. When set, prefetching occurs from the Outbound Post List FIFO if it is not empty. Yes Yes 0 3 Inbound Free List FIFO Prefetch Enable. When set, prefetching occurs from the Inbound Free List FIFO if it is not empty. Yes Yes 0 4 Inbound Post List FIFO Interrupt Mask. When set, Interrupt is masked. Yes Yes 1 5 Inbound Post List FIFO Interrupt. Set when the Inbound Post List FIFO is not empty. Not affected by the Interrupt Mask bit. Yes No 0 6 Outbound Free List FIFO Overflow Interrupt Mask. When set, Interrupt is masked. Yes Yes 1 7 Outbound Free List FIFO Overflow Interrupt. Set when the Outbound Free List FIFO becomes full. A Local LSERR (NMI) interrupt is generated if enabled in the Interrupt Control/Status register. Writing 1 clears interrupt. Yes Yes/Clr 0 Unused. Yes No 0 31:8 88 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 5. PIN DESCRIPTION Table 5-1 lists the abbreviations used in this section to represent the various pin types. Table 5-1. Pin Type Abbreviations 5.1 Pin Summary Abbreviation Pin Type The tables in this section describe the PCI 9080 pins. Table 5-2 through Table 5-5 provide pin information common to all three Local Bus modes of operation-- C, J, and S: I/O * Power and Ground OC Open collector pin * Serial EEPROM Interface TP Totem pole pin * PCI System Bus Interface * Local Bus Mode and Processor Independent Interface The pins in Table 5-6 through Table 5-8 correspond to the Local Bus modes of the PCI 9080: I Input and output pin Input pin only O Output pin only TS Tri-state pin STS Sustained tri-state pin, driven high for one CLK before float DTS Driven tri-state pin, driven high for one-half CLK before float All Local Bus internal pull-ups go through a 2 k resistor. All Local Bus internal pull-downs go through a 100 k resistor. * C Bus Mode Interface Pin Description (32-bit address/32-bit data, nonmultiplexed) All local tri-state I/O pins should have external pull-ups (use 3 k - 10 k). * J Bus Mode Interface Pin Description (32-bit address/32-bit data, multiplexed) Unspecified pins are not connected. * S Bus Mode Interface Pin Description (32-bit address/16-bit data, multiplexed) Note: For PCI Pins, DO NOT pull any pins up or down unless the PCI 9080 is being used in an embedded design. Refer to the PCI Local Bus Specification, v2.1, page 123. The following pins have internal pull-ups: ADMODE, BIGEND#, BTERM#, DREQ[1:0]#, EEDO, EESEL, LINTi#, LLOCK#, LRESETi#, NB#, READYi#, S[2:0], SHORT#, and WAITI#. The following pins have internal pull-downs: BREQ, LHOLDA, TEST, and USERI. For a visual view of the chip pin out, refer to Figure 7-3 in Section 7.3, "PCI 9080 Pin Out." PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 89 Section 5 Pin Description Pin Out Common to All Bus Modes 5.2 Pin Out Common to All Bus Modes Table 5-2. Power and Ground Pin Description Total Pins Pin Type Pin Number Test 1 I 49 Power (+5V ) 6 I 53, 68, 105, 144, 157, 167 Five volt power supply pins for core. 38, 60, 83 Power supply pins for PCI Bus pins. Symbol Signal Name TEST VDDL (Core) VDDH (PCI) Power (+5V or +3.3V ) 3 VDDH (Local) Power (+5V ) 3 VSS Ground 20 I Function Test Pin. Pull high for test, low for normal operation. When TEST is pulled high, all outputs except USERO (pin 27) are placed in tri-state. USERO provides a NAND-TREE output when TEST is pulled high. Liberal .01 to .1 F decoupling capacitors should be placed near the PCI 9080. Liberal .01 to .1 F decoupling capacitors should be placed near the PCI 9080. I 1, 124, 184 Power supply pins for Local Bus pins. Liberal .01 to .1 F decoupling capacitors should be placed near the PCI 9080. I 22, 37, 45, 52, 59, 67, 75, 82, 90, 98, 104, 114, 123, 134, 143, 156, 166, 183, 193, 208 Ground pins. Table 5-3. Serial EEPROM Interface Pin Description Total Pins Pin Type Pin Number Serial EEPROM Chip Select 1 O TP 8 mA 176 Serial EEPROM chip select. EEDI Serial EEPROM Data IN 1 O TP 8 mA 172 Write data to serial EEPROM. EEDO Serial EEPROM Data OUT 1 I 171 Read data from serial EEPROM. EESK Serial Data Clock 1 O TP 8 mA 173 Serial EEPROM clock. SHORT# Load Short 1 I 174 When active low, only five 32-bit registers are loaded from the serial EEPROM. When active high, all Local Configuration registers are also loaded from serial EEPROM. EESEL Serial EEPROM Select 1 I 175 When high, use 93CS46 (1K bit) serial EEPROM. When low, use 93CS56 (2K bit) serial EEPROM. Symbol Signal Name EECS Function Note: Serial EEPROM interface operates at the core voltage (+5V). The PCI 9080 requires the use of a serial EEPROM that can operate up to 1 MHz. 90 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 5 Pin Description Pin Out Common to All Bus Modes Table 5-4. PCI System Bus Interface Pin Description Total Pins Pin Type Pin Number Address and Data 32 I/O TS PCI 32-36, 39-44, 46-47, 76-81, 84-89, 91-97 C/BE[3:0]# Bus Command and Byte Enables 4 I/O TS PCI 70-73 CLK Clock 1 I 54 Provides timing for all transactions on PCI and is an input to every PCI device. PCI operates up to 33 MHz. DEVSEL# Device Select 1 I/O STS PCI 64 When actively driven, indicates driving device has decoded its address as Target of current access. As an input, indicates whether any device on bus is selected. FRAME# Cycle Frame 1 I/O STS PCI 57 Driven by current Master to indicate beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, Data transfers continue. When FRAME# is de-asserted, transaction is in final Data phase. GNT# Grant 1 I 51 Indicates to agent that access to bus is granted. Every Master has its own REQ# and GNT#. IDSEL Initialization Device Select 1 I 63 Used as chip select during configuration Read and Write transactions. INTA# Interrupt A 1 O OC PCI 55 Used to request interrupt. IRDY# Initiator Ready 1 I/O STS PCI 61 Indicates ability of initiating agent (Bus Master) to complete current Data phase of transaction. LOCK# Lock 1 I/O STS PCI 69 Indicates an atomic operation that may require multiple transactions to complete. PAR Parity 1 I/O TS PCI 74 Even parity across AD[31:0] and C/BE[3:0]#. All PCI agents require parity generation. PAR is stable and valid one clock after Address phase. For Data phases, PAR is stable and valid one clock after either IRDY# is asserted on a Write transaction or TRDY# is asserted on a Read transaction. Once PAR is valid, it remains valid until one clock after completion of current Data phase. PERR# Parity Error 1 I/O STS PCI 65 Reporting of data parity errors during all PCI transactions, except during a Special Cycle. REQ# Request 1 O PCI 50 Indicates to arbiter that this agent needs to use the bus. Every Master has its own GNT# and REQ#. RST# Reset 1 I 56 Used to bring PCI-specific registers, sequencers and signals to a consistent state. SERR# Systems Error 1 O OC PCI 66 Reports address parity errors, data parity errors on Special Cycle command, or any other system error where result will be catastrophic. STOP# Stop 1 I/O STS PCI 62 Indicates current Target is requesting Master to stop current transaction. TRDY# Target Ready 1 I/O STS PCI 58 Indicates ability of Target agent (selected device) to complete current Data phase of transaction. Symbol Signal Name AD[31:0] PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Function All multiplexed on the same PCI pins. Bus transaction consists of an Address phase followed by one or more Data phases. The PCI 9080 supports both Read and Write bursts. All multiplexed on the same PCI pins. During Address phase of a transaction, C/BE[3:0]# defines the bus command. During Data phase C/BE[3:0]# are used as Byte Enables. Refer to PCI Specification v2.1 for further detail. 91 Section 5 Pin Description Pin Out Common to All Bus Modes Table 5-5. Local Bus Mode and Processor Independent Interface Pin Description Total Pins Pin Type Pin Number Address Decode Mode 1 I 20 Determines how S[2:0] are used to access the PCI 9080 Internal registers. BIGEND# Big Endian Select 1 I 48 Can be asserted during Local Bus Address phase of Direct Master transfer or Configuration Register access to specify use of Big Endian byte ordering. Big Endian byte order for Direct Master transfers or Configuration Register accesses is also programmable through Configuration registers. BPCLKo Buffered PCI Clock Output 1 O TP 8 mA 168 Provides a buffered PCI clock output. BREQ Bus Request 1 I 169 Asserted to indicate a Local Bus Master requires the bus. If enabled through the PCI 9080 Configuration registers, the PCI 9080 releases bus during a DMA transfer if this signal is asserted. BREQo Bus Request Out 1 O TP 8 mA 21 Asserted to indicate the PCI 9080 requires bus to perform a direct PCI-to-Local Bus access while a Direct Master access is pending on Local Bus. It can be used with external logic to generate Backoff to a Local Bus Master. Its operational parameters are set up through the PCI 9080 Configuration registers. BTERMo# Burst Terminate Out 1 O DTS 8 mA 28 Asserted, along with READYo#, to request break up of a burst and start of a new Address cycle (Abort only). DACK[1:0]# DMA Acknowledge Outputs 2 O TP 8 mA 25, 30 DMPAF# Direct Master Programmable Almost Full 1 O TP 8 mA 8 DP[3:0] Data Parity 4 I/O TS 8 mA 12-15 Parity is even for each of up to four byte lanes on Local Bus. Parity is checked for writes to the PCI 9080 or reads by the PCI 9080. Parity is generated for reads from the PCI 9080 or writes by the PCI 9080. DREQ[1:0]# DMA Request Inputs 2 I 24, 29 When a channel is programmed through the Configuration registers to operate in Demand mode, its DREQ input serves as a DMA request. DREQ0# corresponds to the PCI 9080 DMA Ch 0 and DREQ1# to DMA Ch 1. LDSHOLD Direct Slave HOLD Request 1 O TP 8 mA 165 Asserted concurrent with LHOLD to indicate the PCI 9080 is requesting use of Local Bus to perform a Direct Slave transfer. LINTi# Local Interrupt In 1 I 151 When asserted low, causes a PCI interrupt. LINTo# Local Interrupt Out 1 O TP 8 mA 152 Synchronous level output that remains asserted as long as an interrupt condition exists. If an edge level interrupt is required, disabling and then enabling Local interrupts through the Interrupt Control/Status register (INTCSR) creates an edge if the interrupt condition still exists or a new interrupt condition occurs. LLOCKo# Bus Lock 1 O TP 8 mA 7 Indicates an atomic operation for a Direct Slave PCI-to-Local Bus access may require multiple transactions to complete. LRESETi# Local Reset Input 1 I 150 Resets Local Bus portion of the PCI 9080, Local Configuration registers and DMA Configuration registers. Also causes local reset output to be asserted. Symbol Signal Name ADMODE 92 Function When a channel is programmed through the Configuration registers to operate in Demand mode, its DACK output indicates a DMA transfer is being executed. DACK0# corresponds to the PCI 9080 DMA Ch 0 and DACK1# to DMA Ch 1. Direct Master Write FIFO almost full status output. Programmable through a Configuration register. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 5 Pin Description Pin Out Common to All Bus Modes Table 5-5. Local Bus Mode and Processor Independent Interface Pin Description (continued) Total Pins Pin Type Pin Number System Error Interrupt Output 1 O TP 8 mA 23 Bus Mode 2 I 9, 10 Symbol Signal Name LSERR# MODE[1:0] Function Synchronous level output asserted when PCI Bus Target Abort or Master Abort Status bit is set in PCI Status Configuration register. If an edge level interrupt is required, disabling and then enabling LSERR# interrupts through interrupt/control status creates an edge if interrupt condition still exists or new interrupt condition occurs. Selects bus operation mode of the PCI 9080: Bit 1 Bit 0 0 0 1 1 0 1 0 1 Bus Mode C J S Reserved NB# No Local Bus Initialization 1 I 26 Externally forces Local Init Done bit in Init Control Register to 1. Init Done bit is also programmable through Local Bus Configuration accesses. The PCI 9080 issues Retrys to all PCI accesses until Local Init Done bit is set. If this bit is not going to be set by a Local processor, tie NB# low. PCHK# Data Parity Check 1 O TP 8 mA 16 Parity is checked for writes to the PCI 9080 or reads by the PCI 9080. Parity is checked for each byte lane with its byte enable asserted. Asserted in Clock cycle following data being checked if a parity error is detected. S[2:0] Address Select 3 I 17-19 If ADMODE is high, internal PCI 9080 registers are selected when LA[31:29] match S[2:0]. If ADMODE is low, internal PCI 9080 registers are selected when S0 is asserted low. USERI User Input 1 1 31 General-purpose input that can be read from the PCI 9080 Configuration registers. USERO User Output 1 O TP 12 mA 27 General-purpose output controlled from the PCI 9080 Configuration registers. WAITI# Wait Input 1 I 6 Can be asserted to cause the PCI 9080 to insert wait states for Local Direct Master accesses to PCI Bus. Can be thought of as a ready input for Direct Master accesses. WAITO# Wait Out 1 O TS 8 mA 149 Indicates the PCI 9080 programmable wait state generator status. WAITO# is asserted when wait states are being caused by internal wait state generator. Can be thought of as an output providing Ready Out status. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 93 Section 5 Pin Description C Bus Mode Pin Out 5.3 C Bus Mode Pin Out Table 5-6. C Bus Mode Interface Pin Description C Mode Bus Symbol Signal Name Total Pins Pin Type Pin Number ADS# Address Strobe 1 I/O TS 12 mA 154 Indicates a valid address and start of a new Bus access. Asserted for first clock of a Bus access. BLAST# Burst Last 1 I/O TS 8 mA 155 Signal driven by current Local Bus Master to indicate last transfer in a Bus access. BTERM# Burst Terminate 1 I 146 For processors that burst up to four Lwords. If Bterm is disabled through the PCI 9080 Configuration registers, the PCI 9080 also bursts up to four Lwords. If enabled, the PCI 9080 continues to burst until a BTERM# input is asserted. BTERM# is a ready input that breaks up a Burst cycle and causes another Address cycle to occur. Used in conjunction with the PCI 9080 programmable wait state generator. DEN# Data Enable 1 O TS 12 mA 145 Used in conjunction with DT/R# to provide control for data transceivers attached to Local Bus. DT/R# Data Transmit/Receive 1 O TS 12 mA 138 Used in conjunction with DEN# to provide control for data transceivers attached to Local Bus. When asserted, signal indicates the PCI 9080 receives data. LW/R# Write/Read 1 I/O TS 12 mA 137 Asserted low for reads and high for writes. LLOCK# Bus Lock 1 I 153 Indicates an atomic operation that may require multiple transactions to complete. Used by the PCI 9080 for Direct Local access to PCI Bus. LA[31:2] Address Bus 30 I/O TS 8 mA 136, 135, 133-125, 122-115, 113-106, 103-101 LD[31:0] Data Bus 32 I/O TS 8 mA 177-182, 185-192, 194-207, 2-5 94 Function Carries upper 30 bits of physical address bus. During bursts, LA[31:2] increment to indicate successive Data cycles. Carries 32-, 16-, or 8-bit data quantities depending on bus width configuration. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 5 Pin Description C Bus Mode Pin Out Table 5-6. C Bus Mode Interface Pin Description (continued) C Mode Bus Symbol Signal Name Total Pins Pin Type Pin Number Function LBE[3:0]# Byte Enables 4 I/O TS 12 mA 139-142 Encoded, based on configured bus width, as follows: 32-bit bus: For a 32-bit bus, the four byte enables indicate which of the four bytes are active during a Data cycle: BE3# Byte Enable 3--LD[31:24] BE2# Byte Enable 2--LD[23:16] BE1# Byte Enable 1--LD[15:8] BE0# Byte Enable 0--LD[7:0] 16-bit bus: For a 16-bit bus, BE3#, BE1# and BE0# are encoded to provide BHE#, LA1, and BLE#, respectively: BE3# Byte High Enable (BHE#)--LD[15:8] BE2# not used BE1# Address bit 1 (LA1) BE0# Byte Low Enable (BLE#)--LD[7:0] 8-bit bus: For an 8-bit bus, BE1# and BE0# are encoded to provide LA1and LA0, respectively: BE3# not used BE2# not used BE1# Address bit 1 (LA1) BE0# Address bit 0 (LA0) LCLK Local Processor Clock 1 I 160 Local clock input. LHOLD Hold Request 1 O TP 8 mA 158 Asserted to request use of Local Bus. The Local Bus arbiter asserts LHOLDA when control is granted. LHOLDA Hold Acknowledge 1 I 159 Asserted by Local Bus arbiter when control is granted in response to LHOLD. The bus should not be granted to the PCI 9080 unless requested by LHOLD. LRESETo# Local Bus Reset Out 1 O TP 8 mA 11 Asserted when the PCI 9080 chip is reset. Used to drive RESET# input of Local processor. READYi# Ready In 1 I 147 When the PCI 9080 is a Bus Master, indicates that Read data on bus is valid or that a Write Data transfer is complete. Used in conjunction with the PCI 9080 programmable wait state generator. READYo# Ready Out 1 O DTS 8 mA 148 When a Local Bus access is made to the PCI 9080, indicates Read data on bus is valid or a Write Data transfer is complete. READYo# can be connected to READYi#. EOT0# End of Transfer for DMA Ch 0 1 I 163 Terminates current DMA Ch 0 transfer. EOT1# End of Transfer for DMA Ch 1 1 I 164 Terminates current DMA Ch 1 transfer. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 95 Section 5 Pin Description J Bus Mode Pin Out 5.4 J Bus Mode Pin Out Table 5-7. J Bus Mode Interface Pin Description J Bus Mode Symbol Signal Name Total Pins Pin Type Pin Number ALE Address Latch Enable 1 O TS 8 mA 161 Asserted during Address phase and de-asserted before Data phase. ADS# Address Strobe 1 I/O TS 12 mA 154 Indicates valid address and start of a new Bus access. Asserted for first clock of a Bus access. BLAST# Burst Last 1 I/O TS 8 mA 155 Signal driven by current Local Bus Master to indicate last transfer in a Bus access. BTERM# Burst Terminate 1 I 146 For processors that burst up to four Lwords. If Bterm is disabled through the PCI 9080 Configuration registers, the PCI 9080 also bursts up to four Lwords. If enabled, the PCI 9080 continues to burst until a BTERM# input is asserted. BTERM# is a ready input that breaks up a Burst cycle and causes another Address cycle to occur. Used in conjunction with the PCI 9080 programmable wait state generator. DEN# Data Enable 1 I/O TS 12 mA 145 As an input, DEN# must only be asserted during Data phases. For processor systems in which ADS# is not asserted during Data phase, DEN# can be pulled high. Function As an output, DT/R# is used in conjunction with DEN# to provide control for data transceivers attached to Local Bus. DT/R# Data Transmit/Receive 1 O TS 12 mA 138 Used in conjunction with DEN# to provide control for data transceivers attached to Local Bus. When asserted, signal indicates the PCI 9080 receives data. LW/R# Write/Read 1 I/O TS 12 mA 137 Asserted low for reads and high for writes. LABS[3:2] Address Bus Burst 2 I/O TS 8 mA 162,163 Carries word address of 32-bit memory address. Incremented during Burst access. LAD[31:0] Address/Data Bus 32 I/O TS 8 mA 136, 135, 133-125, 122-115, 113-106, 103-99 During Address phase, bus carries upper 30 bits of physical address bus. During Data phase, bus carries 32 bits of data. 96 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 5 Pin Description J Bus Mode Pin Out Table 5-7. J Bus Mode Interface Pin Description (continued) J Mode Bus Symbol Signal Name Total Pins Pin Type Pin Number Function LBE[3:0]# Byte Enables 4 I/O TS 12 mA 139-142 Byte enables are encoded based on configured bus width as follows: 32-Bit Bus: For a 32-bit bus, the four byte enables indicate which of the four bytes are active during a Data cycle: BE3# Byte Enable 3--LAD[31:24] BE2# Byte Enable 2--LAD[23:16] BE1# Byte Enable 1--LAD[15:8] BE0# Byte Enable 0--LAD[7:0] 16-Bit Bus: For a 16-bit bus, BE3#, BE1# and BE0# are encoded to provide BHE#, LA1, and BLE#, respectively: BE3# Byte High Enable (BHE#)--LAD[15:8] BE2# not used BE1# Address bit 1 (LA1) BE0# Byte Low Enable (BLE#)--LAD[7:0] 8-Bit Bus: For an 8-bit bus, BE1# and BE0# are encoded to provide LA1and LA0, respectively: BE3# not used BE2# not used BE1# Address bit 1 (LA1) BE0# Address bit 0 (LA0) LCLK System Clock 1 I 160 Local clock input. LHOLD Hold Request 1 O TP 8 mA 158 Asserted to request use of Local Bus. The Local Bus arbiter asserts LHOLDA when control is granted. LHOLDA Hold Acknowledge 1 I 159 Asserted by Local Bus arbiter when control is granted in response to LHOLD. The bus should not be granted to the PCI 9080 unless requested by LHOLD. LLOCK# Bus Lock 1 I 153 Indicates an atomic operation that may require multiple transactions to complete. Used by the PCI 9080 for Direct Local access to PCI Bus. LRESETo# Local Bus Reset Out 1 O TP 8 mA 11 Asserted when the PCI 9080 chip is reset. READYi# Ready In 1 I 147 When the PCI 9080 is a Bus Master, READYi# is used to indicate Read data on bus is valid or a Write Data transfer is complete. READYi# is used in conjunction with the PCI 9080 programmable wait state generator. READYo# Ready Out 1 O DTS 8 mA 148 When a Local Bus access is made to the PCI 9080, indicates that Read data on bus is valid or that a Write Data transfer is complete. READYo# can be connected to READYi#. EOT0# End of Transfer for DMA Ch 0 1 I 4 Terminates current DMA Ch 0 transfer. EOT1# End of Transfer for DMA Ch 1 1 I 5 Terminates current DMA Ch 1 transfer. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 97 Section 5 Pin Description S Bus Mode Pin Out 5.5 S Bus Mode Pin Out Table 5-8. S Bus Mode Interface Pin Description S Bus Mode Symbol Signal Name Total Pins Pin Type Pin Number Function ALE Address Latch Enable 1 O TS 8 mA 161 Asserted during Address phase and de-asserted before Data phase. AS# Address Strobe 1 I/O TS 12 mA 154 Indicates valid address and start of a new Bus access. Asserted for first clock of a Bus access. BLAST# Burst Last 1 I/O TS 8 mA 155 Signal driven by current Local Bus Master to indicate last transfer in a Bus access. BTERM# Burst Terminate 1 I 146 For processors that burst up to eight words and do not use BTERM# input. If Bterm is disabled through the PCI 9080 Configuration registers, the PCI 9080 also bursts up to eight words. If enabled, the PCI 9080 continues to burst until a BTERM# input is asserted. BTERM# breaks up a Burst cycle and causes another Address cycle to occur. Used in conjunction with the PCI 9080 programmable wait state generator. DEN# Data Enable 1 O TS 12 mA 145 Used in conjunction with DT/R# to provide control for data transceivers attached to Local Bus. DT/R# Data Transmit/Receive 1 O TS 12 mA 138 Used in conjunction with DEN# to provide control for data transceivers attached to Local Bus. When asserted, signal indicates the PCI 9080 is receiving data. LA[31:16] Address Bus 16 I/O TS 8 mA 136, 135, 133-125, 122-118 Carries upper 16 bits of address. LABS[3:1] Address Bus Burst 3 I/O TS 8 mA 162-164 Carries word address of 32-bit memory address. Incremented during Burst access. LAD[15:1],D0 Address/Data Bus 16 I/O TS 8 mA 117-115, 113-106, 103-99 During Address phase, carries lower physical address bits. During Data phase, carries 16 bits of data. LBE[1:0]# Byte Enables 2 I/O TS 12 mA 141,142 LCLK Local Clock 1 I 160 Indicate which of the two bytes are active during a Data cycle. Local clock input. Note: For i960S processor systems, CLK2 input. i960S processor's RESET# input must be connected to the PCI 9080 LRESETo# output. This enables the PCI 9080 to determine phase of 2x clock processor. LHOLD Hold Request 1 O TP 8 mA 158 Asserted to request use of Local Bus. The Local Bus arbiter asserts LHOLDA when control is granted. LHOLDA Hold Acknowledge 1 I 159 Asserted by Local Bus arbiter when control is granted in response to LHOLD. The bus should not be granted to the PCI 9080 unless requested by LHOLD. 98 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 5 Pin Description S Bus Mode Pin Out Table 5-8. S Bus Mode Interface Pin Description (continued) S Bus Mode Symbol Signal Name Total Pins Pin Type Pin Number LLOCK# Bus Lock 1 I 153 Indicates an atomic operation that may require multiple transactions to complete. Used by the PCI 9080 for Direct Local access to PCI Bus. LRESETo# Local Bus Reset Out 1 O TP 8 mA 11 Asserted when the PCI 9080 chip is reset. Function Note: For i960S processors, this output must be used to drive Reset Input of i960S processor. Enables the PCI 9080 to determine phase of 2x clock processor. LW/R# Write/Read 1 I/O TS 12 mA 137 Asserted low for reads and high for writes. READYi# Ready In 1 I 147 When the PCI 9080 is a Bus Master, READYi# is used to indicate Read data on bus is valid or a Write Data transfer is complete. READYi# is used in conjunction with the PCI 9080 programmable wait state generator. READYo# Ready Out 1 O DTS 8 mA 148 When a Local Bus access is made to the PCI 9080, indicates that Read data on bus is valid or that a Write Data transfer is complete. READYo# can be connected to READYi#. EOT0# End of Transfer for DMA Ch 0 1 I 4 Terminates current DMA Ch 0 transfer. EOT1# End of Transfer for DMA Ch 1 1 I 5 Terminates current DMA Ch 1 transfer. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 99 This page intentionally left blank. 100 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 6. ELECTRICAL SPECIFICATIONS 6.1 General Specifications Table 6-1. Absolute Maximum Ratings Specification Maximum Rating Storage Temperature -65 to +150 C Ambient Temperature with Power Applied -55 to +125 C Supply Voltage to Ground -0.5 to +7.0V Input Voltage (VIN) (5V only) VSS -0.5V , VDD +0.5V Output Voltage (VOUT) (5V only) VSS -0.5V , VDD +0.5V Input Voltage (VIN) (3V only) VSS -0.3V , VDD +0.3V Output Voltage (VOUT) (3V only) VSS -0.3V , VDD +0.3V Table 6-2. Operating Ranges Ambient Temperature Supply Voltage (VDD) -40 to +85 C Input Voltage (VIN) Min Max 5V 5% VSS VDD 3V 5% VSS VDD Table 6-3. Capacitance (sample tested only) Parameter Test Conditions Pin Type Typical Value Units CIN VIN = 2.0V , f = 1 MHz Input 5 pF COUT VOUT = 2.0V , f = 1 MHz Output 10 pF PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 101 Section 6 Electrical Specifications General Specifications Table 6-4. Electrical Characteristics Estimated over Operating Range (1) Parameter Description VOH Output High Voltage VOL Output Low Voltage VIH Input High Level VIL Min Max Units IOH = -4.0 mA 2.4 Vcc V(1) IOL per Tables VSS 0.4 V(1) Vcc -- TTL = 2.0 VDD+10% V(1) Input Low Level Vss -- TTL = -0.5v TTL = 0.8v V(1) VOH3 PCI 3.3V Output High Voltage 1.8V IOH = -4.0 mA 0.9 Vcc Vcc V VOL3 PCI 3.3V Output Low Voltage 1.8V IOL per Tables Vss 0.1 Vcc V VIH3 PCI 3.3V Input High Level Vcc -- 0.5 Vcc Vcc +0.5 V VIL3 PCI 3.3V Input Low Level Vss -- -0.5 Vcc 0.3 Vcc V ILI Input Leakage Current VSS VIN VDD, VDD = Max -10 +10 A IOZ Tri-State Output Leakage Current VDD = Max, VSS VIN VDD -10 +10 A ICC Power Supply Current VDD=5.25V, PCLK=LCLK=33 MHz 60 130 mA Note: 102 Test Conditions 1.5V Assume Local = 5V PCI. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 6 Electrical Specifications Local Inputs 6.2 Local Inputs Local Clock THOLD TSETUP Inputs Valid Figure 6-1. PCI 9080 Local Input Setup and Hold Waveform Table 6-5. AC Electrical Characteristics (Local Inputs) Estimated over Operating Range Signals (Synchronous Inputs) CL = 50 pF, Vcc = 5.0 5% TSETUP (ns) (WORST CASE) THOLD (ns) (WORST CASE) ADS# 6 1 BIGEND 4 0 BLAST# 6 0 BREQi 7 0 BTERM# 7 1 DP[3:0] 4 0 DREQ[1:0]# 3 1 EOT0# 7 1 EOT1# 1 1 LA[31:0] 5 0 LAD 5 0 LBE[3:0]# 7 0 LD[31:0] 5 0 LHOLDA 7 2 LINTi 7 0 LLOCK 4 0 LW/R# 9 0 READYi# 8 1 S[2:0] 1 2 USERi 4 0 WAITi# Input Clocks 13 0 Min Max Local Clock Input Frequency 0 40 MHz PCI Clock Input Frequency 0 33 MHz PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 103 Section 6 Electrical Specifications Local Outputs 6.3 Local Outputs Local Clock TVALID (MAX) TVALID (MIN) Outputs Valid Figure 6-2. PCI 9080 Local Output Delay Table 6-6. AC Electrical Characteristics (Local Outputs) Estimated over Operating Range Signals (Synchronous Outputs) CL = 50 pF, Vcc = 5.0 5% ADS# Output TVALID (Max) 14.5 BLAST# 16 BREQo 13 BTERMo# 15 DACK[1:0]# 14 DEN# 13 DMPAF# 17 DP[3:0] 20 DT/R# 14 LA (Address, C Mode) LABS[3:1] LAD (Address, J Mode) 15.8 12 12.1 LAD (Data, J Mode) 15 LD (32- and 16-Bit Data, C Mode) 15 LD (8-Bit Data, C Mode) 20 LBE[3:0]# 16 LDSHOLD 12 LHOLD 13 LINTo# 13 LLOCKo# 12 LSERR# 12 LW/R# 14 PCHK# 12 READYo# 14 USERO 11 WAITo# 18 Note: 104 All TVALID (Mins) values are greater than 5 ns. PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 6 Electrical Specifications Table 6-7. ALE Operation Signal TVALID (ns) from Local Clock Min./Max. Pulse Width (ns) Min./Max. ALE 4.0 / 8.8 5.0 / 10.9 LAD[31:0] 5.5 / 12.1 N/A LCLK ALE LAD[31:0] min/max 4 ns/8.8 ns min/max 5.5 ns/12.1 ns min/max 9 ns/19.7 ns Figure 6-3. ALE Operation PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 105 This page intentionally left blank. 106 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 7. PACKAGE, SIGNAL, AND PIN OUT SPECS 7.1 Package Mechanical Dimensions For 208-pin PQFP, JC = 5 C/watt 30.6 0.4 28 0.1 156 105 104 157 30.6 0.4 28 0.1 0.15 0.05 Index 208 53 Pin 1 1 52 0.5 0.1 3.4 0.2 0.2 0.1 0.4/0.5/0.65 Dimensions in millimeters 1.3 0/3.5/7 Figure 7-1. Package Mechanical Dimensions PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 107 Section 7 Package, Signal, and Pin Out Specs Typical PCI Bus Master Adapter 7.2 Typical PCI Bus Master Adapter C Mode J Mode S Mode READYo# READYi# BLAST# BTERM# EOT0# EOT1# LHOLD LHOLDA LDSHOLD ADS# LW/R# DT/R# DEN# ALE READYo# READYi# BLAST# BTERM# EOT0# EOT1# LHOLD LHOLDA LDSHOLD AS# LW/R# DT/R# DEN# ALE READYo# READYi# BLAST# BTERM# EOT0# EOT1# LHOLD LHOLDA LDSHOLD LRESETi# LRESETo# LCLK LRESETi# LRESETo# LCLK LRESETi# LRESETo# LCLK LINTi# LSERR# LINTo# LINTi# LSERR# LINTo# LINTi# LSERR# LINTo# DP[3:0] PCHK# DP[3:0] PCHK# DP[3:0] PCHK# DREQ[1:0]# DACK[1:0]# DREQ[1:0]# DACK[1:0]# DREQ[1:0]# DACK[1:0]# WAITI# BIGEND# LLOCKo# BPCLKO BREQ DMPAF# WAITO# WAITI# BIGEND# LLOCKo# BPCLKO BREQ DMPAF# WAITO# WAITI# BIGEND# LLOCKo# BPCLKO BREQ DMPAF# WAITO# USERO USERI MODE[1:0] S[2:0] ADMODE NB# LLOCK# BREQo BTERMo# EECS EEDI EEDO EESK SHORT# EESEL USERO USERI MODE[1:0] S[2:0] ADMODE NB# LLOCK# BREQo BTERMo# EECS EEDI EEDO EESK SHORT# EESEL USERO USERI MODE[1:0] S[2:0] ADMODE NB# LLOCK# BREQo BTERMo# EECS EEDI EEDO EESK SHORT# EESEL LBE[3:0]# PCI Bus Interface PCI Bus AD[31:0] C/BE[3:0]# PAR FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# PERR# SERR# REQ# GNT# CLK RST# INTA# LOCK# PCI 9080 ADS# LW/R# DT/R# DEN# LAD[31:0] CPU Local Bus LABS[3:2] LBE[3:0]# LAD[15:1],D0 LA[31:16] LABS[3:1] LBE[1:0]# LD[31:0] LA[31:2] Memory I/O Controller Serial EEPROM Figure 7-2. Typical PCI Bus Master Adapter 108 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 7 Package, Signal, and Pin Out Specs PCI 9080 Pin Out 7.3 PCI 9080 Pin Out S J 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 C VSS VSS VSS BLAST# BLAST# BLAST# AS# ADS# ADS# LLOCK# LLOCK# LLOCK# LINTo# LINTo# LINTo# LINTi# LINTi# LINTi# LRESETi# LRESETi# LRESETi# WAITO# WAITO# WAITO# READYo# READYo# READYo# READYi# READYi# READYi# BTERM# BTERM# BTERM# DEN# DEN# DEN# VDDL(core) VDDL(core) VDDL(core) VSS VSS VSS LBE0# LBE0# LBE0# LBE1# LBE1# LBE1# NC LBE2# LBE2# NC LBE3# LBE3# DT/R# DT/R# DT/R# LW/R# LW/R# LW/R# LA31 LAD31 LA31 LA30 LAD30 LA30 VSS VSS VSS LA29 LAD29 LA29 LA28 LAD28 LA28 LA27 LAD27 LA27 LA26 LAD26 LA26 LA25 LAD25 LA25 LA24 LAD24 LA24 LA23 LAD23 LA23 LA22 LAD22 LA22 LA21 LAD21 LA21 VDDH(local) VDDH(local) VDDH(local) VSS VSS VSS LA20 LAD20 LA20 LA19 LAD19 LA19 LA18 LAD18 LA18 LA17 LAD17 LA17 LA16 LAD16 LA16 LAD15 LAD15 LA15 LAD14 LAD14 LA14 LAD13 LAD13 LA13 VSS VSS VSS LAD12 LAD12 LA12 LAD11 LAD11 LA11 LAD10 LAD10 LA10 LAD9 LAD9 LA9 LAD8 LAD8 LA8 LAD7 LAD7 LA7 LAD6 LAD6 LA6 LAD5 LAD5 LA5 VDDL(core) VDDL(core) VDDL(core) Refer to Section 5, "Pin Description," for a complete description of each pin used in C, J, and S modes. VDDL(core) LHOLD LHOLDA LCLK ALE LABS3 LABS2 NC LDSHOLD VSS VDDL(core) BPCLKO BREQ NC EEDO EEDI EESK SHORT# EESEL EECS NC NC NC NC NC NC VSS VDDH(local) NC NC NC NC NC NC NC NC VSS NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSS VDDL(core) LHOLD LHOLDA LCLK NC NC EOT0# EOT1# LDSHOLD VSS VDDL(core) BPCLKO BREQ NC EEDO EEDI EESK SHORT# EESEL EECS LD31 LD30 LD29 LD28 LD27 LD26 VSS VDDH(local) LD25 LD24 LD23 LD22 LD21 LD20 LD19 LD18 VSS LD17 LD16 LD15 LD14 LD13 LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 VSS 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 PCI 9080 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 VSS VSS VSS LAD4 LAD4 LA4 LAD3 LAD3 LA3 LAD2 LAD2 LA2 LAD1 LAD1 NC D0 LAD0 NC VSS VSS VSS AD0 AD0 AD0 AD1 AD1 AD1 AD2 AD2 AD2 AD3 AD3 AD3 AD4 AD4 AD4 AD5 AD5 AD5 AD6 AD6 AD6 VSS VSS VSS AD7 AD7 AD7 AD8 AD8 AD8 AD9 AD9 AD9 AD10 AD10 AD10 AD11 AD11 AD11 AD12 AD12 AD12 VDDH(PCI) VDDH(PCI) VDDH(PCI) VSS VSS VSS AD13 AD13 AD13 AD14 AD14 AD14 AD15 AD15 AD15 AD16 AD16 AD16 AD17 AD17 AD17 AD18 AD18 AD18 VSS VSS VSS PAR PAR PAR C/BE0# C/BE0# C/BE0# C/BE1# C/BE1# C/BE1# C/BE2# C/BE2# C/BE2# C/BE3# C/BE3# C/BE3# LOCK# LOCK# LOCK# VDDL(core) VDDL(core) VDDL(core) VSS VSS VSS SERR# SERR# SERR# PERR# PERR# PERR# DEVSEL# DEVSEL# DEVSEL# IDSEL IDSEL IDSEL STOP# STOP# STOP# IRDY# IRDY# IRDY# VDDH(PCI) VDDH(PCI) VDDH(PCI) VSS VSS VSS TRDY# TRDY# TRDY# FRAME# FRAME# FRAME# RST# RST# RST# INTA# INTA# INTA# CLK CLK CLK VDDL(core) VDDL(core) VDDL(core) VDDH(Local) NC NC EOT0# EOT1# WAITI# LLOCKo# DMPAF# MODE1 MODE0 LRESETo# DP3 DP2 DP1 DP0 PCHK# S2 S1 S0 ADMODE BREQo VSS LSERR# DREQ1# DACK1# NB# USERO BTERMo# DREQ0# DACK0# USERI AD31 AD30 AD29 AD28 AD27 VSS VDDH(PCI) AD26 AD25 AD24 AD23 AD22 AD21 VSS AD20 AD19 BIGEND# TEST REQ# GNT# VSS VDDH(Local) NC NC EOT0# EOT1# WAITI# LLOCKo# DMPAF# MODE1 MODE0 LRESETo# DP3 DP2 DP1 DP0 PCHK# S2 S1 S0 ADMODE BREQo VSS LSERR# DREQ1# DACK1# NB# USERO BTERMo# DREQ0# DACK0# USERI AD31 AD30 AD29 AD28 AD27 VSS VDDH(PCI) AD26 AD25 AD24 AD23 AD22 AD21 VSS AD20 AD19 BIGEND# TEST REQ# GNT# VSS VDDH(Local) LD3 LD2 LD1 LD0 WAITI# LLOCKo# DMPAF# MODE1 MODE0 LRESETo# DP3 DP2 DP1 DP0 PCHK# S2 S1 S0 ADMODE BREQo VSS LSERR# DREQ1# DACK1# NB# USERO BTERMo# DREQ0# DACK0# USERI AD31 AD30 AD29 AD28 AD27 VSS VDDH(PCI) AD26 AD25 AD24 AD23 AD22 AD21 VSS AD20 AD19 BIGEND# TEST REQ# GNT# VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 VDDL(core) LHOLD LHOLDA LCLK ALE LABS3 LABS2 LABS1 LDSHOLD VSS VDDL(core) BPCLKO BREQ NC EEDO EEDI EESK SHORT# EESEL EECS NC NC NC NC NC NC VSS VDDH(local) NC NC NC NC NC NC NC NC VSS NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSS Figure 7-3. PCI 9080 Pin Out (All Modes) PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 109 This page intentionally left blank. 110 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 8. TIMING DIAGRAMS PCI 9080 operates in three modes, selected through mode pins, corresponding to three bus types--C, J, and S. Timing Diagrams are provided for each mode. For some functions, a timing diagram may only be provided for one mode of operation. Even though a different mode is used, that timing diagram can be used to determine functionality. 8.1 Initialization 0ns 50ns 100ns 150ns 200ns CLK RST# ASYNCHRONOUS LCLK LRESETo# Timing Diagram 8-1. (C, J Modes) PCI RST# Asserting Local Output LRESETo# 0ns 25ns 50ns 75ns 100ns 125ns 150n LRESETo# AS# LA[31:16] ADDR LAD[15:1] ADDR DATA LRESETo# must be used to establish Phase A relationship as shown. Timing Diagram 8-2. (S Mode) Two Phase Clock Synchronization Using LRESETo# PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 111 Section 8 Timing Diagrams Initialization 0ns 250ns 500ns LCLK LHOLD LDSHOLD WILL NOT BE RE-ASSERTED UNITL LHOLDA GOES LOW HIGH IF DIRECT SLAVE REQUEST |--- CAN GO HIGH LHOLDA Local Bus MUST REMAIN HIGH UNTIL LHOLD GOES LOW PCI 9080 DRIVES BUS Timing Diagram 8-3. PCI 9080 Local Bus Arbitration 112 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams Initialization 0us 5us 10us 15us 20us 25us EESK LRESETo# EECS EEDI EEDO 0 1 1 0 0 0 0 0 INTERNALLY PULLED UP 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 START BIT 0 INDICATES SERIAL EEPROM PRESENT ----| D7 D6 D5 D4 D3 D2 D1 D0 BITS [31:16] CFG REGISTER 0 HEX . EESK EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 BITS [15:0] CFG REGISTER 0 HEX D7 D6 D5 D4 D3 BITS [31:16] OF CFG REGISTER 8 HEX . . CONTINUES . EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 LAST WORD D1 D0 CONTINUES SHORT: BITS [15:0] MAILBOX 1 LOC C4 HEX LONG: BITS [15:0] LOC REGISTER 98 HEX EXTRA LONG: BITS [15:0] PCI Base Address for Local Expansion ROM 54 HEX EESK, EEDO, EECS FROM CFG REGISTERS AFTER COMPLETION OF READ Timing Diagram 8-4. PCI 9080 1K Serial EEPROM PCI Initialization PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 113 Section 8 Timing Diagrams 0ns Initialization 100ns 200ns 300ns 400ns 500n CLK FRAME# AD[31:0] ADDR DATA C/BE[3:0]# CMD BE IRDY# DEVSEL# TRDY# INTA# RESPONSE ON THE PCI SIDE [3,15] LCLK LINTi# Timing Diagram 8-5. Local Interrupt (LINTi#) Input Asserting PCI Output INTA# 114 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 8.2 C Mode 8.2.1 C Mode Direct Slave 0ns CLK 50ns 100ns 150ns 200ns 4 250ns FRAME# AD[31:0] Data ADDR C/BE[3:0]# BE CMD=B IRDY# DEVSEL# TRDY# Timing Diagram 8-6. (C Mode) PCI Configuration Write to PCI 9080 PCI Configuration Register 0ns CLK 50ns 1 2 100ns 3 4 150ns 5 200ns 6 7 250ns 300ns 8 FRAME# AD[31:0] C/BE[3:0]# ADDR CMD=A Data Read BE IRDY# DEVSEL# TRDY# Timing Diagram 8-7. (C Mode) PCI Configuration Read to PCI 9080 PCI Configuration Register PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 115 Section 8 Timing Diagrams C Mode 0ns CLK 50ns 1 2 100ns 3 150ns 4 5 200ns 6 7 250ns 8 FRAME# AD[31:0] Data ADDR C/BE[3:0]# CMD=7 BE IRDY# DEVSEL# TRDY# Timing Diagram 8-8. (C Mode) PCI Memory Write to PCI 9080 Local Configuration Register 0ns CLK 50ns 1 2 100ns 3 4 150ns 5 200ns 6 7 250ns 8 FRAME# AD[31:0] C/BE[3:0]# ADDR CMD=6 Data Read BE IRDY# DEVSEL# TRDY# Timing Diagram 8-9. (C Mode) PCI Memory Read to PCI 9080 Local Configuration Register 116 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns CLK 100ns 1 2 3 4 200ns 5 6 7 300ns 8 400ns 500ns 14 FRAME# AD[31:0] C/BE[3:0]# ADDR CMD Data BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# LW/R# BLAST# LA[31:2] LD[31:0] ADDR Data READYI# Timing Diagram 8-10. (C Mode) Direct Slave Single Cycle Read (32-Bit Local Bus) PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 117 Section 8 Timing Diagrams C Mode 0ns CLK 250ns 1 2 3 4 5 6 7 500ns 8 FRAME# AD[31:0] C/BE[3:0]# ADDR Data CMD BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# LW/R# BLAST# LA[31:2] LD[31:0] ADDR Data READYi# Timing Diagram 8-11. (C Mode) Direct Slave Single Cycle Write 118 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LBE LW/R# LD[31:0] D0 LA[31:2] A D1 A+4 D2 A+8 D3 D4 A+C A+10 D5 A+14 D6 A+18 D7 A+1C BTERM# READYi# Eight Lword burst, no wait states, Burst enabled, Bterm enabled, 32-bit Local Bus. Note: If Bterm is disabled, a new ADS cycle starts every quad Lword boundary. Timing Diagram 8-12. (C Mode) PCI 9080 DMA or Direct Slave Burst Read from Local Bus, No Wait States, Bterm Enabled PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 119 Section 8 Timing Diagrams C Mode 0ns 250ns 500ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LBE LW/R# LD[31:0] LA[31:2] BTERM# D0 A D1 A+4 D2 A+8 D3 D4 A+C A+10 D5 D6 D7 A+14 A+18 A+1C D8 A+20 D9 D10 A+24 A+28 Bterm FORCES NEW ADS# --> READYi# Eight Lword burst, no wait states, Burst enabled, Bterm enabled, 32-bit Local Bus. Note: If Bterm is disabled, a new ADS# cycle starts every quad Lword boundary. Timing Diagram 8-13. (C Mode) DMA or Direct Slave PCI 9080 Burst Write to Local Bus, Bterm Enabled 120 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# ADDR D0 CMD D1 D2 D3 D4 BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# LW/R# BLAST# LA[31:2] ADDR LD[31:0] D0 +4 +8 +C D1 D2 D3 +10 D4 +14 +18 +1C D5 D6 D7 READYi# BTERM# No wait states, 32-bit bus, Burst enabled, Bterm disabled. Unused read data is flushed using with local processor. Timing Diagram 8-14. (C Mode) Direct Slave PCI-to-Local Burst Read, Bterm Disabled PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 121 Section 8 Timing Diagrams 0ns C Mode 100ns 200ns 300ns 400ns 500ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# 0001 LBE = 0 LW/R# LD[31:0] LA[31:2] D0 ADDR D1 A+4 D2 D3 A+8 A+C D4 A+10 D5 D6 D7 D8 A+14 A+18 A+1C A+20 BTERM# READYi# No wait states, Burst enabled, Bterm disabled, 32-bit Local Bus. Unaligned Transfer results in new ADS#. Note: Not all byte enables asserted or a quad boundary LA[3:2]=11 results in a new ADS#. Timing Diagram 8-15. (C Mode) PCI 9080 DMA or Direct Slave Burst Write, Bterm Disabled 122 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# ADDR CMD D0 D1 D2 D3 D4 BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# LW/R# BLAST# LA[31:2] LD[31:0] ADDR D0 +4 +8 D1 D2 +C D3 +10 D4 READYi# Timing Diagram 8-16. (C Mode) Direct Slave Read with Prefetch Counter Set to 5 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 123 Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750 LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS# LW/R# LD[31:0] LA[31:2] D0 A D1 +4 D2 D3 +8 +12 D4 +16 D5 D6 D7 D8 +20 +24 +28 +32 D9 D10 +36 A+40 BTERM# READYi# BREQ No wait states, Burst enabled, Bterm enabled, 32-bit Local Bus. Owned by local processor or another bus master. DMA continues from where it left off. Timing Diagram 8-17. (C Mode) Direct Slave or DMA Burst Write to 32-Bit Local Bus Suspended by BREQ Input 124 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns CLK FRAME# AD[31:0] ADDR C/BE[3:0]# CMD D0 D1 D2 D3 D4 BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# LW/R# BLAST# LA[31:2] ADDR LD[31:0] +4 D0 D1 +8 D2 +C D3 +10 D4 +14 D5 +18 D6 +1C D7 READYi# Five Lwords, one wait state, Burst enabled, Bterm disabled. Unused read data is flushed with local processor. Timing Diagram 8-18. (C Mode) Direct Slave Burst Read of Five Lwords with One Wait State PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 125 Section 8 Timing Diagrams C Mode 0ns CLK 250ns 1 2 3 4 5 6 7 500ns 8 FRAME# AD[31:0] C/BE[3:0]# ADDR CMD DO D1 D2 D3 D4 BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# BLAST# LW/R# LA[31:2] LD[31:0] A +4 D0 D1 +8 +C D2 D3 +10 D4 READYi# Five Lwords, one wait state, Burst enabled, Bterm enabled. Timing Diagram 8-19. (C Mode) Direct Slave Burst Write of Five Lwords with One Wait State 126 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns 1000ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# PERR# RETRY RETRY STOP# Delayed Read Retries WRITE IS NOT ALLOWED DURING DELAYED READ READS DATA WRITE RETRIES AND COMPLETES LCLK LHOLD LHOLDA ADS# BLAST# LA[31:2] LD[31:0] LBE[3:0]# READYi# LW/R# Disconnect immediately for a read. Don't effect pending reads when write cycle occurs. Don't flush Read FIFO if PCI read cycle completes. Force Retry on write if read pending. De-assert TRDY# until space is available in Direct Slave Write FIFO. Timing Diagram 8-20. (C Mode) Direct Slave Read 2.1 Spec PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 127 Section 8 Timing Diagrams 0ns C Mode 250ns 500ns 750ns 1000ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# BLAST# LA[31:2] LD[31:0] LBE[3:0]# READYi# LW/R# Timing Diagram 8-21. (C Mode) Direct Slave Read No Flush Mode (Read Ahead Mode) 128 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# D0 ADDR CMD D1 BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# BLAST# LW/R# LA[31:2] LBE[3:0]# LD[31:0] A C D A+4 E F C D E F READYi# Timing Diagram 8-22. (C Mode) Direct Slave Read of Two Lwords from 8-Bit Bus PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 129 Section 8 Timing Diagrams 0ns C Mode 100ns 200ns 300ns 400ns LHOLD LHOLDA ADS# BLAST# LA[31:2] LBE[3:0]# LD[31:0] A C D [7:0] [15:8] A+4 E [23:16] F [31:24] C [7:0] D [15:8] E [23:16] F [31:24] READYi# Timing Diagram 8-23. (C Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 8-Bit Local Bus, No Wait States, Bterm Enabled 130 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# ADDR CMD D0 D1 BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# LW/R# BLAST# LA[31:2] LD[31:0] LBE[3:0]# A A+4 [15:0] [31:16] [15:0] [31:16] 4 6 4 6 READYi# Timing Diagram 8-24. (C Mode) Direct Slave Read of Two Lwords from 16-Bit Bus PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 131 Section 8 Timing Diagrams 0ns C Mode 100ns 200ns 300ns LCLK LHOLD LHOLDA ADS# BLAST# LA[31:2] LBE[3:0]# LD[31:0] A 4 D0[15:0] A+4 6 4 D0[31:16] D1[15:0] 6 D1[31:16] READYi# Timing Diagram 8-25. (C Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 16-Bit Local Bus, No Wait States, Bterm Enabled 132 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns 1000ns 1250ns 1500ns CLK FRAME# AD[31:0] C/BE[3:0]# A D0 BE A D1 BE IRDY# DEVSEL# TRDY# STOP# LCLK LHOLD LHOLDA ADS# BLAST# LW/R# LA[31:2] LBE[3:0]# LD[31:0] A C D A+4 E F [7:0] [15:8][23:16] [31:24] C D E F [7:0] [15:8][23:16] [31:24] READYi# Timing Diagram 8-26. (C Mode) Direct Slave Read of Two Lwords from 8-Bit I/O Local Bus, Burst Disabled PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 133 Section 8 Timing Diagrams 0ns C Mode 250ns 500ns 750ns 1000ns 1250ns 1500ns 1 CLK FRAME# AD[31:0] C/BE[3:0]# A D0 A D1 BE BE IRDY# DEVSEL# TRDY# STOP# LCLK LHOLD LHOLDA ADS# BLAST# LW/R# LA[31:2] LBE[3:0]# LD[31:0] A+4 A C D E F C D E F READYi# Timing Diagram 8-27. (C Mode) Direct Slave Write of Two Lwords to 8-Bit I/O Local Bus, Burst Disabled 134 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 100ns CLK 4 200ns 300ns 400ns 500ns FRAME# AD[31:0] ADDR C/BE[3:0]# CMD Data= AABBCCDD 01234567 BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# LW/R# BLAST# LA[31:2] LD[31:0] LBE[3:0] ADDR DDCCBBAA 67452301 LBE READYi# Timing Diagram 8-28. (C Mode) Direct Slave in BIGEND Local Bus with BIGEND# Input or Internal Register Setting PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 135 Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns CLK FRAME# AD[31:0] C/BE[3:0]# ADDR R D0 D1 BYTE ENABLES W-A W-DATA W BE IRDY# DEVSEL# TRDY# LOCK# <-- CAN BE DE-ASSERTED AFTER LAST DATA LCLK LHOLD LHOLDA ADS# BLAST# LA[31:2] LD[31:0] ADDR D0 +4 D1 +8 +12 +16 +20 D2 D3 D4 D5 +24 +28 +32 D6 D7 D8 W-ADDR READYi# LLOCKo# DE-ASSERTED AFTER DETECTING PCI UNLOCK -- Timing Diagram 8-29. (C Mode) Locked Direct Slave Read Followed by Write and Release (LLOCKo#) 136 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 8.2.2 C Mode Direct Master 0ns 100ns 200ns 300ns 400ns LCLK LA[31:2] LD[31:0] DATA 0 DATA 1 CS# ADS# LBE[3:0]# LW/R# BLAST# DP[3:0] DP0 DP1 READYo# First READYo# will be delayed at least five clocks for access to shared registers. Timing Diagram 8-30. (C Mode) Local Bus Read from PCI 9080 CFG Registers PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 137 Section 8 Timing Diagrams 0ns C Mode 100ns 200ns 300ns 400ns LCLK LA[31:2] LD[31:0] DATA 0 DATA 1 CS# ADS# LBE[3:0]# DATA 0 BYTE ENABLES DATA 1 BYTE ENABLES LW/R# BLAST# READYo# First READYo# will be delayed at least five clocks for access to shared registers Timing Diagram 8-31. (C Mode) Local Bus Write to PCI 9080 CFG Registers 138 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 100ns 200ns 300ns 400ns LCLK LA[31:2] A LW/R# ADS# BLAST# READYo# LD[31:0] LBE[3:0]# D0 LBE CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# A0 CMD D0 BE DEVSEL# IRDY# TRDY# Timing Diagram 8-32. (C Mode) Local Bus Direct Master Single Memory Read PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 139 Section 8 Timing Diagrams C Mode 0ns 100ns 200ns 300ns 400ns LCLK LA[31:2] A LW/R# ADS# BLAST# READYo# LD[31:0] LBE[3:0]# D0 LBE CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# A0 CMD D0 BE DEVSEL# IRDY# TRDY# Timing Diagram 8-33. (C Mode) Local Bus Direct Master Single Memory Write Cycle 140 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns LCLK LA[31:2] A LW/R# ADS# BLAST# READYo# LD[31:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# ADDR CMD D0 D4 D8 D12 D16 BE DEVSEL# IRDY# TRDY# Timing Diagram 8-34. (C Mode) PCI 9080 Direct Master Memory Read, 12 Lword Burst PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 141 Section 8 Timing Diagrams C Mode 0ns 250ns 500ns Left 750ns Center Right LCLK LA[31:2] LD[31:0] A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 LW/R# ADS# BLAST# READYo# CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# A CMD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 BE DEVSEL# IRDY# TRDY# Timing Diagram 8-35. (C Mode) PCI 9080 Direct Master Memory Write of 12 Lwords 142 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns LCLK LA[31:2] A LW/R# ADS# BLAST# READYo# LD[31:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 WAITI# CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# Timing Diagram 8-36. (C Mode) PCI 9080 Direct Master Memory Read with WAITI# PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 143 Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 75 LCLK LA[31:2] A LW/R# ADS# BLAST# READYo# LD[31:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 WAITI# CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# A CMD D7 D8 D9 D10 D11 BE DEVSEL# IRDY# TRDY# Timing Diagram 8-37. (C Mode) PCI 9080 Direct Master Memory Write with WAITI# 144 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns LCLK LA[31:2] LD[31:0] D1 LW/R# ADS# BLAST# READYo# CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# A0 D1 CMD 0 DEVSEL# IRDY# TRDY# Timing Diagram 8-38. (C Mode) PCI 9080 Direct Master Configuration Read--Type 1 or Type 0 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 145 Section 8 Timing Diagrams 0ns C Mode 250ns 500ns LCLK LA[31:2] LD[31:0] A D1 LW/R# ADS# BLAST# READYo# CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# A0 D0 CMD 0 DEVSEL# IRDY# TRDY# Timing Diagram 8-39. (C Mode) PCI 9080 Direct Master Configuration Write--Type 1 or Type 0 146 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns 1000ns 1250ns LCLK LA[31:2] A A LW/R# ADS# BLAST# READYo# LD[31:0] D0 D1 D2 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# A0 D0 0 A1 D1 A2 0 D2 0 DEVSEL# IRDY# TRDY# STOP# Timing Diagram 8-40. (C Mode) Local Bus Direct Master Read from PCI I/O PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 147 Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns 1000ns LCLK LA[31:2] A A+4 A+8 A+C LW/R# ADS# BLAST# READYo# LD[31:0] D0 D1 D2 D3 CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# A0 D0 0 A1 D1 A2 D2 0 0 A3 D3 CMD 0 DEVSEL# IRDY# TRDY# Timing Diagram 8-41. (C Mode) Direct Master Write to PCI I/O 148 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns 1000ns 1250ns 1500ns LCLK LA[31:2] A LD[31:0] LW/R# ADS# BLAST# READYo# WAITI# CLK REQ# GNT# FRAME# AD[31:0] A D0D1D2 C/BE[3:0]# DEVSEL# IRDY# De-assert IRDY# & Keep Bus TRDY# Timing Diagram 8-42. (C Mode) PCI 9080 Direct Master Memory Read--Keep Bus PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 149 Section 8 Timing Diagrams 0ns C Mode 250ns 500ns 750ns 1000ns 1250ns 1500ns LCLK LA[31:2] LD[31:0] ADDR LW/R# ADS# BLAST# READYo# WAITI# CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# Drop Bus TRDY# Timing Diagram 8-43. (C Mode) PCI 9080 Direct Master Memory Read--Drop Bus 150 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns LCLK 1 250ns 2 17 18 19 20 21 AD[31:0] RA D0 D1 D2 D3 C/BE[3:0]# CMD LA[31:2] 3 4 5 6 7 8 9 500ns 10 11 12 13 14 15 16 ADDR LD[31:0] D0 LBE[3:0]# D1 D2 D3 4 5 6 BE LW/R# ADS# BLAST# READYo# CLK 1 2 3 7 8 9 10 11 12 13 14 15 REQ# GNT# FRAME# BE DEVSEL# IRDY# TRDY# Timing Diagram 8-44. (C Mode) PCI Bus Request (REQ#) Delay During Direct Master Write (8 PCI Clock Delay) PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 151 Section 8 Timing Diagrams 0ns C Mode 250ns 500ns 750ns LCLK LA[31:2] ADDR LD[31:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 LW/R# ADS# BLAST# READYo# CLK REQ# GNT# FRAME# AD[31:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C/BE[3:0]# DEVSEL# IRDY# TRDY# Timing Diagram 8-45. (C Mode) Direct Master Memory Read, Prefetch of 16 152 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns 1000ns LCLK LA[31:2] LD[31:0] LW/R# ADS# BLAST# READYo# CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# Timing Diagram 8-46. (C Mode) Direct Master Memory Write and Invalidate (MWI)--Cache Line Size of 8 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 153 Section 8 Timing Diagrams C Mode 0ns 100ns 200ns 300ns 400ns 500ns LCLK LHOLD LHOLDA ADS# LW/R# BLAST# LA[31:2] ADDR 67452301 LD[31:0] READYi# CLK 1 2 3 4 5 6 7 8 9 10 11 12 FRAME# AD[31:0] ADDR C/BE[3:0]# CMD 01234567 BE IRDY# DEVSEL# TRDY# Timing Diagram 8-47. (C Mode) Direct Master in BIGEND Local Bus with BIGEND# Input or Interrupt 154 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns LCLK LA[31:2] LBE[3:0]# A BE 0 BE=3 BE=4 BE=8 BE=9 LD[31:0] D0 D1 D2 D3 D4 LW/R# ADS# BLAST# READYo# Direct Master Read - Does not pass Byte Enable CLK REQ# GNT# FRAME# AD[31:0] A0 C/BE[3:0]# CMD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 0 DEVSEL# IRDY# TRDY# Timing Diagram 8-48. (C Mode) Direct Master Burst, Memory Read Cycles (Changing LBE[3:0]#) PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 155 Section 8 Timing Diagrams C Mode 0ns 100ns 200ns 300ns 400ns 500n LCLK LA[31:2] A LD[31:0] D0 LBE[3:0]# BE=0 D1 D2 BE=F BE=0 D3 D4 BE=A BE=C LW/R# ADS# BLAST# READYo# Pass Byte Enable CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# A D0 D1 CMD BE=0 BE=F D2 BE=0 D3 D4 BE=A BE=C DEVSEL# IRDY# TRDY# Timing Diagram 8-49. (C Mode) Direct Master Five Lword Burst Write (Changing LBE[3:0]#) 156 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns LCLK LA[31:2] RA WA LW/R# UNLOCK --> LLOCK# <-- LOCK KEEP LOCK --> ADS# BLAST# READYo# LD[31:0] D0 WD CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# D0 D1 D2 D3 0 0 0 0 DEVSEL# IRDY# TRDY# LOCK# Timing Diagram 8-50. (C Mode) Direct Master Locked Read Followed by Write and Release (LLOCK# and LOCK#) PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 157 Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns CLK FRAME# DIRECT SLAVE READ AD[31:0] C/BE[3:0]# ADDR CMD D0 D1 D2 D3 BYTE ENABLES IRDY# DEVSEL# TRDY# DIRECT MASTER WILL NOT GAIN PCI BUS UNTIL DIRECT SLAVE ACCESS COMPLETES (GNT# ASSERTED , FRAME# DE-ASSERTED, IRDY# DE-ASSERTED) REQ# LCLK LHOLD <-- DIRECT SLAVE- BREQo TIMER STARTS LHOLDA DIRECT SLAVE PROCEEDS ADS# DIRECT MASTER READ LA[31:2] ADDR LD[31:0] READYo# D0 D1 D2 D3 NO DIRECT MASTER READY READYi# BREQo BREQo timer expires and asserts BREQo to indicate potential deadlock condition. External logic backs off Direct Master transfer and asserts LHOLDA to grant the Local Bus for a Direct Slave transfer. Note: For partial deadlock, PCI retry timer bits [31:28] of the Local Bus Region Descriptor Register can be used to issue RETRYs to the PCI Master attempting the Direct Slave access. Refer to Section 3, "Functional Description," for a description of deadlock. Timing Diagram 8-51. (C Mode) BREQo and Deadlock 158 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 8.2.3 C Mode DMA 0ns 250ns 500ns 750ns CLK FRAME# AD[31:0] C/BE[3:0]# ADDR D0 D1 D2 D3 D4 D5 D6 D7 CMD BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# LW/R# BLAST# LA[31:2] ADDR LD[31:0] D0 +4 +8 +C D1 D2 D3 +10 +14 +18 +1C D4 D5 D6 D7 READYi# BTERM# No wait states, 32-bit bus, Burst enabled, Bterm disabled. Timing Diagram 8-52. (C Mode) DMA Aligned PCI Address to Aligned Local Address, Bterm Disabled PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 159 Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns 1000ns CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# LCLK LA[31:2] LD[31:0] LW/R# ADS# BLAST# READYi# Timing Diagram 8-53. (C Mode) DMA Aligned Local Address to Aligned PCI Address, Burst Enabled, Bterm Enabled 160 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns CLK 250ns 1 2 3 4 5 6 7 500ns 750ns 8 FRAME# AD[31:0] C/BE[3:0]# ADDR CMD DO D1 D2 D3 D4 BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# BLAST# LW/R# LA[31:2] ADDR LD[31:0] D0 D1 D2 D3 D4 READYi# Five Lwords, one wait state, Bterm enabled. Timing Diagram 8-54. (C Mode) DMA Aligned PCI Address to Aligned Local Address (External Generation of Wait States) PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 161 Section 8 Timing Diagrams C Mode 0ns 495ns 990ns 1485ns 1980ns CLK Reading from the Descriptor FRAME# AD[31:0] C/BE[3:0]# A D0 D1 D2 D3 A1 d0 d1 d2 d3 BE A2d1 d2 BE Local to PCI Transfer IRDY# Two wait states DEVSEL# TRDY# Local to PCI transfer LCLK LHOLD LHOLDA ADS# BLAST# LA[31:2] LD[31:0] A +4 +8 +12+16 d0 d1 d2 d3 D1 D0 D1 D2 D3 d1 d2 LW/R# READYi# Timing Diagram 8-55. (C Mode) Read of DMA Chaining Parameters from PCI and Local Buses 162 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 100ns 200ns 300ns 400ns 500ns LCLK LHOLD <--- PCI 9080 DRIVES BUS LHOLDA ADS# BLAST# LBE[3:0]# LBE LW/R# LA[31:2] ADDR LD[31:0] D0 D1 D2 D3 DT/R# DEN# READYi# First Address A are bits [31:4] of next Descriptor Pointer Register. D0: PCI start address D1: Local start address D2: Transfer count (bytes) D3: Next descriptor pointer Timing Diagram 8-56. (C Mode) PCI 9080 DMA Read of Chaining Parameters from Local Bus, No Wait States PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 163 Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns CLK Reading from the Descriptor FRAME# AD[31:0] C/BE[3:0]# D0 D1 D2 d0 D3 BE CMD d1 d2 d3 BE Local to PCI Transfer Two wait states IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# BLAST# LA[31:2] +4 +8 LD[31:0] d0 d1 d2 +12 +16 d3 LW/R# READYi# Timing Diagram 8-57. (C Mode) Read of DMA Chaining Parameters from PCI Bus (Local-to-PCI Transfer) 164 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 100ns 200ns 300ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LD[31:0] D0 LA[31:2] A DREQ[1:0]# MUST BE DE-ASSERTED TO PREVENT BURST ------------------------------> DREQ[1:0]# DACK[1:0]# READYi# No wait states. Timing Diagram 8-58. (C Mode) Single Cycle DMA Demand Mode PCI-to-Local 0ns 100ns 200ns 300ns 400ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LD[31:0] D0 LA[31:2] A D1 A+4 CURRENT DATA + LAST DATA TRANSFERRED AFTER DREQ[1:0]# IS DE-ASSERTED DREQ[1:0]# No wait states, Burst enabled, Bterm enabled, 32-bit Local Bus. Timing Diagram 8-59. (C Mode) Multiple Cycle (Burst) DMA Demand Mode PCI-to-Local, No Wait States PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 165 Section 8 Timing Diagrams 0ns C Mode 50ns 100ns 150ns 200ns 250ns 300ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LD[31:0] LA[31:2] DREQ[1:0]# D0 A D1 A+4 DREQ[1:0]# MUST BE DE-ASSERTED WHEN BLAST# IS DE-ASSERTED DACK[1:0]# READYi# No wait states, Burst enabled, Bterm enabled, 32-bit Local Bus. Timing Diagram 8-60. (C Mode) DMA Demand Mode Terminated with BLAST# (Local-to-PCI) 166 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns CLK FRAME# AD[31:0] ADDR C/BE[3:0]# CMD D0 D1 D2 D3 D4 D5 BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# BLAST# LA[31:2] ADDR LD[31:0] D0 +4 D1 +8 +C +10 +14 D2 D3 D4 D5 +18 LW/R# READYi# EOT[1:0]# Stop Data Transfer Mode bit is not set. If this bit is set, there is no BLAST# and D5 is not transferred. See Table 4-62[15] or Table 4-67[15]. Timing Diagram 8-61. (C Mode) DMA Local-to-PCI, Terminated with EOT[1:0]# PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 167 Section 8 Timing Diagrams C Mode 0ns 250ns 500ns CLK FRAME# AD[31:0] C/BE[3:0]# ADDR CMD D0 D1 D2 D3 D4 D5 D6 D7 BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# BLAST# LA[31:2] ADDR LD[31:0] D0 +4 +8 D1 LW/R# READYi# EOT[1:0]# Stop Data Transfer Mode bit is not set. If this bit is set, there is no BLAST# and D1 is not transferred. See Table 4-62[15] or Table 4-67[15]. Timing Diagram 8-62. (C Mode) DMA PCI-to-Local, Terminated with EOT[1:0]# 168 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams C Mode 0ns 250ns 500ns 750ns CLK FRAME# AD[31:0] ADDR C/BE[3:0]# CMD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# LW/R# BLAST# LA[31:2] LD[31:0] D0 +4 +8 +C +10 +14 +18 +1C D1 D2 D3 D4 D7 D5 D6 +20 D8 READYi# Local Latency Timer = 7 CLK, Local Pause Timer = 4 CLK. PCI 9080 has internally added another clock to the Local Pause Timer. Local Latency Timer starts after ADS# is active. Local Pause Timer starts after LHOLDA is de-asserted. Timing Diagram 8-63. (C Mode) DMA PCI-to-Local with Local Pause Timer and Local Latency Timer PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 169 Section 8 Timing Diagrams J Mode 8.3 J Mode 8.3.1 J Mode Direct Slave 0ns 100ns 200ns 300ns 400ns 500ns LCLK LHOLD LHOLDA LDSHOLD ADS# ALE BLAST# LBE[3:0]# DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS# LW/R# LAD[31:0] LABS[3:2] A D0 00 D1 01 D2 10 D3 11 D4 00 A+14 01 D5 D6 10 D7 11 DT/R# DEN# BTERM# READYi# Eight Lword burst, no wait states, Burst enabled, Bterm enabled, 32-bit Local Bus. Note: If Bterm is disabled, a new ADS# cycle starts every quad Lword boundary. BTERM# replaces READYi# when asserted. Timing Diagram 8-64. (J Mode) PCI 9080 Direct Slave Burst Read from Local Bus, No Wait States, Bterm Enabled 170 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams J Mode 0ns 100ns 200ns 300ns 400ns 500ns LCLK LHOLD LHOLDA LDSHOLD ADS# ALE BLAST# LBE[3:0]# DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS# LW/R# LAD[31:0] A LABS[3:2] D0 LAD[3:2] D1 D2 D3 D4 A+14 D5 D6 D7 LAD[3:2] DT/R# DEN# BTERM# READYi# Eight Lword burst, no wait states, Burst enabled, Bterm enabled, 32-bit Local Bus. Note: If Bterm is disabled, a new ADS# cycle starts every quad Lword boundary. BTERM# replaces READYi# when asserted. Timing Diagram 8-65. (J Mode) PCI 9080 Direct Slave Burst Write to Local Bus, No Wait States, Bterm Enabled PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 171 Section 8 Timing Diagrams J Mode 0ns 250ns 500ns LCLK LHOLD LHOLDA ADS# ALE BLAST# LBE[3:0]# DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS# LW/R# LAD[31:0] A LABS[3:2] 00 D0 D1 01 D2 10 D3 11 A+10 00 D4 D5 D6 D7 01 10 11 DT/R# DEN# BTERM# READYi# Eight Lword burst, no wait states, Burst enabled, Bterm disabled, 32-bit Local Bus. Note: If Bterm is disabled, a new ADS# cycle starts every quad Lword boundary. Timing Diagram 8-66. (J Mode) PCI 9080 DMA or Direct Slave Burst Write to Local Bus, No Wait States, Bterm Disabled 172 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams J Mode 0ns CLK 100ns 4 200ns 300ns 400ns 500ns FRAME# AD[31:0] C/BE[3:0]# ADDR Data= AABBCCDD CMD 01234567 BE IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA LDSHOLD ADS# ALE LW/R# BLAST# LAD[31:0] ADDR 67452301 READYi# Timing Diagram 8-67. (J Mode) Direct Slave in BIGEND Local Bus with BIGEND# Input or Internal Register Setting PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 173 Section 8 Timing Diagrams J Mode 0ns 250ns 500ns 750ns 1000ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# PERR# RETRY RETRY STOP# Delayed Read Retries WRITE IS NOT ALLOWED DURING DELAYED READ READS DATA WRITE RETRIES AND COMPLETES LCLK LHOLD LHOLDA LDSHOLD ADS# ALE BLAST# LAD[31:0] LBE[3:0]# READYi# DTR# DEN# LW/R# Disconnect immediately for a read. Don't effect pending reads when a write cycle occurs. Don't flush Read FIFO if PCI read cycle completes. Force Retry on write if read pending. De-assert TRDY# until space is available in Direct Slave Write FIFO. Timing Diagram 8-68. (J Mode) Direct Slave Read v2.1 Spec 174 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams J Mode 0ns 250ns 500ns 750ns 1000ns CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# Single Cycle Burst Cycle TRDY# LCLK LHOLD LHOLDA LDSHOLD ADS# ALE BLAST# LAD[31:0] LBE[3:0]# LBE LRDYi# LW/R# DTR# DEN# Timing Diagram 8-69. (J Mode) Direct Slave Read No Flush Mode (Read Ahead Mode), Prefetch Mode Enabled PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 175 Section 8 Timing Diagrams J Mode 0ns 100ns 200ns 300ns 400ns LCLK LA[31:2] A D D CS# ADS# LBE[3:0]# LW/R# BLAST# DP[3:0] DP0 DP1 READYo# Could take more than five local clocks for PCI 9080 to assert READYo#. Timing Diagram 8-70. (J Mode) Local Bus Read from PCI 9080 CFG Registers 0ns 100ns 200ns 300ns 400ns LCLK LA[31:2] A D D CS# ADS# LBE[3:0]# DATA 0 BYTE ENABLES DATA 1 BYTE ENABLES LW/R# BLAST# READYo# Could take more than five local clocks for PCI 9080 to assert READYo#. Timing Diagram 8-71. (J Mode) Local Bus Write to PCI 9080 CFG Registers 176 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams J Mode 8.3.2 J Mode Direct Master 0ns 250ns 500ns 750ns 1000ns LCLK LAD[31:0] LW/R# ADS# BLAST# READYo# CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# Unused D12-D16 are flushed from FIFO. Timing Diagram 8-72. (J Mode) Direct Master Read Access from PCI Bus (Keep PCI Bus If Read FIFO Full Mode), No PCI Disconnects PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 177 Section 8 Timing Diagrams J Mode 0ns 250ns 500ns 750ns LCLK <--- LOCAL ADDRESS MATCHES LOCAL DIRECT MASTER BASE ADDRESS LAD[31:0] LBE[3:0]# ALL LBE[3:0]# = 0000, SEPARATE ADS#/DATA CYCLE FOR PARTIALS WITH LOCAL PROCESSOR LW/R# ADS# BLAST# READYo# CLK REQ# GNT# FRAME# REMAPPED A --> AD[31:0] C/BE[3:0]# D10 D11 D12 D13 D14 D15 DEVSEL# IRDY# TRDY# Timing Diagram 8-73. (J Mode) Local Bus Direct Master Burst Write Access to PCI Bus, Continuous If Same Clock Rate and No PCI Disconnects 178 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams J Mode 0ns 250ns 500ns 750ns LCLK LAD[31:0] RA D0 WA WD LW/R# KEEP LOCK --> LLOCK# UNLOCK --> <-- LOCK ADS# DEN# BLAST# READYo# CLK REQ# GNT# FRAME# AD[31:0] R-RA C/BE[3:0]# CMD D0 0 D1 D2 D3 0 0 0 WD DEVSEL# IRDY# TRDY# LOCK# One Lword burst (Pre-Read Four mode). Timing Diagram 8-74. (J Mode) Local Bus Direct Master Lock Memory Read Access from PCI Bus Followed by Write and Release PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 179 Section 8 Timing Diagrams J Mode 8.3.3 J Mode DMA 0ns 250ns 500ns LCLK LHOLD LHOLDA ADS# ALE BLAST# LBE[3:0]# DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS# LW/R# LAD[31:0] LABS[3:2] A 00 D0 D1 01 D2 10 D3 11 D4 00 A+14 01 D5 D6 10 D7 11 DT/R# DEN# BTERM# READYi# Eight Lword burst, no wait states, Burst enabled, Bterm enabled, 32-bit Local Bus. Note: If Bterm is disabled, a new ADS# Cycle starts every quad Lword boundary. Timing Diagram 8-75. (J Mode) PCI 9080 DMA Local-to-PCI, No Wait States, Bterm Enabled 180 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams J Mode 0ns 100ns 200ns 300ns 400ns 500ns LCLK LHOLD LHOLDA ADS# ALE BLAST# LBE[3:0]# DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS# LW/R# LAD[31:0] A LABS[3:2] LAD[3:2] D0 D1 D2 D3 D4 A+14 D5 D6 D7 LAD[3:2] DT/R# DEN# BTERM# READYi# Eight Lword burst, no wait states, Burst enabled, Bterm enabled, 32-bit Local Bus. Note: If Bterm is disabled, a new ADS# cycle starts every quad Lword boundary. Timing Diagram 8-76. (J Mode) PCI 9080 DMA PCI-to-Local Bus, No Wait States, Bterm Enabled PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 181 Section 8 Timing Diagrams 0ns J Mode 100ns 200ns 300ns 400ns 500ns LCLK LHOLD LHOLDA ADS# ALE BLAST# LBE[3:0]# ALL ZERO LW/R# LAD[31:0] A D0 A+4 D1 A+8 D2 A+C D3 DT/R# DEN# READYi# First Address A are bits [31:4] of next Descriptor Pointer Register. D0: PCI start address D1: Local start address D2: Transfer count (bytes) D3: Next descriptor pointer Timing Diagram 8-77. (J Mode) DMA Read of Chaining Parameters, No Wait States 182 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams J Mode 0ns 250ns 500ns LCLK LHOLD LHOLDA ADS# ALE BLAST# LBE[3:0]# DOES NOT CHANGE, UNALIGNED HAS OWN CYCLE WITH ADS# LW/R# LAD[31:0] LABS[3:2] A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 A Data LAD[3:2] DT/R# DEN# BTERM# READYi# BREQ Give up local bus when programmable BREQ is asserted Owned by local bus or another bus master DMA continues from where it left off DMA burst suspended by BREQ. No wait states, Burst enabled, Bterm enabled, 32-bit Local Bus. Timing Diagram 8-78. (J Mode) PCI 9080 Write to Local Bus BREQ Asserted PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 183 Section 8 Timing Diagrams S Mode 8.4 S Mode 0ns 100ns 200ns 300ns 400ns A LCLK (Internal) LCLK LHOLD LHOLDA AS# BLAST# LA[31:16] A A+4 A+8 A+c LBE[1:0]# LABS[3:1] LAD[16:1] A A [15:0] A+2 A+4 [31:16] [15:0] A+6 A+8 A+a [31:16] [15:0] [31:16] A+c [15:0] A+e [31:16] BTERM# READYi# . Local clock is twice frequency. Timing Diagram 8-79. (S Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 16-Bit Local Bus, No Wait States, Bterm Enabled 184 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved Section 8 Timing Diagrams S Mode 0ns 50ns 100ns 150ns 200ns 250ns Local Bus A B C D LCLK LA[31:16] LAD[15:1] LABS[3:1] ADDR ADDR DATA 0 START WORD ADDR DATA 1 NEXT WORD ADDR CS OR LA[31:29] MATCH S[2:0] CS# AS# LBE[1:0]# LW/R# BLAST# DP[3:0] DP0 DP1 READYo# Local clock is twice frequency. Timing Diagram 8-80. (S Mode) Local Bus Read from PCI 9080 CFG Registers PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved 185 Section 8 Timing Diagrams S Mode 0ns 50ns 100ns 150ns 200ns 250ns Local Bus A B C D CLK LA[31:16] ADDR LAD[15,1] ADDR LABS[3:1] ADDR LABS1 DATA 0 START WORD ADDR DATA 1 NEXT WORD ADDR CS# CS OR LA[31:29] MATCH S[2:0] AS# LBE[1:0]# BYTE ENABLES FOR DATA WORD 0 BYTE ENABLES FOR DATA WORD 1 LW/R# BLAST# READYo# PCHK# PCHK0 PCHK1 Local Bus clock is twice frequency. Timing Diagram 8-81. (S Mode) Local Bus Write to PCI 9080 CFG Registers Xyz 186 PCI 9080 Data Book v1.06 PLX Technology, Inc. All rights reserved PCI 9080-3 Errata Rev. 1.3 April 2001 A. Product Status Product PCI 9080 Revision Version 03 Samples October 1997 Production January 1998 B. Documentation Status Document Data Book Revision Version 1.06 Description PCI 9080 Data Book Date January 2000 C. Errata: 1. EOTx# Pin Usage Problem: The use of EOTx# to terminate ongoing DMA transfers may result in corrupted data being transferred across the chip, premature indication of FIFO empty via "DMA Done Bit", or may cause PCI 9080 to perform an invalid read cycle in place of the Write Back cycle. This is true for aligned and unaligned transfers, and for local to PCI and PCI to local transfers. Solution/Workaround: 1. Use the DMA engines in demand mode. Use the DREQ# pin to pause ongoing DMA transactions. DMA abort can then be used to terminate the pending transfers once the DMA channel has paused. 2. Write to DMA control registers to pause ongoing DMA transfers. Use DMA abort to terminate the DMA transfer. 3. Use of DMA when transferring to and from 32-bit buses must follow these conditions: a. The starting addresses on both the PCI and local sides must be 32-bit aligned. b. The transfer count must also be in 32-bit multiples. c. The transfers must not be in Memory Write and Invalidate or in Clear Count modes. 4. Synchronize the PCI clock with the Local clock by using the inverted version of the BCLKo signal to drive LCLK. The inverter should have a propagation delay of less than 5ns. Document number: 9080-SIL-ER-P0-1.3 -1- 2. LLOCKo# (Local Lock output) assertions with Direct Slave Reads Problem: After the first Direct Slave Read transaction, subsequent Direct Slave Reads will cause the LLOCKo# signal to assert with the LHOLD signal. The PCI 9080 will act as if the two lines are shorted together. This has the consequence of locking the local processor every time. Solutions/Workarounds: 1. Execute a Direct Slave Write cycle before any Direct Slave Reads. A Direct Slave Write cycle sets the internal state machine such that any number of subsequent Direct Slave Reads will not activate the LLOCKo# bug. 2. Disconnect use of the LLOCKo# pin. 3. Demand Mode DMA in Stop Transfer Mode Problem: This update only applies to Demand Mode DMA transfers when the Stop Transfer bit (DMAMODEx[15]) is active. If DREQ# is negated before all data transfers are complete (pausing the DMA), subsequent assertions of DREQ# will fail to transfer the last long word of the intended transfers. Furthermore, if chaining DMA is active, the PCI 9080 will fail to read the descriptor of the following link in the chain. Solution/Workaround: 1. Always specify one extra long word to be transferred when attempting to pause demand mode transfers using DREQ#. 2. Do not negate DREQ# until all intended transfers are complete. 3. Pause the DMA transfer by writing to the channel Enable bit rather than by using demand mode. 4. Pause the DMA without the stop transfer bit enabled. 4. Unaligned DMA In Big Endian Mode Problem: Unaligned DMA cycles in Big Endian Mode may result in corrupted data being sent across the device. Solution/Workaround: (Convention: Local device refers to device that uses big endian byte ordering.) Document number: 9080-SIL-ER-P0-1.3 -2- 1. To interface PCI 9080 to a Big Endian device on the local bus, disable the Big Endian feature in the PCI 9080 and connect the data bits [0:31] of the local device directly to the data bit [0:31] of the local bus and PCI 9080. Therefore, long word transfers are compatible between the two domains. If the local device writes a byte to address 0, the data appears on bits [24:31] and LBE3# to the PCI 9080 is asserted. This corresponds to byte address 3 on the PCI bus. If byte or word transfers to PCI 9080 are performed, then the local device software must map the address so that the data appears on the correct byte lane. Also, if byte or word data structures are shared by the local device and other PCI Little Endian devices, then address mapping in the software must be included. 2. Swap the byte lanes when connecting the local device to the PCI 9080 local bus. In this case byte addressing is compatible, but word and long word addressing is not. 5. Direct Slave Non-PCI 2.1, Cache, Write Flush mode Problem: If the PCI 9080 Local/DMA arbitration register is set for Non-PCI 2.1 mode (bit 24 = 0), Cache mode enabled (bit 28 = 1, no Flush mode), Write Flushes Read mode off (bit 26 = 0), a write will cause the local bus to stop reading data. The local bus never resumes reading data, causing all read attempts to be retried on the PCI bus. Solutions/Workarounds: (any or all) 1. Set the PCI9080 to operate in PCI 2.1 mode. (Set Local/DMA arbitration register bit 24 = 1). 2. Do not use Cache mode (Set Local/DMA arbitration register bit 28 = 0, Write Flushes Cache mode). 3. Set the PCI 9080 to operate in PCI Read with Write Flush mode on. (Set Local/DMA arbitration register bit 26=1). 6. Direct Master Burst Read past a 64K boundary Problem: This erratum prevents the 9080 from prefetching read data past a 64K boundary (low 16 bits of the PCI address). This implies that a Direct Master read must not request burst data past this boundary. If it does, the PCI 9080 will hang the local bus at the boundary, refusing to gather any further data. Document number: 9080-SIL-ER-P0-1.3 -3- Solution/Workaround: This 64K boundary is not a hard wall. It can be crossed in 2 separate cycles. It only cannot be crossed in a single burst cycle. Any of the following solutions may be implemented: 1. Break all Direct Master burst reads at 64K boundaries. Separating bursts across the boundary into 2 separate bursts will work just fine. 2. Break all Direct Master burst reads at 4, 16, or 32K boundaries. While this places even more restrictions on the requesting device, it may be easier to implement than the 64K boundary. (The PCI 9080 provides an option bit that prevents prefetching past 4K boundaries). 3. The 64K boundary can be crossed if the local master only reads in single cycles. 7. Simultaneous PCI DMA Descriptor read with local access to internal registers Problem: If the PCI 9080 encounters a PCI target retry when attempting to read a DMA descriptor from the PCI bus, the PCI 9080 will retry the read after a few clocks. A local read of the PCI 9080's internal configuration registers coincident with this retried descriptor read will result in the local initiator receiving data from the DMA descriptor register for which the descriptor is being read. A local write to configuration registers synchronous to this descriptor read will receive a READYo# from the 9080 even though the write never gets through. (The write data never actually goes anywhere.) Solution/Workaround 1: 1. On local reads, if the value returned is the same as the DMA configuration register, reread the internal register. 2. Read or write to the internal registers twice and compare the values. 8. Aborting chained DMA with descriptors on both PCI and local buses Problem: The PCI 9080 has 2 independent DMA controllers that support chaining DMA with their descriptors located on either the PCI or local buses. This makes it possible for one DMA channel to have descriptors on the PCI bus while the other channel has descriptors on the local bus. If a DMA channel is aborted while doing local to PCI transfers and the local bus is running faster than the PCI bus, a subsequent DMA Local-to-PCI transfer will result in incorrect data being transferred across the PCI 9080 (when both channels are active with descriptors on both sides of the bus). Document number: 9080-SIL-ER-P0-1.3 -4- Solution/Workaround: Follow the DMA abort with a DMA PCI-to-Local transfer (on the aborted channel) of zero bytes. This will reset the internal state machines for subsequent local to PCI transfers. 9. Delayed read during 32K PCI clocks timeout Problem: As per the PCI Specification, when a master performs a delayed read, it must complete that delayed read. When a delayed read is not completed within 32K PCI clocks, the target with the pending delayed read should discard it (protect against violations or PCI 2.0 devices). There is a 1 clock window (last clock of 32K timeout) in which the PCI 9080 is discarding the delayed read. During this 1 clock window, new PCI cycles are not monitored. If a new PCI cycle is begun during that 1 clock window, the PCI 9080 ignores the PCI cycle. Therefore, a Master Abort will occur on the PCI bus. Solution/Workaround: This is an extremely rare occurrence. If you encounter it, software should recover both the timeout and Master Abort with a retry. 10. LOCK# negation during an idle phase This errata was previously published. However, it has since been determined to not be an issue in the PCI 9080-3, and therefore this erratum is retracted. 11. DMA Channel 0 Almost Full Threshold value of zero with Local-to-PCI transfers Problem: During a DMA channel 0 Local to PCI transfer, DMA Channel 0 uses the Almost Full Threshold register bits (DMATHR[11:8]) to determine when the PCI 9080 should request the PCI bus to send out the data in its FIFO. If the threshold is set to 0 and if only 1 word (or less) of data is in the FIFO, it will be left there and not be sent out to the PCI bus. This can only happen when Demand mode is used to transfer only 1 word to the PCI side at a time. If this 1 word is the last word of a DMA transfer, the thresholds will be ignored and the data will still go through. This problem does not apply to DMA Channel 1. Solutions / Workarounds: (use any) 1. Do not use DMA channel 0 Demand mode to transfer a single word at a time. Use standard block mode or chaining DMA with a byte count of four to effect the transfers instead. 2. Set the Almost Full Threshold to a non-zero value. Document number: 9080-SIL-ER-P0-1.3 -5- 12. Direct Slave Read Retry Problem: Direct Slave Writes are posted into a FIFO followed by a single PCI 2.1 deferred Direct Slave Read and more Direct Slave Writes. Any posted Direct Slave Writes after a pending Direct Slave Read will cause the read data never to be prefetched into a read FIFO. This condition will cause any subsequent Direct Slave Reads to be retried indefinitely. All subsequent Direct Slave Writes are unaffected and execute as expected. PCI Specification v2.1 Mode bit is enabled and the PCI Read with Write Flush Mode bit is disabled. Solution/Workaround 1: 1. Enable the Retry Writes when reads are pending bit in MARBR[25]. 2. Do not post writes after a pending read when PCI 9080 does not own the Local Bus. 3. Disable the PCI Specification v2.1 mode bit in the MARBR[24]. 13. Direct Slave Prefetch Burst Read over the Space Boundary Problem: If a Direct Slave prefetch Read transaction is performed over the defined Space boundary, the Local bus may hang by posting a wrong address during the prefetch read cycle. This is due to the fact that the PCI 9080 performs an automatic increment of the address during prefetch Read. Solution/Workaround 1: 1. If crossing a Space boundary is required during a Direct Slave Read, the Space prefetch counter should be set to 4 Lwords and the starting address should be quad-word aligned. 2. Disable Bterm mode for the address space in LBRDx[7]. Both solutions will guarantee a new address cycle and proper address value(s) to appear on the Local bus when the defined Space boundary is crossed. 14. PCI Target Abort during DMA Transfer This issue was previously published as an erratum. However, it has since been determined to be compliant with the PCI Specification, and therefore this erratum is retracted. The text for this issue has been relocated to PCI 9080 Design Note #10. Document number: 9080-SIL-ER-P0-1.3 -6- 15. Local Bus timing analysis did not include clock skew delay (max of 0.5ns). The PCI 9080 Local Bus timing analysis did not include the clock skew delay (max of 0.5ns). This affects the hold time requirement for LHOLDA and potentially the rest of the local bus pins. For example, the PCI 9080 Data Book shows 2.0ns hold time for LHOLDA but the actual number is 2.5ns. This causes the PCI 9080 to start the local bus cycle without ADS# if hold time is violated. Below is the AC Electrical Characteristics for Local Inputs, with the corrected times, that include the clock skew delay of 0.5ns max. Times that differ from the PCI 9080 Data Book, version 1.06, page 103, section 6.2 titled Local Inputs, are printed in boldface. AC Electrical Characteristics (Local Inputs) Estimated over Operating Range Signal ADS# BIGEND# BLAST# BREQI BTERM# DP[3:0] DREQ[1:0]# EOT0# EOT1# LA[31:0] LAD[31:0] LBE[3:0]# LD[31:0] LHOLDA LINTI LLOCK LW/R# READYI# S[2:0] USERI WAIT# Old Tsetup(ns) 6 4 6 7 7 4 3 7 1 5 5 7 5 7 7 4 9 8 1 4 13 New Tsetup (ns) 6 4 6 7 7 4 3 7 1 5 5 7 5 7 7 4 9 8 1 4 13 Old Thold (ns) 1 0 0 0 1 0 1 1 1 0 0 0 0 2 0 0 0 1 2 0 0 New Thold (ns) 2.01 0 0 0 1.5 0 1.5 1.5 1.5 0 1.69 1.25 0 2.5 0 0 0 1.5 2.5 0 0 Document number: 9080-SIL-ER-P0-1.3 -7- Below is the AC Electrical Characteristics for Local Outputs, with the corrected times, that include the clock skew delay of 0.5ns max. Times that differ from the PCI 9080 Data Book version 1.06, page 104, section 6.3 titled Local Outputs, are printed in boldface. AC Electrical Characteristics (Local Outputs) Estimate over Operating Range Signal ADS# BLAST# BREQO BTERMO# DACK[1:0]# DEN# DMPAF# DP[3:0] DT/R# LA[31:2] (C Mode) LABS[3:1] LAD[31:0] (Address, J Mode) LAD[31:0] (Data, J Mode) LD[31:0] (32- and 16-Bit, C Mode) LD[31:0] (8-bit C Mode) LBE[3:0]# LDSHOLD LHOLD LINTO# LLOCKO# LSERR# LW/R# PCHK# READYO# USERO WAITO# Old Output Tvalid (max) 14.5 16 13 15 14 13 17 20 14 15.8 12 12.1 15 15 20 16 12 13 13 12 12 14 12 14 11 18 New Output Tvalid (max) 15.0 16 13 15 14 13 17 20 14 16.3 12 12.6 15 15 20 16 12 13 13 12 12 14 12 14 11 18 Copyright a 2001 by PLX Technology, Inc. All rights reserved. PLX is a trademark of PLX Technology, Inc. which may be registered in some jurisdictions. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology reserves the right, without notice, to make changes in product design or specification. Document number: 9080-SIL-ER-P0-1.3 -8-