PJESDZ6V8-2G
E.S.D. Dual Protection Diode Array
SPECIFICATION FEATURES
APPLICATIONS
MAXIMUM RATINGS (Per Device)
Rating Symbol Value Units
This Dual Unidirectional ESD Protector Array family have been designed to protect
sensitive equipment against ESD in high speed transmission buses, operating at
5V. This dual array offers an integrated solution to protect up to
2 data lines in a unidirectional mode or, 1 data line in a bi-directional mode, in
application where the board space is a premium, in our SOT523 package
version.
Peak Power Dissipation of 20W 8/20µs Waveform
Low Leakage Current, Maximum of 0.5µA at rated voltage
IEC61000-4-2 ESD 15kV air, 8kV Contact Compliance
Maximum Capacitance of 10pF per device at 0Vdc 1MHz
Mobile Phones
Digital Cameras
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C
Parameter Symbol Min Unit
s
Conditions Typical Max
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Off State Junction Capacitance*
VWRM
VBR
IR
c
V
Cj
BR
I =
R
V =
I =
pp
0 Vdc Bias f = 1MHz
between pin 1, 2 to 3 (Gnd)
5.0 V
6.2 7.2 V
µA0.5
10 V
910 pF
1mA
5V
2A
20
2
20
-55 to +125
W
A
kV
°C
Peak Pulse Power (8/20µs Waveform)
ESD Voltage (HBM Per MIL STD883C - Method 3015-6)
Operating Temperature Range
PPP
VESD
TJ
Tstg
12/9/2008 Page 1www.panjit.com
Pin to pin compatible with standard SOT523
Notebooks PC's
Storage Temperature Range
Lead Free Package 100% Tin Plating, Matte finish
°C
-55 to +150
Peak Pulse Current (8/20µs Waveform) IPPM
2
1
3
PANJIT SOT523
3
12
Low profile, Max height of 0.55mm
* Capacitance between pins 1 and 2 is half of the value, in a bi-directional configuration.
Pulse Waveform
0
10
20
30
40
50
60
70
80
90
100
110
0 5 10 15 20 25 30
ti me, µsec
Percent of Ipp
50% of Ipp @ 20µs
Rise time 1 0-90% - 8µs
6.5
7
7.5
8
8.5
9
9.5
00.511.52
Peak Current, A 8/20µ s
Clamping Voltage, V
4
5
6
7
8
9
10
012345
Vdc Bias, V
Junction Capacitnace, pF
www.panjit.com
PJESDZ6V8-2G
12/9/2008 Page 2
TYPICAL CHARACTERISTIC CURVES (Per Device) Tj = 25°C
Clamping Voltage vs 8/20µs Ipp
Off-State Capacitance vs DC Bias
12/9/2008 Page 3 www.panjit.com
PACKAGE DIMENSIONS AND SUGGESTED PAD LAYOUT
PJESDZ6V8-2G
