© Semiconductor Components Industries, LLC, 2007
August, 2007 - Rev. 7
1Publication Order Number:
MC100LVELT22/D
MC100LVELT22
3.3V Dual LVTTL/LVCMOS
to Differential LVPECL
Translator
Description
The MC100LVELT22 is a dual LVTTL/LVCMOS to differential
LVPECL translator. Because LVPECL (Low Voltage Positive ECL)
levels are used, only +3.3 V and ground are required. The small outline
8‐lead package and the low skew, dual gate design of the LVELT22
makes it ideal for applications which require the translation of a clock
and a data signal.
Features
•350 ps Typical Propagation Delay
•<100 ps Output-to-Output Skew
•Flow Through Pinouts
•The 100 Series Contains Temperature Compensation
•LVPECL Operating Range: VCC = 3.0 V to 3.8 V
with GND = 0 V
•When Unused TTL Input is left Open, Q Output will Default High
•Pb-Free Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAMS*
KR22
ALYWG
G
SOIC-8
D SUFFIX
CASE 751
1
8
TSSOP-8
DT SUFFIX
CASE 948R
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
KVT22
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
4I M G
G
14
(Note: Microdot may be in either location)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M= Date Code
G= Pb-Free Package
MC100LVELT22
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2
1
2
3
45
6
7
8
D0
GND
VCC
Q0
D1Q1
Q1
Q0
LVPECL LVTTL/
LVCMOS
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
PIN FUNCTION
Table 1. PIN DESCRIPTION
Qn, Qn LVPECL Differential Outputs
D0, D1 LVTTL/LVCMOS Inputs
VCC Positive Supply
GND Ground
EP Exposed pad must be connected
to a sufficient thermal conduit.
Electrically connect to the most
negative supply or leave floating
open.
EP
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor N/A
Internal Input Pullup Resistor N/A
ESD Protection Human Body Model
Machine Model
> 4 kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in
Transistor Count 164
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Positive Power Supply GND = 0 V 7 V
VIInput Voltage GND = 0 V VI VCC 7 V
Iout Output Current Continuous
Surge
50
100
mA
mA
TAOperating Temperature Range -40 to +85 °C
Tstg Storage Temperature Range -65 to +150 °C
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SO-8
SO-8
190
130
°C/W
°C/W
qJC Thermal Resistance (Junction-to-Case) std bd SO-8 41 to 44 ± 5% °C/W
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP-8
TSSOP-8
185
140
°C/W
°C/W
qJC Thermal Resistance (Junction-to-Case) std bd TSSOP-8 41 to 44 ± 5% °C/W
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol Wave Solder Pb
Pb-Free
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
MC100LVELT22
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3
Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V (Note 2)
-40 °C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
ICC Power Supply Current 28 28 29 mA
VOH Output HIGH Voltage (Note 3) 2275 2420 2275 2420 2275 2420 mV
VOL Output LOW Voltage (Note 3) 1490 1680 1490 1680 1490 1680 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Output parameters vary 1:1 with VCC. VCC can vary ±0.15 V.
3. Outputs are terminated through a 50 ohm resistor to VCC-2 volts.
Table 5. LVTTL/LVCMOS INPUT DC CHARACTERISTICS VCC = 3.3 V; TA = -40°C to 85°C (Note 4)
Symbol Characteristic Min Typ Max Unit Condition
IIH Input HIGH Current 20 mAVIN = 2.7 V
IIHH Input HIGH Current 100 mAVIN = VCC
IIL Input LOW Current -0.2 mA VIN = 0.5 V
VIK -1.2 V IIN = -18 mA
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. VCC can vary ±0.15 V.
Table 6. AC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V (Note 5)
-40 °C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
fmax Maximum Toggle Frequency 350 MHz
tPLH Propagation Delay (Note 6) 200 350 600 200 350 600 200 350 600 ps
tskew Skew Output-to-Output
Part-to-Part
30 100
400
30 100
400
30 100
400
ps
tJITTER Random Clock Jitter (RMS) 1.6 ps
tr/tfOutput Rise/Fall Time (20-80%) 200 550 200 500 200 500 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. VCC can vary ±0.15 V.
6. Specifications for standard TTL input signal.
MC100LVELT22
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4
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D - Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC - 3.0 V
ORDERING INFORMATION
Device Package Shipping†
MC100LVELT22D SOIC-8 98 Units / Rail
MC100LVELT22DG SOIC-8
(Pb-Free)
98 Units / Rail
MC100LVELT22DR2 SOIC-8 2500 / Tape & Reel
MC100LVELT22DR2G SOIC-8
(Pb-Free)
2500 / Tape & Reel
MC100LVELT22DT TSSOP-8 100 Units / Rail
MC100LVELT22DTG TSSOP-8
(Pb-Free)
100 Units / Rail
MC100LVELT22DTR2 TSSOP-8 2500 / Tape & Reel
MC100LVELT22DTR2G TSSOP-8
(Pb-Free)
2500 / Tape & Reel
MC100LVELT22MNR4 DFN8 1000 / Tape & Reel
MC100LVELT22MNRG DFN8
(Pb-Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D - ECL Clock Distribution Techniques
AN1406/D - Designing with PECL (ECL at +5.0 V)
AN1503/D -ECLinPSt I/O SPiCE Modeling Kit
AN1504/D - Metastability and the ECLinPS Family
AN1568/D - Interfacing Between LVDS and ECL
AN1672/D - The ECL Translator Guide
AND8001/D - Odd Number Counters Design
AND8002/D - Marking and Date Codes
AND8020/D - Termination of ECL Logic Devices
AND8066/D - Interfacing with ECLinPS
AND8090/D - AC Characteristics of ECL Devices
MC100LVELT22
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5
PACKAGE DIMENSIONS
SOIC-8 NB
CASE 751-07
ISSUE AH
SEATING
PLANE
1
4
58
N
J
X 45_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
-X-
-Y-
G
M
Y
M
0.25 (0.010)
-Z-
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
MC100LVELT22
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6
PACKAGE DIMENSIONS
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.80 1.10 0.031 0.043
D0.05 0.15 0.002 0.006
F0.40 0.70 0.016 0.028
G0.65 BSC 0.026 BSC
L4.90 BSC 0.193 BSC
M0 6 0 6
____
SEATING
PLANE
PIN 1
14
85
DETAIL E
B
C
D
A
G
DETAIL E
F
M
L
2X L/2
-U-
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
-T-
-V-
-W-
0.25 (0.010)
8x REFK
IDENT
K0.25 0.40 0.010 0.016
TSSOP-8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R-02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
MC100LVELT22
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7
PACKAGE DIMENSIONS
DFN8
CASE 506AA-01
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
A
D
E
B
C0.10
PIN ONE
2 X
REFERENCE
2 X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
L
(A3)
D2
E2
C
C0.10
C0.10
C0.08
8 X
A1
SEATING
PLANE
e/2 e
8 X
K
NOTE 3
b8 X 0.10 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.20 0.30
D2.00 BSC
D2 1.10 1.30
E2.00 BSC
E2 0.70 0.90
e0.50 BSC
K0.20 ---
L0.25 0.35
14
85
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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PUBLICATION ORDERING INFORMATION
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Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81-3-5773-3850
MC100LVELT22/D
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
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