©2009 Integrated Device Technology, Inc.
JANUARY 2009
DSC 4833/12
1
HIGH-SPEED 3.3V 32K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
CNTRST
R
Counter/
Address
Reg.
A
14R
A
0R
Counter/
Address
Reg.
CNTEN
R
ADS
R
CNTEN
L
ADS
L
CNTRST
L
Dout0-8_L
Dout9-17_L Dout0-8_R
Dout9-17_R
B
W
0
L
B
W
1
L
B
W
1
R
B
W
0
R
I/O
0L
-I/O
17L
I/O
0R
-I/O
17R
Din_L
ADDR_L
Din_R
ADDR_R
OE
R
OE
L
4833 tbl 01
UB
L
LB
L
R
/W
L
CE
0L
UB
R
LB
R
R/W
R
CE
0R
CE
1R
CE
1L
32K x 18
MEMORY
ARRAY
CLK
R
CLK
L
.
,
A
14L
A
0L
Functional Block Diagram
Features:
◆True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
◆Pipelined output mode
◆Counter enable and reset features
◆Dual chip enables allow for depth expansion without
additional logic
◆Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆Separate byte controls for multiplexed bus and bus
matching compatibility
◆LVTTL- compatible, single 3.3V (±150mV) power supply for
core
◆LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
◆Industrial temperature range (-40°C to +85°C) is
available for selected speeds
◆Available in a 128-pin Thin Quad Plastic Flatpack (TQFP)
and 208-pin fine pitch Ball Grid Array, and 256-pin
Ball Grid Array
IDT70V3379S
◆Green parts available, see ordering information
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
2
Description:
The IDT70V3379 is a high-speed32K x 18 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times. With an input data register, the IDT70V3379 has been
optimized for applications having unidirectional or bidirectional data flow
in bursts. An automatic power down feature, controlled by CE0 and CE1,
permits the on-chip circuitry of each port to enter a very low standby power
mode.
The 70V3379 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controllable by the OPT pins. The power supply for
the core of the device (VDD) remains at 3.3V.
Pin Configuration(1,2,3,4)
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
1716
15
1412 13
10
9876543
21 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
I/O
9L
NC V
SS
NC
A
2L
A
4L
CLK
L
A
8L
A
12L
NC
NC OPT
L
NC V
SS
NC V
SS
A
1L
A
5L
A
9L
A
13L
NC
V
DDQL
I/O
9R
V
DDQR
V
DD
A
3L
A
6L
NC
A
10L
A
14L
NC NC
NC V
SS
I/O
10L
NC
NC
I/O
11L
NC V
DDQR
I/O
10R
NC
I/O
11R
NC V
SS
V
DD
NC I/O
12L
V
DD
V
SS
V
SS
NC
V
SS
I/O
12R
CNTRST
R
NC I/O
14L
V
DDQR
V
DDQL
I/O
15R
NC V
SS
NCNC
NC A
11L
A
7L
A
0L
NC
I/O
7L
NC
I/O
6L
I/O
8R
UB
L
NC
I/O
8L
V
DDQL
CE
0L
CE
1L
LB
L
CNTRST
L
OE
L
I/O
0L
I/O
2L
I/O
1R
ADS
R
R/W
R
NC
I/O
16R
I/O
15L
NC
A
13R
A
12R
NC V
DD
CLK
R
I/O
0R
NC
NC
NC
NC NC
NC
V
SS
A
5R
A
9R
CE
0R
CE
1R
V
DD
V
SS
NC
NC
NC
NC
NC
NC A
14R
A
10R
UB
R
V
SS
V
DDQL
I/O
1L
I/O
2R
NC
NC NC NC A
11R
A
7R
LB
R
OE
R
V
SS
NC
V
DDQL
OPT
R
NC
70V3379BF
BF-208
(5)
208-Pin fpBGA
Top View
(6)
4833 tbl 02
I/O
14R
V
DDQL
V
SS
V
DDQR
NC
NC
NC
NC I/O
7R
NC
R/W
L
NC
ADS
L
V
DDQL
I/O
13R
CNTEN
L
V
SS
I/O
13L
V
SS
I/O
16L
V
DDQR
V
SS
I/O
17R
I/O
17L
V
DDQL
V
SS
V
DD
A
8R
CNTEN
R
A
6R
A
3R
A
1R
A
2R
A
0R
I/O
3L
I/O
4L
A
4R
V
DD
V
SS
V
SS
V
SS
V
DDQR
V
DDQL
V
SS
V
DDQR
V
SS
I/O
3R
I/O
4R
V
SS
V
DDQR
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
5R
I/O
5L
V
DDQR
I/O
6R
V
SS
V
SS
V
DDQL
V
DD
V
SS
V
DDQR
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
1
2/05/01
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
3
Pin Configuration(1,2,3,4) (con't.)
E16
I/O7R
D16
I/O8R
C16
I/O8L
B16
NC
A16
NC
A15
NC
B15
NC
C15
NC
D15
NC
E15
I/O7L
E14
NC
D14
NC
D13
VDD
C12
A6L C14
OPTL
B14
VDD
A14
A0L
A12
A5L
B12
A4L
C11
ADSL
D12
VDDQR
D11
VDDQR
C10
CLKL
B11
CNTRST
L
A11
CNTEN
L
D8
VDDQR
C8
NC
A9
CE1L
D9
VDDQL
C9
LBL
B9
CE0L
D10
VDDQL
C7
A7L
B8
UBL
A8
NC
B13
A1L
A13
A2L
A10
OEL
D7
VDDQR
B7
A9L
A7
A8L
B6
A12L
C6
A10L
D6
VDDQL
A5
A14L
B5
NC
C5
A13L
D5
VDDQL
A4
NC
B4
NC
C4
NC
D4
VDD
A3
NC
B3
NC
C3
VSS
D3
NC
D2
I/O9R
C2
I/O9L
B2
NC
A2
NC
A1
NC
B1
NC
C1
NC
D1
NC
E1
I/O10R E2
I/O10L E3
NC E4
VDDQL
F1
I/O11L F2NC F3
I/O11R F4
VDDQL
G1NC G2
NC G3
I/O12L
G4
VDDQR
H1NC H2
I/O12R
H3NC H4
VDDQR
J1
I/O13L J2
I/O14R J3
I/O13R J4
VDDQL
K1
NC K2
NC K3
I/O14L
K4
VDDQL
L1
I/O15L L2NC L3
I/O15R L4
VDDQR
M1
I/O16R M2
I/O16L M3
NC M4
VDDQR
N1
NC N2
I/O17R N3
NC N4
VDD
P1
NC P2
I/O17L P3NC P4
NC
R1NC R2NC R3NC R4NC
T1NC T2NC T3NC T4NC
P5
A13R
R5
NC
P12
A6R
P8NC P9
LBR
R8
UBR
T8NC
P10
CLKR
T11
CNTEN
R
P11
ADSR
R12
A4R
T12
A5R
P13
A3R
P7
A7R
R13
A1R
T13
A2R
R6
A12R
T5
A14R T14
A0R
R14
OPTR
P14
NC P15
NC
R15
NC
T15
NC T16
NC
R16
NC
P16
I/O0L
N16
NC
N15
I/O0R
N14
NC
M16
NC
M15
I/O1L
M14
I/O1R
L16
I/O2R
L15
NC
L14
I/O2L
K16
I/O3L
K15
NC
K14
NC
J16
I/O4L
J15
I/O3R
J14
I/O4R
H16
I/O5R
H15
NC
H14
NC
G16
NC
G15
NC
G14
I/O5L
F16
I/O6L
F14
I/O6R F15
NC
R9
CE0R R11
CNTRST
R
T6
A11R
T9
CE1R
A6
A11L
B10
R/WL
C13
A3L
P6
A10R
R10
R/WR
R7
A9R
T10
OER
T7
A8R
,
E5
VDD E6
VDD E7
VSS E8
VSS E9
VSS E10
VSS E11
VDD E12
VDD E13
VDDQR
F5
VDD F6
VSS F8VSS
F9
VSS F10
VSS F12
VDD F13
VDDQR
G5
VSS G6
VSS G7
VSS
G8
VSS G9
VSS G10
VSS G11
VSS
G12
VSS G13
VDDQL
H5
VSS H6
VSS
H7
VSS H8
VSS H9
VSS H10
VSS
H11
VSS H12
VSS H13
VDDQL
J5
VSS J6VSS J7VSS J8VSS J9
VSS J10
VSS J11
VSS J12
VSS
J13
VDDQR
K5
VSS
K6
VSS K7
VSS
K8
VSS
L5
VDD L6VSS
L7
VSS L8
VSS
M5
VDD M6
VDD M7
VSS M8
VSS
N5
VDDQR N6
VDDQR N7
VDDQL
N8
VDDQL
K9
VSS
K10
VSS K11
VSS
K12
VSS
L9
VSS L10
VSS
L11
VSS L12
VDD
M9
VSS M10
VSS M11
VDD M12
VDD
N9
VDDQR N10
VDDQR N11
VDDQL
N12
VDDQL
K13
VDDQR
L13
VDDQL
M13
VDDQL
N13
VDD
F7
VSS F11
VSS
4833 drw 02c
,
12/05/01
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
70V3379BC
BC-256(5)
256-Pin BGA
Top View(6)
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
70
69
68
67
66
65
91
71
A
14L
NC
V
SS
NC
IO
9L
IO
9R
V
DDQL
V
SS
IO
10L
IO
10R
V
DDQR
V
SS
IO
11L
IO
11R
IO
12L
IO
12R
V
DD
V
DD
V
SS
V
SS
IO
13R
IO
13L
IO
14R
IO
14L
IO
15R
IO
15L
V
DDQL
V
SS
IO
16R
IO
16L
V
DDQR
V
SS
IO
17R
IO
17L
NC
NC
NC
A
14R
A
1R
A
0R
OPT
R
IO
0L
IO
0R
V
DDQR
V
SS
IO
1L
IO
1R
V
DDQL
V
SS
IO
2L
IO
2R
IO
3L
IO
3R
IO
4L
IO
4R
V
SS
V
SS
V
DD
V
DD
IO
5L
IO
5R
V
DDQR
V
SS
IO
7R
IO
7L
V
DDQL
V
SS
NC (V
SS
)
(7)
IO
8R
IO
8L
NC (V
SS
)
(7)
OPT
L
A
0L
A
1L
IO
6R
IO
6L
70V3379PRF
PK-128
(5)
128-Pin TQFP
Top View
(6)
4833 drw 02a
A
13L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
UB
L
LB
L
CE
1L
CE
0L
V
DD
V
DD
V
SS
V
SS
CLK
L
OE
L
R/W
L
ADS
L
CNTEN
L
CNTRST
L
A
6L
A
5L
A
4L
A
3L
A
2L
A
13R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
UB
R
LB
R
CE
1R
CE
0R
V
DD
V
DD
V
SS
V
SS
CLK
R
OE
R
R/W
R
ADS
R
CNTEN
R
CNTRST
R
A
6R
A
5R
A
4R
A
3R
A
2R
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
.
12/05/01
Pin Configuration(1,2,3,4) (con't.)
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 14mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. In the 70V3379 (32K x 18) and 70V3389 (64K x 18), pins 96 and 99 are NC. The upgrade devices 70V3399 (128K x 18) and 70V3319 (256K x 18) assign
these pins as Vss. Customers who plan to take advantage of the upgrade path should treat these pins as VSS on the 70V3379 and 70V3389. If no upgrade is
needed, the pins can be treated as NC.
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
5
NOTES:
1 . "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table I—Read/Write and Enable Control(1,2,3)
Pin Names
Left Port Right Port Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip Enables
R/W
L
R/W
R
Read / Wri te E nable
OE
L
OE
R
Output Enable
A
0L
- A
14L
A
0R
- A
14R
Address
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Da ta Inp u t/ O utp u t
CLK
L
CLK
R
Clock
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counte r Enable
CNTRST
L
CNTRST
R
Co unte r Reset
UB
L
- LB
L
UB
R
- LB
R
Byte Enables (9-bit bytes)
V
DDQL
V
DDQR
Po wer (I/O B us) (3.3V o r 2.5V )
(1)
OPT
L
OPT
R
Op tio n fo r s e le c ting V
DDQX
(1,2)
V
DD
Po wer (3.3V)
(1)
V
SS
Gro und (0V)
48 33 tbl 01
OE CLK CE
0
CE
1
UB LB R/WUp pe r By te
I/O
9-18
Lower Byte
I/O
0-8
MODE
X↑L H H H X Hig h-Z Hig h-Z All By te s Des elec te d
X↑LHHLLHigh-Z D
IN
Wri te to Lo we r B yte Only
X↑LHLHL D
IN
High-Z Write to Upper Byte Only
X↑LHLLL D
IN
D
IN
Write to Bo th Byte s
L↑LHHLHHigh-Z D
OUT
Re ad Lo we r By te Only
L↑LHLHHD
OUT
Hig h-Z Read Upp er By te Only
L↑LHLLHD
OUT
D
OUT
Read Bo th Byte s
H↑L H L L X High-Z Hig h-Z Outputs Di sab le d
4833 t bl 02
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
6
Recommended Operating
Temperature and Supply Voltage(1)
Absolute Maximum Ratings(1)
Truth Table II—Address Counter Control(1,2)
NOTES:
1 . "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
NOTES:
1. This is the parameter TA. This is the "instant on" case tempereature.
Address Previous
Address Addr
Used CLK
(6)
ADS CNTEN CNTRST I/O
(3)
MODE
XX0
↑XX L
(4)
D
I/O
(0) Counter Reset to Address 0
An X An ↑ L
(4)
XHD
I/O
(n) External Address Used
An Ap Ap ↑HH H D
I/O
(p) External Address Blocked—Counter disabled (Ap reused)
XApAp + 1
↑H L
(5)
HD
I/O
(p+1) Counter Enabled—Internal Address generation
4833 t bl 0 3
Grade Ambient
Temperature GND V
DD
Commercial 0
O
C to + 70
O
C0V3.3V
+
150m V
Industrial -40
O
C to +85
O
C0V3.3V
+
150m V
4833 tbl 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Sup ply Voltag e 3.15 3.3 3.45 V
V
DDQ
I/O Supply Voltag e
(3)
2.375 2.5 2.625 V
V
SS
Ground 0 0 0 V
V
IH
Input Hig h Vo ltag e
(3)
(Address & Control Inputs) 1.7
____
V
DDQ
+ 125mV
(2)
V
V
IH
In p u t Hi g h Vo ltag e - I/ O
(3)
1.7
____
V
DDQ
+ 125mV
(2)
V
V
IL
Inp ut Low Voltag e -0.3
(1)
____
0.7 V
4833 tbl 05a
Symbol Rating Commercial
& Industrial Unit
V
TERM
(2)
Terminal Vo ltage
wi th Re s pe c t to
GND
-0. 5 to + 4.6 V
T
BIAS
Temperature
Under Bias -55 to +125
o
C
T
STG
Storage
Temperature -65 to + 150
o
C
I
OUT
DC Output Curre nt 50 mA
4833 t bl 06
Recommended DC Operating
Conditions with VDDQ at 2.5V
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 125mV.
3 . To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be
supplied as indicated above.
Recommended DC Operating
Conditions with VDDQ at 3.3V
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 150mV.
3 . To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Supply Voltage 3.15 3.3 3.45 V
V
DDQ
I/ O S up p l y Vo l tag e
(3)
3.15 3.3 3.45 V
V
SS
Ground 0 0 0 V
V
IH
Inp ut Hi g h Vo ltag e
(Add re ss & Co ntro l Inp uts)
(3)
2.0
____
V
DDQ
+ 150mV
(2)
V
V
IH
Input High Voltage - I/O
(3)
2.0
____
V
DDQ
+ 150mV
(2)
V
V
IL
Inp ut Low Vo ltag e -0.3
(1)
____
0.8 V
4833 tbl 05b
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
7
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
NOTE:
1. At VDD < - 2.0V input leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.4 for details.
Symbol Parameter Test Condi tions
70V3379S
UnitMin. Max.
|I
LI
| Inp ut Le akag e Curre nt
(1)
V
DDQ
= Max., V
IN
= 0V to V
DDQ
___
10 µA
|I
LO
| Outp ut Le ak age Curre nt CE
0
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
DDQ
___
10 µA
V
OL
(3. 3V) Output Low Vo ltag e
(2)
I
OL
= +4mA, V
DDQ
= Min.
___
0.4 V
V
OH
(3.3V) Output High Voltage
(2)
I
OH
= -4mA, V
DDQ
= Min. 2.4
___
V
V
OL
(2. 5V) Output Low Vo ltag e
(2)
I
OL
= +2mA, V
DDQ
= Min.
___
0.4 V
V
OH
(2.5V) Output High Voltage
(2)
I
OH
= -2mA, V
DDQ
= Min. 2.0
___
V
4833 t bl 08
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) TQFP ONLY
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 8 pF
C
OUT
(3)
Outp ut Capac itanc e V
OUT
= 3dV 10.5 pF
4833 tbl 07
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
8
DC Electrical Characteristics Over the Operating
T emperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
70V3379S4
Com'l Only 70V3379S5
Com'l
& I nd
70V3379S6
Com'l Only
S ymbol Parameter Test Con diti on Versi on Typ .
(4)
Max. Typ.
(4)
Max. Typ.
(4)
Max. Unit
I
DD
Dy namic Op e rating
Cu rren t ( B o t h
Po rts Active)
CE
L
and CE
R
= V
IL
,
Outp uts Disable d,
f = f
MAX
(1)
COM'L S 375 460 285 360 245 310 mA
IND S
____ ____
285 415
____ ____
I
SB1
Standby Curre nt
(B o th P o rts - TTL
Le vel Inp uts )
CE
L
= CE
R
= V
IH
f = f
MAX
(1)
COM'L S 145 190 105 145 95 125 mA
IND S
____ ____
105 175
____ ____
I
SB2
Standby Curre nt
(One Po rt - TTL
Le vel Inp uts )
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outp uts Disabled ,
f=f
MAX
(1)
COM'L S 265 325 190 260 175 225 mA
IND S
____ ____
190 300
____ ____
I
SB3
Ful l S tand b y C urrent
(Bo th P orts - CMOS
Le vel Inp uts )
Both Ports CE
L
and
CE
R
> V
DDQ
- 0.2V,
V
IN
> V
DDQ
- 0.2V or V
IN
< 0. 2 V,
f = 0
(2)
COM'LS615615615
mA
IND S
____ ____
630
____ ____
I
SB4
Ful l S tand b y C urrent
(One Po rt - CMOS
Le vel Inp uts )
CE
"A"
< 0. 2V and
CE
"B"
> V
DDQ
- 0. 2V
(5)
V
IN
> V
DDQ
- 0.2V or V
IN
< 0. 2 V,
Active Port, Outputs Disabled ,
f = f
MAX
(1)
COM'L S 265 325 180 260 170 225 mA
IND S
____ ____
180 300
____ ____
4833 tbl 09
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
9
AC Test Conditions
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 3. Typical Output Derating (Lumped Capacitive Load).
Inp ut P ulse Lev el s (Add ress & Co ntrols )
In p ut P ul s e Le v e l s (I/ Os )
In p ut R ise / F al l Ti mes
In p ut Timi ng Re fer e nc e Le v e l s
Outp ut Refe re nce Le ve ls
Outp ut Lo ad
GND to 3
.
0V/ GND to 2.35V
GND to 3. 0V/ GND to 2. 35V
3ns
1.5V/1.25V
1.5V/1.25V
F ig ures 1, 2, and 3
4833 tbl 10
1.5V/1.25
50Ω
50Ω
4833 drw 03
10pF
(Tester)
D
ATA
OUT
,
4833 drw 04
590Ω
5pF*
435Ω
3.3V
DATAOUT
,
833Ω
5pF*
770Ω
2
.
5
V
DATAOUT
,
-1
1
2
3
4
5
6
7
20.5 30 50 80 100 200
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
Capacitance (pF)
∆tCD
(
Typical, ns)
4833 drw 05
•
•
•
•
·
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the Operating
T emperature Range (Read and Write Cycle Timing)(1,2)
(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
NOTES:
1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).
2. These values are valid for either level of VDDQ (3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.
70V3379S4
Com'l Only 70V3379S5
Com'l
& In d
70V3379S6
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
t
CYC2
Clo ck Cy cle Time (Pip eline d ) 7.5
____
10
____
12
____
ns
t
CH2
Clo ck High Time (Pip eline d) 3
____
4
____
5
____
ns
t
CL2
Clo ck Lo w Time (Pip elined ) 3
____
4
____
5
____
ns
t
R
Cloc k Ri se Ti me
____
3
____
3
____
3ns
t
F
Clock Fall Time
____
3
____
3
____
3ns
t
SA
Address Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HA
Address Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SC
Chip Enable Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HC
Chip Enable Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SB
Byte Enable Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HB
Byte Enab l e Ho ld Time 0. 7
____
0.7
____
1.0
____
ns
t
SW
R/W Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HW
R/W Ho ld Time 0.7
____
0.7
____
1.0
____
ns
t
SD
Inp ut Data Se tup Time 1. 8
____
2.0
____
2.0
____
ns
t
HD
Inp ut Data Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SAD
ADS Se tup Time 1.8
____
2.0
____
2.0
____
ns
t
HAD
ADS Hol d Ti me 0.7
____
0.7
____
1.0
____
ns
t
SCN
CNTEN Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HCN
CNTEN Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SRST
CNTRST Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HRST
CNTRST Ho ld Time 0.7
____
0.7
____
1.0
____
ns
t
OE
(1)
Outp ut Enab le to Data Vali d
____
4
____
5
____
6ns
t
OLZ
Output Enable to Output Low-Z 0
____
0
____
0
____
ns
t
OHZ
Outp ut Enab le to Output Hig h-Z 1 4 1 4.5 1 5 ns
t
CD2
Clock to Data Valid (Pipelined)
____
4.2
____
5
____
6ns
t
DC
Data Outp ut Ho ld Afte r Cl oc k Hig h 1
____
1
____
1
____
ns
t
CKHZ
Clo c k High to Outp ut Hi gh -Z 1 3 1 4.5 1. 5 6 ns
t
CKLZ
Clo c k Hi g h to O utput Lo w-Z 1
____
1
____
1
____
ns
Port-to-Port Delay
t
CO
Cloc k-to -Cloc k Offs e t 6
____
8
____
10
____
ns
4 833 tb l 1
1
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
11
t
SC
t
HC
CE
0(B1)
ADDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CLK
4833 drw 07
Q
0
Q
1
Q
3
DATA
OUT(B1)
t
CH2
t
CL2
t
CYC2
ADDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
Q
2
Q
4
t
CD2
t
CD2
t
CKHZ
t
CD2
t
CKLZ
t
DC
t
CKHZ
t
CD2
t
CKLZ
t
SC
t
HC
t
CKHZ
t
CKLZ
t
CD2
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
An An + 1 An + 2 An + 3
t
CYC2
t
CH2
t
CL2
R/
W
ADDRESS
CE
0
CLK
CE
1
UB,LB
(0-3)
(3)
DATA
OUT
OE
t
CD2
t
CKLZ
Qn Qn + 1 Qn + 2
t
OHZ
t
OLZ
t
OE
4833 drw 06
(1)
(1)
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
DC
t
SC
t
HC
t
SB
t
HB
(4)
(1 Latency)
(5)
(5)
Timing Waveform of a Multi-Device Pipelined Read(1,2)
Timing Waveform of Read Cy cle for Pipelined Operation(2)
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and CNTRST = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB or LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3379 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
12
CLK
L
R/W
L
ADDRESS
L
DATA
INL
CLK
R
R/W
R
ADDRESS
R
DATA
OUTR
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
SW
t
HW
t
SA
t
HA
t
CO
(3)
t
CD2
NO
MATCH
VALID
NO
MATCH
MATCH
MATCH
VALID
4833 drw 08
t
DC
R/
W
ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4
DATA
IN
Dn + 2
CE
0
CLK
4833 drw 09
Qn Qn + 3
DATA
OUT
CE
1
UB,LB
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
CH2
t
CL2
t
CYC2
READ NOP READ
t
SD
t
HD
(3)
(1)
t
SW
t
HW
WRITE
(4)
Timing Wa v ef orm of Left Port Write to Pipelined Right P ort R ead(1,2)
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will
be tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite
port will be tCO + tCYC + tCD2).
Timing W aveform of Pipelined Read-to-Write-to-R ead (OE = VIL)(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
13
ADDRESS An
CLK
DATA
OUT
Qx - 1
(2)
Qx Qn Qn + 2
(2)
Qn + 3
ADS
CNTEN
t
CYC2
t
CH2
t
CL2
4833 drw 11
t
SA
t
HA
t
SAD
t
HAD
t
CD2
t
DC
READ
EXTERNAL
ADDRESS READ WITH COUNTER COUNTER
HOLD
t
SAD
t
HAD
t
SCN
t
HCN
READ
WITH
COUNTER
Qn + 1
R/
W
ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5
DATA
IN
Dn + 3Dn + 2
CE
0
CLK
4833 drw 10
DATA
OUT
Qn Qn + 4
CE
1
UB,LB
OE
t
CH2
t
CL2
t
CYC2
t
CKLZ
t
CD2
t
OHZ
t
CD2
t
SD
t
HD
READ WRITE READ
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
(3)
(1)
t
SW
t
HW
(4)
Timing Waveform of Pipelined Read with Address Counter Advance(1)
NOTES:
1. CE0, OE, UB, LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
14
ADDRESS An
D
0
t
CH2
t
CL2
t
CYC2
Q
0
Q
1
0
CLK
DATA
IN
R/
W
CNTRST
4833 drw 13
INTERNAL
(3)
ADDRESS
ADS
CNTEN
t
SRST
t
HRST
t
SD
t
HD
t
SW
t
HW
COUNTER
RESET WRITE
ADDRESS 0 READ
ADDRESS 0 READ
ADDRESS 1 READ
ADDRESS n
Qn
An + 1 An + 2
READ
ADDRESS n+1
DATA
OUT
t
SA
t
HA
1An An + 1
(4)
(5)
(6)
Ax
t
SAD
t
HAD
t
SCN
t
HCN
Timing Waveform of Write with Address Counter Advance(1)
Timing Waveform of Counter Reset(2)
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: ADDR 0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
ADDRESS An
CLK
DATA
IN
Dn Dn + 1 Dn + 1 Dn + 2
ADS
CNTEN
t
CH2
t
CL2
t
CYC2
4833 drw 12
INTERNAL
(3)
ADDRESS An
(7)
An + 1 An + 2 An + 3 An + 4
Dn + 3 Dn + 4
t
SA
t
HA
t
SAD
t
HAD
WRITE
COUNTER HOLD WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
t
SD
t
HD
t
SCN
t
HCN
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
15
Functional Description
The IDT70V3379 provides a true synchronous Dual-Port Static RAM
interface. Registered inputs provide minimal set-up and hold times on
address, data, and all critical control inputs. All internal registers are clocked
on the rising edge of the clock signal, however, the self-timed internal write
pulse is independent of the LOW to HIGH transition of the clock signal.
An asynchronous output enable is provided to ease asyn-
chronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V3379s for depth expan-
sion configurations. Two cycles are required with CE0 LOW and CE1
HIGH to re-activate the outputs.
4833 drw 14
IDT70V3379
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
A
15
CE
1
CE
0
V
DD
V
DD
IDT70V3379
IDT70V3379
IDT70V3379
Control Inputs
Control Inputs
Control Inputs
Control Inputs UB,LB
R/W,
OE,
CLK,
ADS,
CNTRST,
CNTEN
.
Depth and Width Expansion
The IDT70V3379 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V3379 can also be used in applications requiring expanded
width, as indicated in Figure 4. Through combining the control signals, the
devices can be grouped as necessary to accommodate applications
needing 36-bits or wider.
Figure 4. Depth and Width Expansion with IDT70V3379
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
16
Ordering Information
A
Power 99
Speed A
Package A
Process/
Temperature
Range
Blank
I
(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BF
PRF
BC 208-pin fpBGA (BF-208)
128-pin TQFP (PK-128)
256-pin BGA (BC-256)
4
5
6
XXXXX
Device
Type
Speed in
nanoseconds
4833 drw 15A
SStandard Power
70V3379 576K (32K x 18-Bit) 3.3V
Synchronous Dual-Port RAM
Commercial Only
Commercial & Industrial
Commercial Only
.
A
G
(2)
Green
NOTES:
1. Contact your local sales office for Industrial temp range in other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
Datasheet Document History
1/18/98: Initial Public Release
3/15/99: Page 10 Additional Notes
4/28/99: Added fpBGA package
6/8/99: Page 2 Changed package body height from 1.5mm to 1.4mm
6/11/99: Page 5 Deleted note 6 for Table II
7/14/99: Page 2 Corrected pin to T3 to VDDQL
8/4/99: Page 6 Improved power numbers
10/4/99: Upgraded speed to 133MHz, added 2.5V I/O capability
11/12/99: Replaced IDT logo
2/28/00: Added new BGA package, added full 2.5V interface capability
5/1/00: Page 2 Added ball pitch
Page 3 Renamed pins
Page 6 Made corrections to Truth Table
Page 9 Changed Ω numbers in figure 2
6/7/00: Page 4 Added information to pin and pin notes
Page 6 Increased storage temperature parameter
Clarified TA Parameter
Page 8 DC Electrical parameters–changed wording from "open" to "disabled"
Removed note 7 on DC Electrical Characteristics table
6.42
IDT70V3379S
High-Speed 3.3v 32K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
17
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
Datasheet Document History
01/18/98: Initial Public Release
03/15/99: Page 10 Additional Notes
04/28/99: Added fpBGA package
06/08/99: Page 2 Changed package body height from 1.5mm to 1.4mm
06/11/99: Page 5 Deleted note 6 for Table II
07/14/99: Page 2 Corrected pin to T3 to VDDQL
08/04/99: Page 6 Improved power numbers
10/04/99: Upgraded speed to 133MHz, added 2.5V I/O capability
11/12/99: Replaced IDT logo
02/28/00: Added new BGA package, added full 2.5V interface capability
05/01/00: Page 2 Added ball pitch
Page 3 Renamed pins
Page 6 Made corrections to Truth Table
Page 9 Changed Ω numbers in figure 2
06/07/00: Page 4 Added information to pin and pin notes
Page 6 Increased storage temperature parameter
Clarified TA Parameter
Page 8 DC Electrical parameters–changed wording from "open" to "disabled"
Removed note 7 on DC Electrical Characteristics table
01/10/01: Page 1 Changed 64K to 32K in block drawing
Removed Preliminary status
04/10/01: Added Industrial Temperature Ranges and removed related notes
12/12/01: Page 2, Added date revision to pin configurations
3& 4
Page 6 Removed i ndustrial temp footnote from table 04
Page 8 Removed industrial temp for 6ns from DC & AC Electrical Characteristics
& 10
Page 16 Removed industrial temp from 6ns in ordering information
Added industrial temp footnote
Page 1 Replaced TM logo with ® logo
& 17
01/05/06: Page 1 Added green availability to features
Page 16 Added green indicator to ordering information
02/08/06: Page 5 Changed footnote 2 for Truth Table I from ADS, CNTEN, CNTRST = VIH to ADS, CNTEN, CNTRST = X
07/25/08: Page 8 Corrected a typo in the DC Chars table
01/19/09: Page 16 Removed "IDT" from orderable part number
