19-3950; Rev 0; 6/91 MAAXAL/VI Complete, 8-Channel, 12-Bit Data-Acquisition Systems General Description The MAX180/MAX181 are complete 12-bit Data Acquisition System (DAS) which combine 8/6-channel input multi- plexer, high bandwidth Track-and-Hold (T/H), low-drift zener reference, and flexible microprocessor (uP) interface with high conversion speed and low power consumption. The MAX180/MAX181 can be configured by a uP for unipolar or bipolar conversions and single-ended or differ- ential inputs. Both devices sample and digitize at 100kHz throughput rate and feature a fast 8- or 16-bit uP interface. The MAX180 has 8 analog input channels, while the MAX18 1 has 6. The multiplexer output of the MAX180 is fed directly into the Analog-to-Digital Converter (ADC) input. The MAX181 brings out both the multiplexer output and ADC input to separate pins, allowing a programmable gain amplifier to be inserted between the MUX and the ADC. The systems allow the user to choose between an internal or an external reference. Futhermore, the internal refer- ence value and the offset can be adjusted, allowing the overall system gain and offset errors to be nulled. The multiplexer has high impedance inputs, simplifying ana- log drive requirements. Applications High-Speed Servo Loops Digital-Signal Processing High-Accuracy Process Control Automatic Testing Systems Block Diagram Features @ 12-Bit Resolution, +1/2LSB Linearity @ 8-Channel Multiplexed Inputs (MAX180) @ Single-Ended 1-of-6 Multiplexer (MAX181) @ Built-In Track-and-Hold @ 100kHz Sampling Rate @ DC and Dynamically Tested @ Internal 25ppm/C Voltage Reference @ Each Channel Configurable for Unipolar (OV to +5V) or Bipolar (-2.5V to +2.5V) Input Range @ Each Channel Configurable for Single-Ended or Differential Inputs @ Fast 8-/16-Bit .P Interface @ +5V and -12V to -15V Supply Operation _ @ 110mW Power Consumption Ordering Information PART | TEMP.RANGE PIN-PACKAGE Tabey MAX180ACPL OC1o+70C 40PlasticDIP 41/2 MAX180BCPL OCto+70C 40PlasticDIP_ +4 MAX180CCPL OCto+70C 40 PlasticDIP_ +4 MAX180ACQH OCto+70C 44 PLCC +1/2 MAX180BCQH OCto+70C 44 PLCC +1 Ordering information continued on last page. Pin Configurations MUXOUT** ADCIN'* OFFADJ L | AINO 4 | . AI | * V 4 TH L Vpo AIN3 mux - AINA 4 } AGND ANS H+ | DGND ANG 14 Zz aN ss REFOUT H auriep REFADJ 1 ZENER REFIN {DAC SAR on SI CONTROL LATCH AND CONTROL | Pen THREE-STATE OUTPUT Do + MAX180 ONLY BUSY ** MAX181 ONLY TOP VIEW ANOT] @ ~~ ~= [a] Yoo AINI [ay re | Ke AIN2 Fs 238 AINS : MAA 4 Ag AINA (Fe ie Foe) BIP ans re] MAXIBT FS ore (MUXOUT)** AINS* [7 | aa] BUSY (ADCIN)** AIN7* [es | faa | CS REFIN fs | rae | WR AGND [10 | rar] RD REFOUT [17] rsa} HBEN REFADJ [72 | [29 | CLKIN OFFADL (73 | [2s | 00 MODE [14 | [er] D1 Vss Lis | [2s] De D1 [as | fz | 03 D10 [7 | roa | 4 D9 [18 | lea | DS D8 [19] j2z | D6 * MAX180 ONLY Dano [2] jad OY * MAX181 ONLY DIP MAAXILIMMA Maxim Integrated Products 1 For free samples & the latest literature: http:/www.maxim-ic.com, or phone 1-800-998-8800 LS LXVW/O8S LXVMAX180/MAX181 Complete, 8-Channel, 12-Bit Data-Acquisition Systems ABSOLUTE MAXIMUM RATINGS Vop to DGND VsstoDGND .......... 0.0.00 eee eee AGNDtoDGND................ AIN _, MUXOUT, ADCIN, REFADJ, OFFADJ to REFIN REFINtoDGND ................ CS, WR, RD, CLK, A2-A0, BIP, DIFF, HBEN to DGND BUSY, D0-D11toDGND ......... -0.3V, VDD + 0.3V +0.3V, Vss - 0.3V -0.3V, Vob + 0.3V -0.3V, Vpp + 0.3V Continuous Power Dissipation (any package) tO +70 oes 1000mW derates above +70C by .............. 0.00005 Operating Temperature Ranges: MAX18 _C_ _ 10mWw/C 0C to +70C MAX18 Eo 8 we. ee -40C to +85C MAX18 MUL oo... ee. BBPS to +128C Storage Temperature Range .............. -65C to +160C Lead Temperature (soldering, 10 sec} re +300C Stresses beyond those listed under Absolute Maximum Ratings" may cause permanent damage fo the device. These are stress ratings only, and functional operation of the device at ihese or any oiher conditions beyand those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VoD = +5V +5%, Vsg = -12V 5% or -15V +5%, REFIN = -5V, Internal Reference Mode, Bipolar Made, Slow-Memory Mode (see text), fCLK = 1.6MHz external, MAX180/MAX181 all grades, Ta = TMIN to TMax, unless otherwise noted.) (Note 1) PARAMETER | SYMBOL | CONDITIONS [| MIN TYP MAX | UNITS ACCURACY (Note 2) Resolution N 12 Bits Integral Nonlinearity Error INL MAKI8_A a2 LSB MAX18_B/C +1 Differential Nonlinearity Error DNL Guaranteed monotonic over temperature +1 LSB Unipolar Offset Error (Note 3) +1 +4 LSB Bipolar Offset Error (Note 3) +1 +6 LSB Unipolar Gain Error +2 +10 LSB Bipolar Gain Errror +2 +15 LSB Gain-Error Tempco (Note 4) +5 pom/"C Channel-to-Channel Matching +1/4 LSB DYNAMIC PERFORMANCE (Note 2} Sea sna | ABogaseg operant |r : Total Harmonic Distortion THD 10kHz input signal, 100kHz sampling rate, 80 dB {up to the 5th harmonic) bipolar mode, Ta = +25C Spurious-Free Dynamic Range SFDR hwolarbode Tae 10K sampling rate, 80 dB Full-Power Sampling Bandwidth In track mode, under-sampled waveform 6 MHz Toa. Acquisition tACQ 1.875 ys Asynchronous hold mode | Note 7.500 8.125 Conversion Time tcONV - S ROM, Slow Memory and I/O Port Modes; 9375 10.000 H ANALOG INPUT Voltage Range AIN_, MUXOUT, and ADCIN REFIN Vpb Unipolar, Single-Ended Range AIN_ to AGND 0 5.0 Unipolar, Differential Range AIN_+ to AIN_- 0 50 | Bipolar, Single-Ended Range AIN_ to AGND -2.5 2.5 Bipolar, Differential Range AIN_+ to AIN_- -2.5 2.5 MAXILAAComplete, 8-Channel, 12-Bit Data-Acquisition Systems ELECTRICAL CHARACTERISTICS (continued) {oD = +5V 5%, Vgs = -12V +5% or -15V +5%, REFIN = -5V, Internal Reference Mode, Bipolar Mode, Slow-Memory Mode (see text), CLK = 1.6MHz external, MAX180/MAX181 all grades, Ta = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS ANALOG INPUT (continued) Input Current AN. MAX180 +10 LA ADCIN, MAX181 +0.1 Mux-On Resistance RON AIN_ = 2.5V, ImMuxouT = 1.25mA, MAX181 2 kQ Mux-On Leakage Current ION AIN_ = MUXOUT = +5V, MAX181 +100 nA Mux-Off Leakage Current lIN (OFF) AIN_ = +5V, Vout = +5V, MAX181 +100 nA lout (OFF) | AIN_ = +5V, Vout = +8V, MAX181 +100 Input Capacitance (Note 5) CIN AIN_ . ADCIN 25 36 pF MUXOUT 35 45 REFERENCE INPUT Input Range (Note 5) -4.92 -5.00 -5.08 V Input Current -2 mA Input Resistance 25 kQ REFERENCE OUTPUT VREF Output Voltage Ta = +25C 498 -.00 -5.02 V VREF Output Tempco (Note 6) MAX18_A/B 29 | ppm/C MAX18_C 45 VREF Load Regulation (Note 7) louT = OMA to 5mA, Ta = +25C 0.2 1.0 |mVimA REFADJ, OFFADJ Input Current VREFADJ, VOFFADJ = Yop to REFIN +1 HA Disable Threshold 45 Vv REFADJ Adjustment Range REFIN < REFADJ <AGND +60 +80 mV OFFADJ Adjustment Range REFIN < OFFADJ <AGND +15 +25 LSB LOGIC INPUTS Input Low Voltage VIL MODE_ 0.8 Vv CS, RD, WR, CLK, A2-A0, DIFF, BIP, HBEN 0.8 Input High Voltage VIH MODE 46 Vv CS, RD, WR, CLK, A2-A0, DIFF, BIP, HBEN 24 Input Mid-Level Voltage VMID MODE 1.5 3.5 Vv Input Floating Voltage VEFLT MODE 25 V MODE Ta = +25C +50 +100 Input Current lin Ta = Tin to TMAX +50 +100! yA CS, RD, WR, CLK, A2-A0, | Ta=+25C H DIFF, BIP, HBEN Ta = TmIn to TMAX +10 Input Capacitance (Note 5) CIN 15 pF LOGIC OUTPUTS Output Low Voltage Vo D11-D0, BUSY, RADY, Isink = 1.6mA 0.4 Vv Output High Voltage Vou D11-D0, BUSY, RDY, IsourRcE = 360A 40 Vv Floating State Leakage Current ILKG D11-D0, Vout = OV to Voo +10 nA He ae parce (Note 5) COUT S| pF MAXIM 3 KS EXVIW/O8LXVIMAX180/MAX181 Complete, 8-Channel, 12-Bit Data-Acquisition Systems ELECTRICAL CHARACTERISTICS (continued) {VoD = +5V +5%, Vsg = -12V +5% or -15V+5%, REFIN = -5V, Internal Reference Mode, Bipolar Mode, Slow-Memory Mode (see text), CLK = 1.6MHz external, MAX180/MAX181 all grades, Ta = TMIN to Tmax, unless otherwise noted.) (Note 1) PARAMETER | SYMBOL | CONDITIONS [ MIN TYP MAX UNITS POWER REQUIREMENTS Supply Voltage (Note 1) VoD 478 5.00 _ 5.26 V Vss -11.40 -15.75 Supply Current loo Vop = 5V 46 70 | nA Iss Vss = -12V 7.0 10.0 Power Dissipation PD Vpp = 5V, VSS = -15V 110 155 mW Input near FS, Vsg = -12V, Vpp = 4.75V to 5. 25V te FI Power-Supply Rejection, FE = 5V with Internal Reference PSR yet net SY Von Say 41/8 = +42 | LSB Input near FS, Vpop = SV, Vgg = -11.4V to = -12.6V 418 -t1/2 TIMING CHARACTERISTICS (VoD = +5V, Vg = -12V, foLK = 1.6MHz, Internal Reference Mode, Ta = TMIN to TMAX, unless otherwise noted.) (Note 8) PARAMETER SYMBOL CONDITIONS Ta = +25C MAX'18_C/E MAX18 M UNITS MIN TYP MAX| MIN TYP MAX| MIN TYP MAX CS to RD Setup time t4 | Note 5 0 0 0 ns CS to RD Hold time to 0 ff) 0 ns CS to WR Setup time 13 0 0 0 ns CS to WR Hold time t4. | Note 5 0 0 0 ns WR Low Pulse Width ts 120 120 120 ns WR High Pulse Width tg | MODE=9 | Note 5 200 200 200 ns DATA IN to WR Setup Time tz 80 100 120 ns DATA IN to WR Hold Time tg 0 0 0 ns WR Rising to BUSY Delay tg CL = 50pF, MODE = 1 160 180 200 | ns WR Falling to BUSY Delay tio CL = 50pF, MODE = open 220 260 280 | ns RD Low Pulse Width tt 100 130 150 ns RD High Pulse Width ti2 Note 5 200 200 200 ns DATA IN to RD Setup Time tig 80 100 120 ns DATA IN to RD Hold Time tia 0 0 0 ns RD te BUSY Fall Delay 45 C_ = 50pF 150 170 200 ns AD to Data out Valid tie CL = 100pF | Note 9 50 100 130 150} ns RD to Data out Three-State t17 Notes 9, 10 30 = 50 65 75 ns HBEN to RD or WR Setup Time| tia 80 100 120 ns HBEN to RD or WR Hold Time tra G 0 0 ns CS to READY Fall Delay tea CL = 50pF 110 130 150 | ons 4 MA AXMULANComplete, 8-Channel, 12-Bit Data-Acquisition Systems TIMING CHARACTERISTICS (continued) Vpp = +8V, Vss = -12V, foLk = 1.6MHz, Internal Reference Mode, Ta = TMIN to Tmax, unless otherwise noted.) (Note 8) PARAMETER SYMBOL CONDITIONS Ta=+25C | MAX18_C/E | MAXI6BM Units MIN TYP MAX! MIN TYP MAX| MIN TYP MAX BUSY to Data Cut Valid to1 CL = 100pF | Note 9 125 150 170 | ns CS, RD, or WR to CLK Setup time for 15 clock 122 Note 5 220 220 220 ns conversion CS, RD, or WR to CLK Setup time for 16 clock to3 Note 5 0 0 0 ns conversion Note 4: Performance at power-supply tolerance limits guaranteed by power-supply rejection test. Note 2: Vpp = +5V, Vss = -15V, FS = +5V, REFIN = -SV. Note 3: Typical change over temperature is +1LSB. Note 4: FS Tempco = AFS/AT, where AFS is full-scale change from Ta = +25C to TMIN or to TMAX. Note 5: Guaranteed by design. Note 6: REFIN TC = AREFIN/AT, where AREFIN is reference voltage change from Ta = +25C to TMIN or to TMAX Note 7: Load current should remain constant during conversion. This current is in addition to the DAC input current. Note 8: All inputs are OV to +5V swing with tr = tf = 5s (10% to 90% of 5V) and timed from a voltage level of +1.6V. Note 9: tig and to1 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. Note 10: 117 is defined as the time required for the data lines to change 0.5V when the circuit load is as shown in Figure 2. Pin Description MAX180 MAX181 NAME DIP PLCC DIP PLCC FUNCTION In he mux: + i -2. AINO-AINS 1-6 27 1-6 2.7 es to the mux: OV to +5V unipolar, -2.5V to AING-AIN7 78 8.9 Soe elar to the mux: OV to +5V unipolar, -2.5V to MUXOUT 7 8 Muliplexer Output ADCIN 8 9 Analog Input to track-and-hold REFIN 9 10 9 10 Reference Input AGND 10 11 10 11 Analog Ground REFOUT 11 13 11 13 -5V Reference Output REFADJ 12 14 12 14 -5V Reference Adjust. Connect to Vop if not required. OFFADJ 13 16 13 15 Offset Adjust. Connect to Vpp if not required. MODE 14 16 14 16 Interface Mode Select pin. Vss 15 17 15 17 Negative Supply: -15V or -12V D1i1-D8 16-19 18-21 16-19 18-21 Three-State Data Outputs, MSB = D11 DGND 20 22 20 22 Digital Ground D7-DO 21-28 24-31 21-28 24-31 Three-State Data Outputs, LSB = DO CLKIN 29 32 29 32 Clock Input, TTL/CMOS compatible HBEN 30 33 30 33 High-Byte Enable Input RD 31 36 31 35 READ Input WR 32 36 32 36 WRITE Input (MODE = 1 or Open) READY Output (MODE = 0) cS 33 37 33 37 CHIP-SELECT Input BUSY 34 38 34 38 BUSY Output DIFF 35 39 35 39 Single-Ended Mode: DIFF = 0, Differential Mode: DIFF = 1 BIP 36 40 36 40 Unipolar Mode: BIP = 0, Bipolar Mode: BIP = 1 A0-A2 37-39 41-43 37-39 41-43 Multiplexer Channel Address Input: A2 = MSB, AO = LSB VpD 40 44 40 44 Positive Supply: +5V Input (substrate connected to Vpp) N.C. 1,12, 1,12, No Connect. No internal connection. Leave pin open or 23,34 23,34 connect to AGND. MAXIM 5 KS ELXVW/OSILXVUWMAX180/MAX181 Complete, 8-Channel, 12-Bit Data-Acquisition Systems +0V CL I DGND a. High-Z to Vou (tov) and VoL to Vou (Iepv) b. High-Z to Voi (tov} and Vou to VoL (tenv) +5V 3k DN ON 3k 10pF 10pF wal I DGND a. Vou to High-2 b. VoL to High-Z Figure 1. Load Circutts for Access Time A/D Converter Operation The MAX180/MAX 181 use successive approximation and input track-and-hold (T/H) circuitry to convert an analog signal to a series of 12-bit digital output codes. The control logic interfaces easily to uPs, requiring only a few passive components for most applications. The T/H does not require an external capacitor. Figure 3 shows the MAX180 typical operating circuit. Starting a Conversion Regardless of the mode or interface selected, the follow- ing Sequence occurs once conversion is started: 1. The data inputs that configure the data-acquisition system (DAS) latch, and the interface signals the wP that a conversion has started. 2. The mux directs the selected input signal to the T/H input. 3. Afixed time delay allows the T/H to acquire the signal. In all modes except asynchronous hold, this delay is 3 clock cycles. In asynchronous hold, the pP controls this delay. 4. The T/H switches to hold mode. The T/H output delivers a stable, single-ended sample of the input signal to the A/D input. 5. The successive approximation cycle begins. The ADC tests and sets each of the 12 bits in turn, from most to least significant. Bit decisions occur on the CLKIN falling edges, for a total of 12 clock cycles. 6. Output data is latched by the output registers, and the interface signals the uP that conversion is com- plete and data is available. Figure 2. Load Circuits for Bus-Relinquish Time +5V MIXED MULTIPLEXER * CONNGURATION_[12_|13 o lL | SHOWN REFADJ OFFAD! Voo Our | 47uF WoT . : = SE. CHO m] AINO REFOUT 2 AEFIN | 2 SE.CH1 AINt _[otur_] 47a ; MAXIM * DIFF.CH2+ 4 ang MAX180 DIFF. CH2- AIN3 DIFF, CH3+ AIN4 DIFF. GH3- | AINS 7 DIFF. CH4+ 4 AING 8 DIFF. CH4- } AIN? DATA 0-011 {Tine A AGND DGND Vss 39 10 20 15 45y Oapr | 4.7uF ma : CONFIGURATION IS 40-PIN DIP Figure 3. MAX180 Typical Operating Circuit MA AXLANComplete, 8-Channel, 12-Bit Data-Acquisition Systems Analog Input - Track-and-Hold Figure 4 shows the equivalent input circuit, illustrating the sampling architecture of the ADCs analog comparator. The input capacitance acts as the hold capacitor and is charged by the input signal with every A/D conversion. The capacitance is charged through an internal 1kQ resistor in series with the input. Note: Figure 4s switches represents both the mux and hold switches. TRACK-AND-HOLD AND COMPARATOR AIN_ (aaa TRACK ADCIN (MAX181) Rin + CHoLD mA sry 5pF AIN_ (DIFF =1 HOLD CSwitcH AGNO (DIFF=0} iN P COMPARATOR TRACK Figure 4. Equivalent Input Circuit When in single-ended input mode and between conver- sions (BUSY = High), the selected analog input is con- nected to the hold capacitor (track mode). When a conversion starts, CHOLD disconnects from the + T/H input, thus sampling the input (see "Digital Interface" section for percise T/H timing). When the switch closes at conversion end, CHOLD reconnects to the input and charges to the input signal. The loading effect of the analog inputs on the signal is such that a high-speed input buffer is usually NOT needed because the ADC disconnects from the input during the actual conversion. The previous explanation applies for the differential input mode if "input" is replaced by AIN+ and analog ground is replaced by AIN-. In the differential input mode, AO-A2 select the input channel pairs (Table 1). Only the signal side of the input channel is held by the T/H; the return side must remain stable within +0.5LSB (+0.1LSB for best results) during the conversion. For example, a common- mode signal of 0.33Vp-p at 60Hz results in a maximum error of 0.5LSB. The T/H starts tracking when the ADC is deselected (BUSY = High). Hold mode begins 3 clock cycles after a conversion is initiated in all but the Asynchronous Hold Mode. Variation in hold-mode delay from one conversion to the next (aperture jitter) is less than 100ps. Figures 7-11 detail the T/H and interface timing for the various interface modes. The time required for the T/H to acquire an input signal is a function of how quickly the input capacitance is charged. If the input source impedance is high, the acquisition time lengthens and more time must be al- lowed between conversions. Acquisition time is calcu- lated by: tACQ = 10(Rs + Rin)20pF (but never less than 1.875ys) where RIN = 1kQ, and Rs = source impedance of the input signal. Input Bandwidth The A/D's input tracking circuitry is excellent for tracking large signals and wide bandwidths and does not exhibit the slew-rate limitations of many other ADC T/Hs. The MAX180/MAX181 T/Hs full-power bandwidth is typically 6MEz; this allows the measurement of periodic signals with bandwidths exceeding the ADCs sample rate (100kHz) using under-sampling techniques. Important note: If under-sampling is used to measure high-fre- quency signals, take special care to avoid aliasing errors. Without adequate input filtering, high-frequency noise could be aliased into the measurement band. Reference The MAX180/MAX181 operate with either the internal reference or an external -5V reference. In both cases, REFIN must be bypassed to AGND with a 47uF electro- lytic capacitor in parallel with a 0.1p.F ceramic capacitor to minimize noise and maintain a low impedance at high frequencies. REFIN is connected directly to the internal DAC, and the current load varies between OmA and 1mA during conversion. Internal Reference The internal reference is buffered through an amplifier whose output connects to REFOUT. To operate the MAX180/MAX181 with the internal reference, connect REFIN to REFOUT. Do not connect a resistor between the bypass Capacitors and REFIN. The reference buffer am- plifier can sink 5mA for external loads. Adjust the refer- ence output at REFADJ (Figure 14). External Reference With a -5V external reference, bypass REFIN to AGND with a 47uF electrolytic capacitor in parallel with a 0.1uF ceramic capacitor. The reference source impedance must be less than 0.2Q and must be able to sink the internal DAC load of 1mA. Connect REFOUT to Vss and REFADJ to VppD to prevent noise. If REFIN is driven above AGND during power sequencing, latchup can occur. Connect a Schottky clamp diode (IN5817) to prevent REFIN from substantially exceeding AGND. MA AXU/VI LS LXVIW/OSILXVINMAX180/MAX181 Complete, 8-Channel, 12-Bit Data-Acquisition Systems Table 1. Address vs. Channel Selection (see Figure 4) A2 Al AO | SE/DIFF| AINO | AIN1 | AIN2 | AINS | AIN4 | AINS | AING | AIN? | COM MAX180/MAX181| 0 0 0 0 + - MAX180/MAX181| 0 0 1 0 + - MAX180/MAX181| 0 1 0 0 + - MAX180/MAX181| 0 1 | 0 + - MAX 180/MAX181 1 0 0 0 + - MAX 180/MAX181 1 0 1 0 + - MAX180 1 1 0 0 + - MAX181 1 1 0 0 MUXOUT CONNECTED TO AGND +,- MAX180 1 1 1 Q | | | | + ~ MAX181 1 1 1 0 CH 0-5, AND MUXOUT ARE OPEN - MAX180/MAX181| 0 0 0 1 + - MAX180/MAX181| 0 0 1 1 - + MAX180/MAX181| 0 1 0 1 + - MAX180/MAX181| 0 1 1 1 - + MAX 180/MAX181 1 0 Q 1 + - MAX180/MAX181 1 0 1 1 - + MAX 180 1 1 0 1 + - MAX180 1 1 1 1 - + MAX181 1 1 a) 1 MUXOUT CONNECTED TO AGND +,- MAX181 1 1 1 1 CH 0-5, AND MUXOUT ARE OPEN - MAX180 WRITE X X X X X X X DIFF BIP A? Al AO READ 011 D10 D9 D8 D7 D6 DS D4 03 D2 D1 O0 BUSY }----- STATUS OUPUT ts + WR } CONTROL RD |} [INPUTS DIFF = 1 HBEN A0 Al DIFF =0 A2 BIP -}_ MAX187 DIFF MUXOUT ADCIN DO/B 01/9 02/10 03/11 D4 TH DS TOP DATA BUS DIFF = 1 DIFF =0 D6 D? D8 Dg D10 D1 Figure 5. Multiplexer channel configuration Figure 6. Input/Output Port Mode (12-Bit-Wide Data Bus Shown) MA MAXIMComplete, 8-Channel, 12-Bit Data-Acquisition Systems ke tit n 7 We ~ 7 < ic 4 7 DATA IN DATA VALID f pata vaup 7 gy + ; he ee tt? DATA OUT NEW DATA D11-D0 10 TT TRACK. _J Figure 7a. Input/Output Port-Mode timing, parallel read (MODE = 1, HBEN = 0). yf 1 HBEN j el tig be eH cS |_{-_ 4 4 4 1 f_ {3 m fe 4 * t3 le {4 WR y- 11s > ts k rt qT tte ee ety ee RO be tf) om le 111 w \ t tp e [12 m BUSY 1 iconv | le by L > 7 |__ DATA IN ML DATA VALIO yt DATA VALID rl tg ly > ig + tT he tT e- DATA OUT r NEW DATA + NEW DATA > te |, _D?-D0 he _11-D8 HOLD ~------- =e 16 TRACK [ el acuxke 3 L * CLK Figure 7b. Input/Output Port-Mode timing, two-byte read (MODE = 1). MAAXIAA 9 LS LXVW/O8SELXVIMAX180/MAX181 Complete, 8-Channel, 12-Bit Data-Acquisition Systems ts tis 3 DATA VALID DATA VALID DATA IN ta t14 +>) te hie ti? OLD DATA 011-D0 NEW DATA 1-D0 DATA OUT WR {READY OUTPUT) Figure 8a. Slow Memory Mode timing, parallel read (MODE = 0, HBEN = 0). HBEN 1 tig be he _| te he ig ha he pe cs /_ 4 + * te ~} we 12 ~| ty tp l__ w- be ty] RD yy ft 1 f 1 BUSY | 1 5 tony Lo tts J tp ke > 3 4 3 fe DATAIN "St DATA VALID-K NE DATA VALID YE DATA VALID a ha ~ 124 ~ iF e 14 bee tt4 > 16 He hi7 DATA OUT OLD DATA NEW DATA 1 (NEW DATA 07-0 ~ -DF-DO tie be 011-8 ___ssWR q (READY OUTPUT) t / * re feo 129 w} be oT TRACK ~_+4 | 3cik fe Figure 8b. Slow Memory Mode timing, two-byte read (MODE = 0). 10 MAXILAAComplete, 8-Channel, 12-Bit Data-Acquisition Systems co 7) Ro * t ! tb ft j++ ~ [2 | RD + + + t Le t}] + tn BUSY " ~ {CONV {CONY -_+J K 7 7 115 w [15 (a mtg ee DATAIN YF DATAVALID \E_DATAVALID K | ta ~ 4 DATA QUT F OLDDATA | { NEW DATA + | 16 011-00 ti? - eH [15 D11-D0 o tt7 - WR (READY OUTPUT) 4 / + | 120 e{ fet {29 *| oo fe TRACK " 3 CLK . | 3CLK lL. Figure 9a. ROM Mode timing, parallel read (MODE = 0, HBEN = 0). HBEN -) lr tia ) ta fe ) ta f= tie >| ~ a >) hs cs 1 t 4 f a fo > ti je tp et ty Ae 12 | ty J >{ 2 RD 1 I 1 J kK J tg +| < ti tii + tit BUSY r tcony I * LW t5 tis LG tb *| 13 > _ 13 DATA IN Farnimo X DATA VALID | XL DATA VALID ty tia tq + sta D7-00 D11-D8 D?-D0 DATA OUT 4 OLDDATA | > NEW DATA NEW DATA Lo tig | w he 7 re * tig lhe ty WR 7 (READY OUTPUT) L j \ 20 to} et HOLD a TRACK | JC | 3CLK 3 CLK Figure 9b. ROM Mode timing, two-byte read (MODE = 0). MAXIAA "1 LS EXVW/O8S-LXVINMAX180/MAX181 Complete, 8-Channel, 12-Bit Data-Acquisition Systems HBEN N cs KR ts > |4 ph- * WR tb ko [5 m ~~ yOTt(C;SN le 6 __,\___ | tis tg / RD Vv yg tconv athe eke t10 be 11 >} BUSY 17 ee ty DATAIN +} DATA VALID K DATA VALID el tg | lg ete ey 7 DATA OUT ca NEW DATA +____ 011-00 HOLD r..OOt~Y TRACK Figure 10a. Asynchronous Hold Mode timing, parallel read (MODE = open circuit) HBEN 1 K 7 A + ts ed __ rt pe sl4 WR b yoo Y x | tte to a t5 tte eb te le RD \ yop YY you yo a, a ; CONV ta {1 oe me (19 oe tet a 10 l_ _ BUSY tia | ov | DATAIN YL DATA wok ME DATA VALID -X lg | Ve | 8 bgp he~ fe ~ 7 ti6w ey h17 DATA OUT NEW DATA NEW DATA D?-D0 D11-D8 HOLD +d TRACK Figure 10b. Asynchronous Hold Mode timing, two-byte read (MODE = open circuit) 12 MAXIMComplete, 8-Channel, 12-Bit Data-Acquisition Systems te + b3 te2 2 220ns: Conversion takes 15 clocks te3 2O0ns: Conversion takes 16 clocks * A WR rising edge starts a conversion in Input/Output Port Mode (Figure 7a, 7) Figure 11. CS, RD, or WR to CLK Setup and Hold Time for Synchronous Operation Digital Interface Input/Output Port Mode (MODE = 1) In this mode, data inputs and outputs are usually con- nected together (Figure 6}, and the uP writes the config- uration data to the DAS internal register with a write instruction (Figure 7). This starts a conversion, as indi- cated by the high-to-low transition of BUSY. The mux connects the selected input channel to the T/H, which acquires the signal during the first 3 clock cycles. On the falling edge of the 3rd clock, the T/H switches to hold mode, and the A/D conversion starts. 15 clock cycles after WR goes high, BUSY goes high, and the conversion result latches into three-state output buffers. The wP can then access the conversion result with a read instruction. For 16-bit bus operation, HBEN = 0, and the 12-bit result is read directly. For 8-bit bus operation, HBEN = 0 during the conversion, and the read instruction returns the 8 LSBs. A second read with HBEN = 1 returns the 4 MSBs in the low nibble. Note: In any mode, HBEN = 1 disables conversion start. The DAS internal register is 5 bits wide: 3 bits for the analog- channel address, 1 bit for single-ended/differential mux operation, and 1 bit for unipolar/bipolar A/D operation. Slow Memory Mode (MODE = 0} The DAS appears to the pP as memory or as a slow peripheral in memory mode. The 5 configuration bits can be preset by an external data latch, a decoded device address, or any external selection logic. A read instruction initiates a conversion as shown in Figure 8. In this mode, the WR input functions as the RDY output and goes low when CS goes low. BUSY goes low after RD goes low, indicating the beginning of a signal acquisition cycle, and can be used to place the pP into a wait state. When the conversion is complete, BUSY releases the uP from its wait state. The wP can then access the conversion result with a read instruction. For 16-bit bus operation, HBEN = 0, and the 12-bit result is read directly. For 8-bit bus operation, HBEN = 0 during the conversion, and the read instruction returns the 8 LSBs. A second read with HBEN = 1 returns the 4 MSBs in the low nibble. Note: In any mode, HBEN = 1 disables conversion start. ROM Mode, Paralie!l Read (MODE = 0) ROM mode avoids using uP wait states. A conversion starts with a read instruction, and the 12 data bits from the previous conversion appear at D11-D0. The data from the first read in a sequence is often disregarded when ROM mode is used. A second read accesses the results of the first conversion and starts a new conver- sion. The time between successive reads must be longer than the conversion time of the MAX180/MAX181 (Figure 9a, 16-bit bus). ROM Mode, 2-Byte Read (MODE = 0) As in memory mode, only D7-DO are used for a 2-byte read. A conversion starts with a read instruction when HBEN is low. At this point, the data outputs contain the 8 LSBs from the previous conversion. Two more read op- erations are needed to access the conversion result. The first, with HBEN high, accesses the 4 MSBs with 4 leading zeros. The second read, with HBEN low, outputs the 8 LSBs and starts a new conversion. Figure 9b (8-bit bus) details this mode. Asynchronous Hold Mode (MODE = Open) Asynchronous hold mode is helpful when a precise or repeatable sample timing is required. Asynchronous hold is very similar to the 1/O port mode, except two write instructions are required. The first write, with HBEN = 1, configures the MAX180/MAX181 and con- nects the selected channel to the T/H input; the second write, with HBEN = 0, places the T/H into hold and starts the conversion. In other words, the three-clock cycle delay for T/H acquisition can be changed by controlling when the second write instruction occurs. The falling edge of the second WR pulse places the T/H into hold {Figure 10). 13 MA AXLAWI KS LXVW/O8-LXVINMAX180/MAX181 Complete, 8-Channel, 12-Bit Data-Acquisition Systems External Ciock The range for the external clock duty cycle is between 20% and 80%. A precise square wave is not required. Clock and Control Synchronization For best analog performance, the MAX180/MAX181 clock should be synchronized to the RD, WR, and CS inputs (Figure 11) with at least 100ns separating convert start from the nearest clock edge. This syn- chronization ensures that transitions at CLKIN are not coupled to the analog input and sampled by the T/H. The magnitude of this feedthrough is only a few millivolts. If CLKIN and convert start (CS, WR and RD) are asynchronous, frequency components caused by mixing of the clock and convert signals can in- crease the apparent input noise. When the clock and convert signals are synchronized, small end-point errors (offset and full-scale) are the most that can be generated by clock feedthrough, but even these errors are eliminated by ensuring that the start of a conversion (RD or WR and CS falling edge) does not occur within 100ns of a clock transition (Figure 11). Output Data Format The 12 data bits can be output either in full parallel or as two 8-bit bytes. Table 2 shows the data-bus output format. To obtain parallel output for 16-bit uPs, HBEN is tied low. Note: The output data, D11-D0, is right-justified (i.e. DO, the LSB, is the right-most bit in the 16-bit word). A two-byte read makes use of outputs D7-DO. Byte selection is controlled by HBEN, which multiplexes the data outputs. When HBEN is low, the lower 8 bits appear at the data outputs. When HBEN is high, the upper 4 bits appear at DO-D3 with the leading 4 bits low in locations D4-D7. Note: The 4 MSBs always appear at D11-D8 when the outputs are enabled, regardless of the state of HBEN. Table 2. Data-Bus Output, CS & RD = LOW Application Hints Initialization After Power-Up In some applications, power is removed from the ADC during periods of inactivity to conserve power. This is increasingly common in battery-powered systems. To initialize the MAX180/MAX181 at power-up, execute a read operation with HBEN low, ignoring the data out- puts. Minimizing System-induced Noise The MAX180/MAX181 are insensitive to most noise sources, especially when the layout, bypass, and grounding recommendations are followed . The following practices should also be considered: 1. Minimize digital activity during conversion, especially activity that is asynchronous with the MAX180/MAX181 clock. 2. Avoid data-bus activity within +20ns of the CLKIN falling edge. {f the data bus connected to the ADC is active during a conversion, coupling from the data pins to the ADC comparator can cause errors. Using slow-memory mode avoids this problem by placing the uP in a wait state during the conversion. In ROM mode, the bus should be isolated from the ADC using three-state drivers if the data bus is active during the conversion. In ROM mode, the ADC generates considerable digital noise when RD or CS go high and the output data drivers are disabled after conversion start. This noise can affect the ADC comparator and cause large errors if it coincides with the SAR latching a comparator decision. To prevent this, RD and CS should be active for less than one clock cycle. If this is not possible, RD or CS should go high on a rising edge of CLKIN because the comparator output is latched on the falling edge of CLKIN. DIP Pin # Pin 16 | Pint7 | Pin18 | Pin19 | Pin21 | Pin22 | Pin23 | Pin24 | Pin25 | Pin 26 | Pin27 | Pin 28 Pin Labelt Dil D1G D9 D8 D7 D6 D5 D4 D3 D2 D1 DO HBEN = LOW** O11 D160 DS D8 D7 D6 D5 D4 D3 D2 D1 DO HBEN = HIGH** D11 D10 D9 D8 LOW LOW LOW LOW Dt D10 D9 D8 Note: * 011-D0 are the ADC data output pin names. 011-D0 are the 12-bit conversion results. D11 is the MSB. 14 MAXIComplete, 8-Channel, 12-Bit Data-Acquisition Systems Layout, Grounding, Bypassing Use printed circuit boards for best system performance; wire-wrap boards are not recommended. The board lay- out should ensure that digital- and analog-signal lines are separated as much as possible. Do not run analog and digital (especially clock) lines parallel to one another or digital lines underneath the ADC package. Figure 12a shows the recommended system-ground con- nections. A single-point analog STAR ground should be established at AGND, separate from the logic ground. All other analog grounds and DGND should be connected to this STAR ground, and no other digital system grounds should be connected here. For noise-free operation, the ground return to the power supply from this STAR ground should be low impedance and as short as possible. The ADCs high-speed comparator is sensitive to high- frequency noise in the VDD and Vss power supplies. These supplies should be bypassed to the analog STAR ground with G. 1F and 47pF bypass capacitors. Minimize capacitor lead length for best supply noise rejection. If the 5V power supply is very noisy, connect a small (10Q) resistor to filter the noise (Figure 12b). Gain and Offset Adjustment Figure 13 plots the nominal unipolar I/O transfer function of the MAX180/MAX181. Code transitions occur halfway between successive integer LSB values. Output coding for unipolar operation is natural binary with 1LSB = 1.22mV (5V/4096). Figure 14 shows the bipolar-input transfer function, where output coding is twos-comple- ment. Vsg SUPPLY Vpp SUPPLY -12/-15V GND GND +5 + + R** + Vss AGND DGND Vop GNO +5V MAXIM DIGITAL MAX180/1 CIRCUITRY AIO | [7] fo pe AINI [2 | 39| 42 0 ui T AIN2 | [3 | 38] | At = = AINS | [ 4 | 37] | AO AINA) [ 5 | 36} | BIP AINS | [ 6 | 35] | DIFF ANN | [7 | 34] | BUSY AIN? | [3 | 33] | S ou te ian || Toni AGND [to] 31] | AO = = REFOUT| [14] 30 | HBEN REFADL | [12| 29] | CLKIN OFFADY | [13] 2] | Do MODE | [14] [27] | 1 arto 1 a] T T b11| [16 [25] | D3 = = pio] [17] 2a] | D4 D9] [19] 23] | 0S b8} [19 22] | 06 pene [20] 2] | OF DIP * *Star* ground ** R= 10Q optional for filtering a noisy Vo supply. Figure 12a. Recommended Grounding and Ground Piane Figure 12b. Power-Supply Grounding 15 MAAXIM LS LXVW/O8SEXVINMAX180/MAX181 Complete, 8-Channel, 12-Bit Data-Acquisition Systems If offset and gain adjustments are not desired, connect OFFADJ and REFADJ to Vpp. Figure 15s circuit provides +1.2% (450 LSBs) of adjustment range for gain and +0.44% (+18LSBs) cf adjustment range for offset. This is ideal for applications that require gain (full-scale range) or offset adjustment. If the adjustment inputs are used, bypass to AGND with a0. 1pF capacitor. Offset should be adjusted before gain. For the OV to 5V input range, apply LSB (0.61mV) to the analog input, and adjust R1 so the digital output code changes between 0000 0000 0000 and 0000 0000 0001. To adjust full scale, apply FS - 1LSB (4.99817V), and adjust R2 until the output code changes between 1111 1111 1110 and 1141 11111111. There may be a slight interaction between the adjustments. To adjust bipolar (+2.5V) offset, apply LSB (0.61mV) to the analog input, and adjust R1 until the output code switches between 0000 0000 0000 and 0000 0000 0001. For full scale, apply FS - 1LSB (2.49817V) to the input, and adjust R2 so the output code switches between 0111 1111 1110 and 0114 1111 1111 (Figure 15). There may be some interaction between these adjustments. If an external reference is used, adjust gain by varying the value of the reference instead of R2. Dynamic Performance Wide-bandwidth analog input and 100kHz throughput make the MAX180/MAX181 ideal for wideband-signal processing. To support these and other related applica- tions, fast Fourier transform (FFT) test techniques guar- antee the ADC's dynamic frequency response, distortion, and noise at the rated throughput. Specifically, this in- volves applying a low-distortion sine wave to the ADC input and recording the digital conversion results for a specified time. The data is then analyzed using an FFT algorithm that determines its spectral content. Conver- sion errors are seen as spectral elements outside of the fundamental input frequency. ADCs have traditionally been evaluated by specifications such as zero and full-scale error and integral (INL) and differential (DNL) nonlinearity. Such parameters are widely accepted for specifying performance with DC and slowly varying signals, but less useful in signal-process- ing applications where the ADCs impact on the system transfer function is the main concern. The significance of the various DC parameters does not translate well to the dynamic case, so different tests are required. OUTPUT CODE FULL-SCALE no4ut TRANSITION 11...110 11... 101 | | | | / | | / | | / ! FS 18), | ) / 1LSB = 4096 | oo...011 I | o0...010 \ 00... 001 oo...099 LL, 4 4 jo4}> 01 2 38 ' FS AIN INPUT VOLTAGE (LSBs) FS - 3/2LSB G g 2d p>) O11... O11... 000... 000... 000... 111... 111... W1... 100 100... +& S ov 4FS- 1LSB AIN INPUT VOLTAGE (LSBs) Figure 13. MAX180/MAX181 Unipolar Transfer Function 16 Figure 14. MAX180/MAX 181 Bipolar Transfer Function MA MAXIMComplete, 8-Channel, 12-Bit Data-Acquisition Systems Signal-to-Noise Ratio and Effective Number of Bits Signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental frequency to the RMS am- plitude of all other ADC spectral components, excluding harmonics: The output band is limited to frequencies above DC and below one-half the ADC sample (conver- sion) rate. This band includes both distortion and noise components. For this reason, the signal-to-noise and distortion ratio (SINAD) is a better measure of the ADC's performance. The theoretical minimum ADC noise is caused by quan- tization error and is a direct result of the ADCs resolution: SNR = (6.02N + 1.76)dB where N is the number of bits of resolution. A perfect 12-bit ADC can therefore do no better than 74dB. Figure 16 shows the result of sampling a pure 10kHz sinusoid at a 100kHz rate with the MAX180/MAX181. An output FFT plot shows the relative output amplitude at discrete spectral frequencies (Figure 16). By transposing the equation that converts resolution to SNR, we can determine the effective resolution (effective number of bits) the ADC provides from the measured SNR: N = (SNR - 1.76)/6.02. Figure 17 shows the effective number of bits as a function of the input frequency for the MAX180/MAX181. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all the harmonics (in the frequency band above DC and below one-half the sample rate} to the RMS amplitude of the fundamental frequency. This is ex- pressed as: THD = 20Log Nw an V3 ra VN 2) V1 where V1 is the fundamental RMS ampiitude, and V2 to VN are the amplitudes of the 2nd through Nth harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range is the ratio of the ftundamen- tal RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually this peak occurs at some harmonic of the input frequency. But if AMPLITUDE (dB) i o So -80 -100 l 700 1250 25.00 3750 50.00 f= 1OKH2 FREQUENCY (kHz) OFFADJ ANAXLAA MAXT80 REFIN MAx787 REFOUT REFADJ AGND CONFIGURATION IS 40-PIN DIP Figure 16. FFT Plot for the MAX180/MAX181 12 10 EFFECTIVE BITS 10 100 1M 10M INPUT FREQUENCY (Hz) Figure 15. Offset and Gain Adjustment PAAXISV Figure 17. MAX180/MAX181 Effective Bits vs, Inout Frequency 17 LSLXVW/O8S LXVMAX180/MAX181 Complete, 8-Channel, 12-Bit Data-Acquisition Systems Typical Applications 64k 32k 16k 8k 4k 2k tk 1k NOTE: USE ADDRESS 0-6. ADDRESS 7 FLOATS MUXOQUT. +15V +5V Ifa: + sd Onur | oe Are Ty lta ao LO-twF_]. 47H = 1S 1 [PREFADS OFFADJ oo >Y Aino pen rerout -1 IN4148 ANALOG | YAN INPUTS *) 4J Aina arrn {Se >5l Aina Lape] 47uF tk 5T ans * ADCIN t L131 wuxout 6 - ANAXIAA 99 MAAXIAN ja MAX187 CLKIN fe 13 MAX400, 4 HBEN f-22 4 8 move f+!4t st D DET 33 t k#-2+} a $2 ao |. 32 ENP 24 45V wie * aysy }t_- 33 AAAXIAA DIFF fe 32 MAX328 aip [25 sa 16.19, 21...28 D0-D11 DATA LINES AO 8 At 38 A2 jy 5 AGND DGNO Vs 1 10 20 (15 AO th rotrt amr PY $7 a LS GAIN SELECT Lf (GAIN = 1 TO 128) = sa ao 15 Ve GND 3} 14 Lb CONFIGURATION 1S FOR DIP Figure 18a. MAX181 operating as a 6-channel programmable gain ADC. Gains are 1, 2, 4, 8, 16, 32, 64, and 128. 18 MA AXIL/MComplete, 8-Channel, 12-Bit Data-Acquisition Systems +15V +5V 1 47pF. O1pF 47uF O4pF_] Tz fe [2 fo L tL = REFADJ OFFADJ Vpo ' C1 muxour =REFOUT}-1# WH @ 1N4148 8] apcin REFIN TORE? 47uF aw : > tk AAAXIAA > Lino. MAX187 3 aA, VIN 4) 16k AIN1 CLKIN kX MAX400 8k AIN2 MODE f+] 4k AIN3 _| 32 2k AIN4 1k AIN5 DATA 1k 37 LINES AGND _DGND vss 10 0.115 Avntlanr MUXGUT 7FLOATSMUXOUT I LJ CONFIGURATION IS FOR DIP Figure 18b. MAX181 operating as a single-channel! programmable gain ADC. Gains are 1, 2, 4, 16, and 32. Pin Configurations (continued) =ttq_teneterze eet ae eo 5 fede fs fol [ e AINS L7 | 39 | DIFF (MUXOUT)** AINS* [8 | fag] BUSY (ADCIN)"* AIN7 [_9 | MAXIM [a7] CS REFIN Lio | MAX180 36 | WR AGND [17 | MAX181 [35] RD ne, [72] 134) NO. REFOUT [13 | [33] HBEN REFADJ [14 | [32] CLKIN OFFADJ [45] 31] po move Ls] [30] 01 vss [17 | [29] 2 hal la] 20) |21 lea} leal 24] 25] j26] |27) |28 BE88es5e858 * MAX180 ONLY ** MAX181 ONLY PLCC MAXILAA 19 LE LXVI/OSLXVINMAX180/MAX181 Complete, 8-Channel, 12-Bit Data-Acquisition Systems _ Ordering Information (continued) Chip Topography * Contact factory for dice specifications. ** Contact factory for availability and processing to MIL-STD-883. AIN4 AIN2 PART TEMP.RANGE PIN-PACKAGE ERROR AINO #2 #0 (LSBs) MAX180CCQH OCto+70C 44PLCC +1 AINS, | ; (MUXOUT)** MAX180CC/D 0C to +70C Dice* +4 AING* Meee MAX180AEPL -40Cto+85C 40PlasticDIP -+1/2 arta MAX180BEPL -40Cto+85C 40PlasticDIP +1 , H-HBEN __9.164" MAX180CEPL -40Cto+85C 40PlasticDIP +1 CLKIN (4.166 mm) MAX180AEQH -40Cto+85C 44 PLCC +1/2 REFOUT MAX180BEQH -40Cto+85C 44 PLCC +4 MAX180CEQH -40Cto+85C 44 PLCC +4 MAX180AMJL -58Cto+126C 40CERDIP +1/2 MAX180BMJL -55Cto+125C 40CERDIP* 44 D10} 08] 07 | OS Dll DSDGND'D6 D4 MAX180CMJL -55C to +125C 40CERDIP +14 MAX181ACPL OCto+70C 40PlasticDIP _ +1/2 MAX181BCPL OCto+70C 40PlasticDIP +1 0.160" _ (4.064 mm) MAX181CCPL OC1o+70C 40PlasticDIP +1 - maxieo MAX181ACQH OCto+70C 44PLCC +1/2 * MAX181 MAX181BCQH OCto+70C 44PLCC + MAX181CCQH OCto+70C 44PLCC +1 MAX181CC/D O0Cto+70C _Dice* +1 MAX1BiAEPL -40Cto+85C 40PlasticDIP = #4/2 MAX181BEPL -40Cto+85C 40PlasticDIP = $4 MAX{81CEPL -40Cto+85C 40PlasticDIP +4 MAX181AEQH -40C to +85C. 44 PLCC +1/2 MAX181BEQH -40Cto+85C 44PLCC +1 MAX181CEQH -40Cto+85C 44PLCC +1 MAX181AMJL -55Cto+125C 4OCERDIP +14/2 MAX181BMJL -55C to +125C 40CERDIP 41 MAX181CMJL -55C to +125C 40CERDIP* +4 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 1991 Maxim Integrated Products Printed USA Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 maxim is a registered trademark of Maxim Integrated Products.