MC34071,2,4,A MC33071,2,4,A High Slew Rate, Wide Bandwidth, Single Supply Operational Amplifiers Quality bipolar fabrication with innovative design concepts are employed for the MC33071/72/74, MC34071/72/74 series of monolithic operational amplifiers. This series of operational amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/s slew rate and fast setting time without the use of JFET device technology. Although this series can be operated from split supplies, it is particularly suited for single supply operation, since the common mode input voltage range includes ground potential (VEE). With A Darlington input stage, this series exhibits high input resistance, low input offset voltage and high gain. The all NPN output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink AC frequency response. The MC33071/72/74, MC34071/72/74 series of devices are available in standard or prime performance (A Suffix) grades and are specified over the commercial, industrial/vehicular or military temperature ranges. The complete series of single, dual and quad operational amplifiers are available in plastic DIP, SOIC and TSSOP surface mount packages. * Wide Bandwidth: 4.5 MHz * High Slew Rate: 13 V/s * Fast Settling Time: 1.1 s to 0.1% * Wide Single Supply Operation: 3.0 V to 44 V * Wide Input Common Mode Voltage Range: Includes Ground (VEE) * Low Input Offset Voltage: 3.0 mV Maximum (A Suffix) * Large Output Voltage Swing: -14.7 V to +14 V (with 15 V Supplies) * Large Capacitance Drive Capability: 0 pF to 10,000 pF * Low Total Harmonic Distortion: 0.02% * Excellent Phase Margin: 60 * Excellent Gain Margin: 12 dB * Output Short Circuit Protection * ESD Diodes/Clamps Provide Input Protection for Dual and Quad http://onsemi.com 8 1 8 SO-8 D SUFFIX CASE 751 1 P SUFFIX CASE 626 PIN CONNECTIONS Offset Null 1 Inputs VEE 8 NC 2 - 7 3 + 6 VCC Output 5 Offset Null 4 (Single, Top View) Output 1 1 2 Inputs 1 3 VEE VCC Output 2 8 7 - + 6 - + 4 Inputs 2 5 (Dual, Top View) 14 14 1 SO-14 D SUFFIX CASE 751A 1 P SUFFIX CASE 646 14 1 TSSOP-14 DTB SUFFIX CASE 948G PIN CONNECTIONS Output 1 Inputs 1 1 14 2 13 3 VCC 1 4 - + 4 5 Inputs 2 6 Output 2 - + Inputs 4 12 11 + - 2 3 + - 7 Output 4 VEE 10 9 8 Inputs 3 Output 3 (Quad, Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. Semiconductor Components Industries, LLC, 1999 October, 1999 - Rev. 2 1 Publication Order Number: MC34071/D MC34071,2,4,A MC33071,2,4,A Representative Schematic Diagram (Each Amplifier) VCC Q3 Q4 Q1 Q7 Q17 Q2 R1 R2 C1 D2 Bias Q8 - Q6 Q5 Q9 Q11 Q10 Q18 R6 R7 Output R8 Inputs + C2 D3 Q19 Base Current Cancellation Q13 Q15 Q14 Q16 Q12 D1 R5 R3 Current Limit R4 VEE/Gnd Offset Null (MC33071, MC34071 only) MAXIMUM RATINGS Rating Symbol Value Unit VS +44 V VIDR Note 1 V Input Voltage Range VIR Note 1 V Output Short Circuit Duration (Note 2) tSC Indefinite sec Operating Junction Temperature TJ +150 C Tstg -60 to +150 C Supply Voltage (from VEE to VCC) Input Differential Voltage Range Storage Temperature Range NOTES: 1. Either or both input voltages should not exceed the magnitude of VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 1). http://onsemi.com 2 MC34071,2,4,A MC33071,2,4,A ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, RL = connected to ground, unless otherwise noted. See Note 3 for TA = Tlow to Thigh) A Suffix Characteristics Symbol Input Offset Voltage (RS = 100 , VCM = 0 V, VO = 0 V) VCC = +15 V, VEE = -15 V, TA = +25C VCC = +5.0 V, VEE = 0 V, TA = +25C VCC = +15 V, VEE = -15 V, TA = Tlow to Thigh VIO Average Temperature Coefficient of Input Offset Voltage RS = 10 , VCM = 0 V, VO = 0 V, TA = Tlow to Thigh VIO/T Input Bias Current (VCM = 0 V, VO = 0 V) TA = +25C TA = Tlow to Thigh IIB Input Offset Current (VCM = 0 V, VO = 0V) TA = +25C TA = Tlow to Thigh IIO Input Common Mode Voltage Range TA = +25C TA = Tlow to Thigh VICR Large Signal Voltage Gain (VO = 10 V, RL = 2.0 k) TA = +25C TA = Tlow to Thigh AVOL Output Voltage Swing (VID = 1.0 V) VCC = +5.0 V, VEE = 0 V, RL = 2.0 k, TA = +25C VCC = +15 V, VEE = -15 V, RL = 10 k, TA = +25C VCC = +15 V, VEE = -15 V, RL = 2.0 k, TA = Tlow to Thigh VOH VCC = +5.0 V, VEE = 0 V, RL = 2.0 k, TA = +25C VCC = +15 V, VEE = -15 V, RL = 10 k, TA = +25C VCC = +15 V, VEE = -15 V, RL = 2.0 k, TA = Tlow to Thigh VOL Min Non-Suffix Typ Max 0.5 0.5 -- 3.0 3.0 5.0 -- 10 -- -- -- 100 -- -- -- 6.0 -- -- -- -- Typ Max 1.0 1.5 -- 5.0 5.0 7.0 -- 10 -- 500 700 -- -- 100 -- 500 700 50 300 -- -- 6.0 -- 75 300 -- -- -- Unit mV V/C nA nA V VEE to (VCC -1.8) VEE to (VCC -2.2) Output Short Circuit Current (VID = 1.0 V, VO = 0 V, TA = 25C) Source Sink Min VEE to (VCC -1.8) VEE to (VCC -2.2) V/mV 50 25 100 -- -- -- 25 20 100 -- -- -- 3.7 13.6 13.4 4.0 14 -- -- -- -- 3.7 13.6 13.4 4.0 14 -- -- -- -- 0.1 -14.7 -- 0.3 -14.3 -13.5 -- -- -- 0.1 -14.7 -- 0.3 -14.3 -13.5 V -- -- -- ISC V mA 10 20 30 30 -- -- 10 20 30 30 -- -- Common Mode Rejection RS 10 k, VCM = VICR, TA = 25C CMR 80 97 -- 70 97 -- dB Power Supply Rejection (RS = 100 ) VCC/VEE = +16.5 V/-16.5 V to +13.5 V/-13.5 V, TA = 25C PSR 80 97 -- 70 97 -- dB -- -- -- 1.6 1.9 -- 2.0 2.5 2.8 -- -- -- 1.6 1.9 -- 2.0 2.5 2.8 Power Supply Current (Per Amplifier, No Load) VCC = +5.0 V, VEE = 0 V, VO = +2.5 V, TA = +25C VCC = +15 V, VEE = -15 V, VO = 0 V, TA = +25C VCC = +15 V, VEE = -15 V, VO = 0 V, TA = Tlow to Thigh NOTES: 3. Tlow = -40C for MC33071, 2, 4, /A = 0C for MC34071, 2, 4, /A ID mA Thigh = +85C for MC33071, 2, 4, /A = +70C for MC34071, 2, 4, /A http://onsemi.com 3 MC34071,2,4,A MC33071,2,4,A AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, RL = connected to ground. TA = +25C, unless otherwise noted.) A Suffix Characteristics Symbol Slew Rate (Vin = -10 V to +10 V, RL = 2.0 k, CL = 500 pF) AV = +1.0 AV = -1.0 SR Non-Suffix Min Typ Max Min Typ Max 8.0 -- 10 13 -- -- 8.0 -- 10 13 -- -- -- -- 1.1 2.2 -- -- -- -- 1.1 2.2 -- -- GBW 3.5 4.5 -- 3.5 4.5 -- MHz Power Bandwidth AV = +1.0, RL = 2.0 k, VO = 20 Vpp, THD = 5.0% BW -- 160 -- -- 160 -- kHz Phase margin RL = 2.0 k RL = 2.0 k, CL = 300 pF fm -- -- 60 40 -- -- -- -- 60 40 -- -- Gain Margin RL = 2.0 k RL = 2.0 k, CL = 300 pF Am -- -- 12 4.0 -- -- -- -- 12 4.0 -- -- Equivalent Input Noise Voltage RS = 100 , f = 1.0 kHz en -- 32 -- -- 32 -- nV/ Hz Equivalent Input Noise Current f = 1.0 kHz in -- 0.22 -- -- 0.22 -- pA/ Hz Differential Input Resistance VCM = 0 V Rin -- 150 -- -- 150 -- M Differential Input Capacitance VCM = 0 V Cin -- 2.5 -- -- 2.5 -- pF Total Harmonic Distortion AV = +10, RL = 2.0 k, 2.0 Vpp VO 20 Vpp, f = 10 kHz THD -- 0.02 -- -- 0.02 -- % -- -- 120 -- -- 120 -- dB |ZO| -- 30 -- -- 30 -- W Setting Time (10 V Step, AV = -1.0) To 0.1% (+1/2 LSB of 9-Bits) To 0.01% (+1/2 LSB of 12-Bits) V/s s ts Gain Bandwidth Product (f = 100 kHz) Channel Separation (f = 10 kHz) Open Loop Output Impedance (f = 1.0 MHz) Deg dB Figure 1. Power Supply Configurations Single Supply Figure 2. Offset Null Circuit VCC Split Supplies 3.0 V to 44 V VCC+|VEE|44 V 2 VCC VCC 3 1 VCC Unit 1 7 - 6 + 1 5 4 2 2 10 k 3 3 VEE 4 VEE VEE Offset nulling range is approximately 80 mV with a 10 k potentiometer (MC33071, MC34071 only). 4 VEE http://onsemi.com 4 MC34071,2,4,A MC33071,2,4,A Figure 4. Input Offset Voltage versus Temperature for Representative Units VV IO , INPUT OFFSET VOLTAGE (mV) 2400 2000 1600 8 & 14 Pin Plastic Pkg SO-14 Pkg 1200 800 SO-8 Pkg 400 0 -55 -40 -20 0 20 40 60 80 0 -2.0 -4.0 100 120 140 160 -55 -25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C) Figure 5. Input Common Mode Voltage Range versus Temperature Figure 6. Normalized Input Bias Current versus Temperature VCC VCC/VEE = +1.5 V/ -1.5 V to +22 V/ -22 V VCC -0.8 VCC -1.6 VCC -2.4 VEE +0.01 VEE VEE -55 -25 0 25 50 75 100 125 125 1.3 VCC = +15 V VEE = -15 V VCM = 0 1.2 1.1 1.0 0.9 0.8 0.7 -55 -25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C) TA, AMBIENT TEMPERATURE (C) Figure 7. Normalized Input Bias Current versus Input Common Mode Voltage Figure 8. Split Supply Output Voltage Swing versus Supply Voltage 125 50 1.4 VCC = +15 V VEE = -15 V TA = 25C 1.2 VO, OUTPUT VOLTAGE SWING (Vpp ) I IB, INPUT BIAS CURRENT (NORMALIZED) 2.0 TA, AMBIENT TEMPERATURE (C) VCC 1.0 0.8 0.6 VCC = +15 V VEE = -15 V VCM = 0 4.0 V ICR , INPUT COMMON MODE VOLTAGE RANGE (V) I IB, INPUT BIAS CURRENT (NORMALIZED) P D , MAXIMUM POWER DISSIPATION (mW) Figure 3. Maximum Power Dissipation versus Temperature for Package Types RL Connected to Ground TA = 25C 40 30 RL = 10 k RL = 2.0 k 20 10 0 -12 -8.0 -4.0 0 4.0 8.0 12 0 VIC, INPUT COMMON MODE VOLTAGE (V) 5.0 10 15 VCC, |VEE|, SUPPLY VOLTAGE (V) http://onsemi.com 5 20 25 MC34071,2,4,A MC33071,2,4,A VCC VCC/VEE = +5.0 V/ -5.0 V to +22 V/ -22 V TA = 25C VCC VCC -1.0 VCC VCC VCC-2.0 Source VCC -2.0 VCC = +15 V RL = Gnd TA = 25C VCC-4.0 VEE +2.0 VEE +1.0 Sink VEE VEE Figure 10. Split Supply Output Saturation versus Load Current Vsat , OUTPUT SATURATION VOLTAGE (V) Vsat , OUTPUT SATURATION VOLTAGE (V) Figure 9. Single Supply Output Saturation versus Load Resistance to VCC 0 5.0 10 15 0.2 0.1 Gnd 0 100 20 1.0 k Figure 12. Output Short Circuit Current versus Temperature 0 60 VCC I SC, OUTPUT CURRENT (mA) Vsat , OUTPUT SATURATION VOLTAGE (V) Figure 11. Single Supply Output Saturation versus Load Resistance to Ground -0.4 -0.8 2.0 VCC = +15 V RL to VCC TA = 25C 1.0 Gnd 100 1.0 k 10 k RL, LOAD RESISTANCE TO VCC () 50 Source 30 20 VO, OUTPUT VOLTAGE SWING (Vpp ) Z O, OUTPUT IMPEDANCE ( ) 20 AV = 100 AV = 10 AV = 1.0 10 10 k 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125 28 VCC = +15 V VEE = -15 V VCM = 0 VO = 0 IO = 0.5 mA TA = 25C 0 1.0 k -25 Figure 14. Output Voltage Swing versus Frequency 50 AV = 1000 VCC = +15 V VEE = -15 V RL 0.1 Vin = 1.0 V 10 0 -55 100 k Sink 40 Figure 13. Output Impedance versus Frequency 30 100 k RL, LOAD RESISTANCE TO GROUND () IL, LOAD CURRENT ( mA) 40 10 k 100 f, FREQUENCY (Hz) 1.0 M 20 16 12 8.0 4.0 0 3.0 k 10 M http://onsemi.com 6 VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k THD 1.0% TA = 25C 24 10 k 30 k 100 k 300 k f, FREQUENCY (Hz) 1.0 M 3.0 M MC34071,2,4,A MC33071,2,4,A Figure 16. Total Harmonic Distortion versus Output Voltage Swing 0.4 THD, TOTAL HARMONIC DISTORTION (%) AV = 1000 0.3 VCC = +15 V VEE = -15 V VO = 2.0 Vpp RL = 2.0 k TA = 25C 0.2 AV = 100 0.1 AV = 10 AV = 1.0 0 10 100 1.0 k 10 k 4.0 3.0 AV = 1000 2.0 AV = 100 1.0 AV = 10 AV = 1.0 0 100 k 0 4.0 f, FREQUENCY (Hz) AVOL , OPEN LOOP VOLTAGE GAIN (dB) AVOL , OPEN LOOP VOLTAGE GAIN (dB) VCC = +15 V VEE = -15 V VO= -10 V to +10 V RL = 10 k f 10Hz 100 -25 0 25 50 75 100 125 Gain 60 Phase Margin = 60 40 20 Gain Margin = 12 dB 120 140 -10 1. Phase RL = 2.0 k 2. Phase RL = 2.0 k, CL = 300 pF -20 3. Gain R = 2.0 k L 4. Gain RL = 2.0 k, CL = 300 pF -30 VCC = +15 V VEE = 15 V V =0V TA = 25C -40 O 1.0 2.0 3.0 5.0 7.0 GBW, GAIN BANDWIDTH PRODUCT (NORMALIED) 100 Phase Margin = 60 0 3 160 180 4 2 10 90 VCC = +15 V VEE = -15 V VO = 0 V RL = 2.0 k TA = 25C 10 135 180 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M f, FREQUENCY (Hz) 20 , EXCESS PHASE (DEGREES) AVOL , OPEN LOOP VOLTAGE GAIN (dB) 1 45 Phase 0 1.0 Figure 19. Open Loop Voltage Gain and Phase versus Frequency 10 20 0 80 TA, AMBIENT TEMPERATURE (C) 20 16 100 104 96 -55 12 Figure 18. Open Loop Voltage Gain and Phase versus Frequency 116 108 8.0 VO, OUTPUT VOLTAGE SWING (Vpp) Figure 17. Open Loop Voltage Gain versus Temperature 112 VCC = +15 V VEE = -15 V RL = 2.0 k TA = 25C , EXCESS PHASE (DEGREES) THD, TOTAL HARMONIC DISTORTION (%) Figure 15. Total Harmonic Distortion versus Frequency 30 Figure 20. Normalized Gain Bandwidth Product versus Temperature 1.15 VCC = +15 V VEE = -15 V RL = 2.0 k 1.1 1.05 1.0 0.95 0.9 0.85 -55 f, FREQUENCY (MHz) -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) http://onsemi.com 7 100 125 MC34071,2,4,A MC33071,2,4,A Figure 21. Percent Overshoot versus Load Capacitance Figure 22. Phase Margin versus Load Capacitance 70 VCC = +15 V VEE = -15 V RL = 2.0 k VO = -10 V to +10 V TA = 25C 80 60 m , PHASE MARGIN (DEGREES) 40 20 0 10 100 1.0 k R 50 40 30 20 10 0 10 10 k 100 10 k CL, LOAD CAPACITANCE (pF) Figure 23. Gain Margin versus Load Capacitance Figure 24. Phase Margin versus Temperature 80 10 8.0 m , PHASE MARGIN (DEGREES) VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k to VO = -10 V to +10 V TA = 25C 12 6.0 4.0 2.0 0 10 100 1.0 k CL = 10 pF CL = 100 pF 60 40 CL = 1,000 pF 20 0 -55 10 k -25 0 75 A m , GAIN MARGIN (dB) 4.0 10 CL = 10 pF VEE = -15 V AV = +1.0 RL = 2.0 k to VO = -10 V to +10 V CL = 100 pF CL = 10,000 pF CL = 1,000 pF 0 25 50 75 125 100 125 R1 6.0 4.0 2.0 60 Gain 8.0 0 -25 100 70 12 VCC = +15 V 0 -55 50 Figure 26. Phase Margin and Gain Margin versus Differential Source Resistance 16 8.0 25 TA, AMBIENT TEMPERATURE (C) Figure 25. Gain Margin versus Temperature 12 VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k to VO = -10 V to +10 V CL = 10,000 pF CL, LOAD CAPACITANCE (pF) A m , GAIN MARGIN (dB) 1.0 k CL, LOAD CAPACITANCE (pF) 14 A m , GAIN MARGIN (dB) VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k to VO = -10 V to +10 V TA = 25C 60 50 - + VO 40 R2 30 VCC = +15 V VEE = -15 V RT = R1 + R2 AV = +100 VO = 0 V TA = 25C 1.0 TA, AMBIENT TEMPERATURE (C) 10 20 Phase 10 100 1.0 k 10 k RT, DIFFERENTIAL SOURCE RESISTANCE () http://onsemi.com 8 0 100 k m , PHASE MARGIN (DEGREES) PERCENT OVERSHOOT 100 MC34071,2,4,A MC33071,2,4,A V O , OUTPUT VOLTAGE SWING FROM 0 V (V) Figure 27. Normalized Slew Rate versus Temperature 1.1 1.05 1.0 0.95 0.9 0.85 -55 50 mV/DIV VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k CL = 500 pF 0 -25 0 25 50 75 100 125 10 1.0 mV 5.0 Compensated Uncompensated 0 1.0 mV -5.0 10 mV 1.0 mV -10 0 0.5 1.0 1.5 3.0 3.5 Figure 29. Small Signal Transient Response Figure 30. Large Signal Transient Reponse VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k CL = 300 pF TA = 25C VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k CL = 300 pF TA = 25C 0 1.0 s/DIV 100 Figure 32. Power Supply Rejection versus Frequency 100 TA = 125C VCC = +15 V VEE = -15 V VCM = 0 V VCM = 1.5 V TA = 25C TA = -55C PSR, POWER SUPPLY REJECTION (dB) CMR, COMMON MODE REJECTION (dB) 2.5 ts, SETTLING TIME (s) Figure 31. Common Mode Rejection versus Frequency 60 40 - ADM + VCM 20 1.0 VO VCM x ADM VO CMR = 20 Log 0 0.1 2.0 TA, AMBIENT TEMPERATURE (C) 2.0 s/DIV 80 VCC = +15 V VEE = -15 V AV = -1.0 TA = 25C 1.0 mV 10 mV 5.0 V/DIV SR, SLEW RATE (NORMALIZED) 1.15 Figure 28. Output Settling Time 10 100 1.0 k 10 k 100 k 1.0 M 10 M VCC = +15 V VEE = -15 V TA = 25C 80 VCC 60 - ADM + VEE 40 +PSR = 20 Log VO/ADM VCC -PSR = 20 Log VO/ADM VEE 20 0 0.1 f, FREQUENCY (Hz) 1.0 (VCC = +1.5 V) VO 10 100 +PSR -PSR (VEE = +1.5 V) 1.0 k 10 k f, FREQUENCY (Hz) http://onsemi.com 9 100 k 1.0 M 10 M MC34071,2,4,A MC33071,2,4,A Figure 33. Supply Current versus Supply Voltage Figure 34. Power Supply Rejection versus Temperature 105 PSR, POWER SUPPLY REJECTION (dB) TA = -55C 8.0 7.0 TA = 25C 6.0 TA = 125C 5.0 4.0 0 5.0 10 15 20 -PSR (VEE = +1.5 V) 95 +PSR (VCC = +1.5 V) 85 VCC, |VEE|, SUPPLY VOLTAGE (V) -PSR = 20 Log VO/ADM VEE -25 0 25 VCC - ADM + VCC = +15 V VEE = -15 V TA = 25C 60 40 20 0 VEE 50 75 20 30 50 70 100 100 125 2.8 70 VCC = +15 V VEE = -15 V VCM = 0 TA = 25C 60 50 40 200 300 2.4 2.0 1.6 Voltage 30 1.2 Current 20 0.8 10 0.4 0 10 VO Figure 36. Input Noise versus Frequency en , INPUT NOICE VOLTAGE ( nV Hz ) CHANNEL SEPARATION (dB) 120 80 VO/ADM VCC TA, AMBIENT TEMPERATURE (C) Figure 35. Channel Separation versus Frequency 100 +PSR = 20 Log 75 65 -55 25 VCC = +15 V VEE = -15 V 10 100 1.0 k 10 k 0 100 k i n , INPUT NOISE CURRENT (pA Hz ) I CC , SUPPLY CURRENT (mA) 9.0 f, FREQUENCY (kHz) f, FREQUENCY (kHz) APPLICATIONS INFORMATION CIRCUIT DESCRIPTION/PERFORMANCE FEATURES up to approximately 5.0 mA of current from VEE through either inputs clamping diode without damage or latching, although phase reversal may again occur. If one or both inputs exceed the upper common mode voltage limit, the amplifier output is readily predictable and may be in a low or high state depending on the existing input bias conditions. Since the input capacitance associated with the small geometry input device is substantially lower (2.5 pF) than the typical JFET input gate capacitance (5.0 pF), better frequency response for a given input source resistance can be achieved using the MC34071 series of amplifiers. This performance feature becomes evident, for example, in fast settling D-to-A current to voltage conversion applications where the feedback resistance can form an input pole with the input capacitance of the op amp. This input pole creates a 2nd order system with the single pole op amp and is therefore detrimental to its settling time. In this context, lower input capacitance is desirable especially for higher Although the bandwidth, slew rate, and settling time of the MC34071 amplifier series are similar to op amp products utilizing JFET input devices, these amplifiers offer other additional distinct advantages as a result of the PNP transistor differential input stage and an all NPN transistor output stage. Since the input common mode voltage range of this input stage includes the VEE potential, single supply operation is feasible to as low as 3.0 V with the common mode input voltage at ground potential. The input stage also allows differential input voltages up to 44 V, provided the maximum input voltage range is not exceeded. Specifically, the input voltages must range between VEE and VCC supply voltages as shown by the maximum rating table. In practice, although not recommended, the input voltages can exceed the VCC voltage by approximately 3.0 V and decrease below the VEE voltage by 0.3 V without causing product damage, although output phase reversal may occur. It is also possible to source http://onsemi.com 10 MC34071,2,4,A MC33071,2,4,A minimum current sink capability, typically to an output voltage of (VEE +1.8 V). In single supply applications the output can directly source or sink base current from a common emitter NPN transistor for fast high current switching applications. In addition, the all NPN transistor output stage is inherently fast, contributing to the bipolar amplifier's high gain bandwidth product and fast settling capability. The associated high frequency low output impedance (30 typ @ 1.0 MHz) allows capacitive drive capability from 0 pF to 10,000 pF without oscillation in the unity closed loop gain configuration. The 60 phase margin and 12 dB gain margin as well as the general gain and phase characteristics are virtually independent of the source/sink output swing conditions. This allows easier system phase compensation, since output swing will not be a phase consideration. The high frequency characteristics of the MC34071 series also allow excellent high frequency active filter capability, especially for low voltage single supply applications. Although the single supply specifications is defined at 5.0 V, these amplifiers are functional to 3.0 V @ 25C although slight changes in parametrics such as bandwidth, slew rate, and DC gain may occur. If power to this integrated circuit is applied in reverse polarity or if the IC is installed backwards in a socket, large unlimited current surges will occur through the device that may result in device destruction. Special static precautions are not necessary for these bipolar amplifiers since there are no MOS transistors on the die. As with most high frequency amplifiers, proper lead dress, component placement, and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted input-output coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input pole for optimum frequency response, but also minimizes extraneous "pick up" at this node. Supply decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. The output of any one amplifier is current limited and thus protected from a direct short to ground. However, under such conditions, it is important not to allow the device to exceed the maximum junction temperature rating. Typically for 15 V supplies, any one output can be shorted continuously to ground without exceeding the maximum temperature rating. values of feedback resistances (lower current DACs). This input pole can be compensated for by creating a feedback zero with a capacitance across the feedback resistance, if necessary, to reduce overshoot. For 2.0 k of feedback resistance, the MC34071 series can settle to within 1/2 LSB of 8 bits in 1.0 s, and within 1/2 LSB of 12-bits in 2.2 s for a 10 V step. In a inverting unity gain fast settling configuration, the symmetrical slew rate is 13 V/s. In the classic noninverting unity gain configuration, the output positive slew rate is +10 V/s, and the corresponding negative slew rate will exceed the positive slew rate as a function of the fall time of the input waveform. Since the bipolar input device matching characteristics are superior to that of JFETs, a low untrimmed maximum offset voltage of 3.0 mV prime and 5.0 mV downgrade can be economically offered with high frequency performance characteristics. This combination is ideal for low cost precision, high speed quad op amp applications. The all NPN output stage, shown in its basic form on the equivalent circuit schematic, offers unique advantages over the more conventional NPN/PNP transistor Class AB output stage. A 10 k load resistance can swing within 1.0 V of the positive rail (VCC), and within 0.3 V of the negative rail (VEE), providing a 28.7 Vpp swing from 15 V supplies. This large output swing becomes most noticeable at lower supply voltages. The positive swing is limited by the saturation voltage of the current source transistor Q7, and VBE of the NPN pull up transistor Q17, and the voltage drop associated with the short circuit resistance, R7. The negative swing is limited by the saturation voltage of the pull-down transistor Q16, the voltage drop ILR6, and the voltage drop associated with resistance R7, where IL is the sink load current. For small valued sink currents, the above voltage drops are negligible, allowing the negative swing voltage to approach within millivolts of VEE. For large valued sink currents (>5.0 mA), diode D3 clamps the voltage across R6, thus limiting the negative swing to the saturation voltage of Q16, plus the forward diode drop of D3 (VEE +1.0 V). Thus for a given supply voltage, unprecedented peak-to-peak output voltage swing is possible as indicated by the output swing specifications. If the load resistance is referenced to VCC instead of ground for single supply applications, the maximum possible output swing can be achieved for a given supply voltage. For light load currents, the load resistance will pull the output to VCC during the positive swing and the output will pull the load resistance near ground during the negative swing. The load resistance value should be much less than that of the feedback resistance to maximize pull up capability. Because the PNP output emitter-follower transistor has been eliminated, the MC34071 series offers a 20 mA http://onsemi.com 11 MC34071,2,4,A MC33071,2,4,A (Typical Single Supply Applications VCC = 5.0 V) Figure 37. AC Coupled Noninverting Amplifer Figure 38. AC Coupled Inverting Amplifier VCC 5.1 M VO 0 3.7 Vpp 0 VCC 3.7 Vpp 100 k 20 k 1.0 M Cin CO + 68 k VO MC34071 36.6 mVpp Cin - 100 k Vin 1.0 k 10 k RL + MC34071 10 k - 10 k RL 100 k Vin 370 mVpp AV = 101 VO CO AV = 10 BW (-3.0 dB) = 450 kHz BW (-3.0 dB) = 45 kHz Figure 39. DC Coupled Inverting Amplifer Maximum Output Swing Figure 40. Unity Gain Buffer TTL Driver 2.5 V VO VCC 4.75 Vpp 2.63 V 0 0 to 10,000 pF Vin 91 k VO Figure 42. Active Bandpass Filter AV = 10 BW (-3.0 dB) = 450 kHz R1 Vin Figure 41. Active High-Q Notch Filter 16 k C 0.01 32 k R + - MC34071 + VO VCC 0.4 VCC R2 = For less than 10% error from operational amplifier where fo and GBW are expressed in Hz. GBW = 4.5 MHz Typ. 2.0 C 0.02 http://onsemi.com 12 fo = 30 kHz Ho = 10 Ho = 1.0 R1 R3 4Q2R1-R3 fo = 1.0 kHz 1 fo = 4RC 2.0 C 0.02 R3 2.2 k C 0.047 Given fo = Center Frequency AO = Gain at Center Frequency Choose Value fo, Q, Ao, C Then: Q R3 R3 = R1 = 2Ho foC MC34071 16 k 2.0 R 1.1 k R2 5.6 k C 0.047 VO - R Vin TTL Gate - 1.0 M Vin 0.2 Vdc Cable + MC34071 100 k Vin MC54/74XX MC34071 - 5.1 k RL 5.1 k + Qofo < 0.1 GBW MC34071,2,4,A MC33071,2,4,A Figure 43. Low Voltage Fast D/A Converter Figure 44. High Speed Low Voltage Comparator CF Vin 2.0 V RF 5.0 k 5.0 k 5.0 k Vin - 10 k + 10 k t - MC34071 10 k VO + MC34071 VO 2.0 k RL VCC 1.0 V VO 0.2 s Delay 4.0 V Bit Switches 13 V/s 25 V/s (R-2R) Ladder Network 0.1 Settling Time 1.0 s (8-Bits, 1/2 LSB) t Delay 1.0 s Figure 45. LED Driver Figure 46. Transistor Driver VCC VCC "ON" Vin < Vref VCC RL + Vin MC34071 - + + MC34071 MC34071 - - Vref RL "ON" Vin > Vref (A) PNP Figure 47. AC/DC Ground Current Monitor (B) NPN Figure 48. Photovoltaic Cell Amplifier ILoad RF + ICell MC34071 VO - Ground Current Sense Resistor - MC34071 + RS R1 R2 VO = ILoad RS 1+ R1 R2 VCell = 0 V For VO > 0.1V BW ( -3.0 dB) = GBW R2 R1+R2 http://onsemi.com 13 VO = ICell RF VO > 0.1 V VO MC34071,2,4,A MC33071,2,4,A Figure 49. Low Input Voltage Comparator with Hysteresis Figure 50. High Compliance Voltage to Sink Current Converter Hysteresis VO Iout R2 Vref R1 Vin VOH + MC34071 + MC34071 VOL - - Vin Vin VinL VinH Vref R1 VinL = (V -V )+V R1+R2 OL ref ref R1 VinH = (V -V )+V R1+R2 OH ref ref Iout = VinVIO R R R1 VH = (VOH -VOL) R1+R Figure 51. High Input Impedance Differential Amplifier R1 Figure 52. Bridge Current Amplifier +Vref R2 RF R4 R - 1/2 - 1/2 MC34072 MC34072 +V1 R R3 + VO - VO MC34071 + R R = R +V2 R2 R4 = (Critical to CMRR) R1 R3 R4 R4 VO = 1 + V2-V1 R3 R3 + VO = Vref RF R < < R RF > > R R RF 2R2 (VO 0.1 V) For (V2 V1), V > 0 Figure 54. High Frequency Pulse Width Modulation Figure 53. Low Voltage Peak Detector fOSC Vin + ^ 0.85 RC + IB V + ISC VO = Vin (pk) MC34071 VP 0 t - t - Base Charge Removal + RL VP Iout 10,000 pF - 1/2 MC34072 C + 1/2 MC34072 + Vin V+ VP R IB - 100 k 100 k 47 k VP Pulse Width Control Group t OSC http://onsemi.com 14 Comparator High Current Output MC34071,2,4,A MC33071,2,4,A GENERAL ADDITIONAL APPLICATIONS INFORMATION VS = 15.0 V Figure 55. Second Order Low-Pass Active Filter Figure 56. Second Order High-Pass Active Filter C2 0.02 R1 560 C2 0.05 R2 5.6 k R3 510 - C1 1.0 - MC34071 R2 1.1 k MC34071 C1 0.44 R1 46.1 k C1 1.0 fo = 1.0 kHz Ho = 10 + Then: R1 = Choose: fo, Ho, C1 Choose: fo, Ho, C2 Then: C1 = 2C2 (Ho+1) R2 = 2 R2 R3 = Ho+1 4foC2 fo = 100 Hz Ho = 20 + R2 = Ho+0.5 foC1 2 2 2foC1 (1/Ho+2) C C2 = Ho R2 R1 = Ho Figure 57. Fast Settling Inverter Figure 58. Basic Inverting Amplifier CF* VO = 10 V Step RF + 2.0 k MC34071 R1 VO - - Vin MC34071 RL R2 VO + I Uncompensated High Speed DAC VO R2 = BW (-3.0 dB) = GBW Vin R1 ts = 1.0 s to 1/2 LSB (8-Bits) ts = 2.2 s Compensated SR = 13 V/s to 1/2 LSB (12-Bits) SR = 13 V/s *Optional Compensation Figure 59. Basic Noninverting Amplifier Figure 60. Unity Gain Buffer (AV = +1.0) + MC34071 Vin VO + MC34071 - - Vin R2 RL R1 R1 R1 +R2 VO = Vin 1+ BWp = 200 kHz VO = 20 Vpp SR = 10 V/s R2 R1 BW (-3.0 dB) = GBW R1 R1 +R2 http://onsemi.com 15 VO MC34071,2,4,A MC33071,2,4,A Figure 61. High Impedance Differential Amplifier + R R MC34074 - R - VO MC34074 RE + R - R Example: Let: R = RE = 12 k Then: AV = 3.0 BW = 1.5 MHz MC34074 + R R AV = 1 + 2 RE Figure 62. Dual Voltage Doubler +VO + + MC34074 100 k - 10 + RL 10 +10 - MC34074 + 220 pF 100 k -10 + + RL +VO 18.93 -VO -18.78 10 k 5.0 k 18 15.4 -18 -15.4 + MC34074 100 k - 10 RL 10 -VO http://onsemi.com 16 MC34071,2,4,A MC33071,2,4,A ORDERING INFORMATION Op Amp Function Single Dual Quad Device Operating Temperature Range Package Shipping TA = 0 to +70C DIP-8 SO-8 SO-8 / Tape & Reel 50 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel MC33071P, MC33071AP MC33071D, MC33071AD MC33071DR2, MC33071ADR2 TA = -40 to +85C DIP-8 SO-8 SO-8 / Tape & Reel 50 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel MC34072P, MC34072AP MC34072D, MC34072AD MC34072DR2, MC34072ADR2 TA = 0 to +70C DIP-8 SO-8 SO-8 / Tape & Reel 50 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel MC33072P, MC33072AP MC33072D, MC33072AD MC33072DR2, MC33072ADR2 TA = -40 to +85C DIP-8 SO-8 SO-8 / Tape & Reel 50 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel MC34072VD MC34072VDR2 TA = -40 to +125C SO-8 SO-8 / Tape & Reel 98 Units / Rail 2500 Units / Tape & Reel TA = 0 to +70C DIP-8 SO-8 SO-8 / Tape & Reel 50 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel MC33074P, MC33074AP MC33074D, MC33074AD MC33074DR2, MC33074ADR2 MC33074DTB, MC33074ADTB MC33074DTBR2, MC33074ADTBR2 TA = -40 to +85C DIP-8 SO-8 SO-8 / Tape & Reel TSSOP-14 TSSOP-14 / Tape & Reel 50 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail 2500 Units / Tape & Reel MC34074VD MC34074VDR2 TA = -40 to +125C SO-8 SO-8 / Tape & Reel 98 Units / Rail 2500 Units / Tape & Reel MC34071P, MC34071AP MC34071D, MC34071AD MC34071DR2, MC34071ADR2 MC34074P, MC34074AP MC34074D, MC34074AD MC34074DR2, MC34074ADR2 http://onsemi.com 17 MC34071,2,4,A MC33071,2,4,A PACKAGE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 626-05 ISSUE K 8 5 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. -B- 1 4 F DIM A B C D F G H J K L M N -A- NOTE 2 L C J -T- N SEATING PLANE D M K INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040 G H 0.13 (0.005) M T A M B M D SUFFIX (SO-8) PLASTIC PACKAGE CASE 751-05 ISSUE R D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C 8 5 0.25 H E M B M 1 4 h B MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 e X 45 _ q A C SEATING PLANE L 0.10 A1 B 0.25 M C B S A DIM A A1 B C D E e H h L q S http://onsemi.com 18 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.18 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ MC34071,2,4,A MC33071,2,4,A PACKAGE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE L 14 8 1 7 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. B A F DIM A B C D F G H J K L M N L C J N H G D SEATING PLANE K M D SUFFIX (SO-14) PLASTIC PACKAGE CASE 751A-03 ISSUE F 8 -B- 1 P 7 PL 0.25 (0.010) 7 G B M M R X 45 _ C F -T- SEATING PLANE 0.25 (0.010) M K D 14 PL M T B S A S http://onsemi.com 19 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 MC34071,2,4,A MC33071,2,4,A PACKAGE DIMENSIONS DTB SUFFIX (TSSOP-14) PLASTIC PACKAGE CASE 948G-01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S S N 2X 14 L/2 0.25 (0.010) 8 M B -U- L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A -V- EE CC CC EE K1 J J1 SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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