TL064ID - Texas Instruments

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IN+

IN− OUT

OFFSET N1

Offset Null/Compensation

TL061 Only

OFFSET N2

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SLOS078L –NOVEMBER 1978–REVISED MAY 2015

TL06xx Low-Power JFET-Input Operational Amplifiers

1 Features 2 Applications

1• Very Low Power Consumption • Tablets

• Typical Supply Current: 200 μA (Per Amplifier) • White goods

• Wide Common-Mode and Differential Voltage • Personal electronics

Ranges • Computers

• Low Input Bias and Offset Currents 3 Description

• Common-Mode Input Voltage Range The JFET-input operational amplifiers of the TL06x

Includes VCC+ series are designed as low-power versions of the

• Output Short-Circuit Protection TL08x series amplifiers. They feature high input

• High Input Impedance: JFET-Input Stage impedance, wide bandwidth, high slew rate, and low

• Internal Frequency Compensation input offset and input bias currents. The TL06x series

features the same terminal assignments as the TL07x

• Latch-Up-Free Operation and TL08x series.

• High Slew Rate: 3.5 V/μs Typical

• On Products Compliant to MIL-PRF-38535, Device Information(1)

All Parameters Are Tested Unless Otherwise PART NUMBER PACKAGE BODY SIZE (NOM)

Noted. On All Other Products, Production TL06xxD SOIC (14) 8.65 mm × 3.91 mm

Processing Does Not Necessarily Include Testing TL06xxJ CDIP (14) 19.56 mm × 6.92 mm

of All Parameters. TL06xxN PDIP (14) 19.30 mm × 6.35 mm

TL06xxNS SO (14) 10.30 mm × 5.30 mm

TL06xxPW TSSOP (14) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Schematic Symbol

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

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Table of Contents

8.2 Functional Block Diagram....................................... 14

1 Features.................................................................. 18.3 Feature Description................................................. 14

2 Applications ........................................................... 18.4 Device Functional Modes........................................ 15

3 Description............................................................. 19 Applications and Implementation ...................... 16

4 Revision History..................................................... 29.1 Application Information............................................ 16

5 Pin Configuration and Functions......................... 39.2 Typical Applications ................................................ 16

6 Specifications......................................................... 49.3 System Examples ................................................... 17

6.1 Absolute Maximum Ratings ...................................... 410 Power Supply Recommendations ..................... 19

6.2 ESD Ratings.............................................................. 511 Layout................................................................... 20

6.3 Recommended Operating Conditions....................... 511.1 Layout Guidelines ................................................. 20

6.4 Thermal Information - 8 Pins..................................... 511.2 Layout Examples................................................... 20

6.5 Thermal Information - 14 Pins................................... 512 Device and Documentation Support................. 21

6.6 Thermal Information - 20 Pins................................... 612.1 Documentation Support ........................................ 21

6.7 Electrical Characteristics for TL06xC and TL06xxC . 612.2 Related Links ........................................................ 21

6.8 Electrical Characteristics for TL06xxC and TL06xI... 712.3 Community Resources.......................................... 21

6.9 Electrical Characteristics for TL06xM and TL064M.. 712.4 Trademarks........................................................... 21

6.10 Operating Characteristics........................................ 812.5 Electrostatic Discharge Caution............................ 21

6.11 Typical Characteristics............................................ 912.6 Glossary................................................................ 21

7 Parameter Measurement Information ................ 13 13 Mechanical, Packaging, and Orderable

8 Detailed Description............................................ 14 Information ........................................................... 21

8.1 Overview................................................................. 14

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision K (January 2014) to Revision L Page

• Added Applications................................................................................................................................................................. 1

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision J (September 2004) to Revision K Page

• Updated document to new TI data sheet format - no specification changes......................................................................... 1

• Deleted Ordering Information table. ....................................................................................................................................... 1

• Updated Features with Military Disclaimer............................................................................................................................. 1

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

3 2 1 20 19

9 10 11 12 13

4IN+

VCC−

3IN+

1IN+

VCC+

2IN+

1IN−

1OUT

3OUT

3IN−

4OUT

4IN−

2IN−

2OUT

1OUT

1IN−

1IN+

VCC+

2IN+

2IN−

2OUT

4OUT

4IN−

4IN+

VCC−

3IN+

3IN−

3OUT

1OUT

1IN−

1IN+

VCC−

VCC+

2OUT

2IN−

2IN+

2OUT

2IN−

3 2 1 20 19

9 10 11 12 13

1IN−

1IN+

1OUT

2IN+

NC NC

VCC−

VCC+

OFFSET N1

IN−

IN+

VCC−

VCC+

OUT

OFFSET N2

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

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SLOS078L –NOVEMBER 1978–REVISED MAY 2015

5 Pin Configuration and Functions

TL061x D, P, and PS Package TL062 FK Package

8-Pin SOIC, PDIP, and SO 20-Pin LCCC

Top View Top View

TL062x D, JG, P, PS, and PW Package

8-Pin SOIC, CDIP, PDIP, SO, and TSSOP

Top View

TL064 FK Package

20-Pin LCCC

Top View

TL064x D, J, N, NS, PW, and W Package

14-Pin SOIC, CDIP, PDIP, SO, TSSOP and CFP

Top View

Pin Functions

TL061 TL062 TL064 TYPE DESCRIPTION

NAME D, JG, P, D, J, N, NS,

D, P, PS FK FK

PS, PW PW, W

1IN– — 2 5 2 3 I Negative input

1IN+ — 3 7 3 4 I Positive input

1OUT — 1 2 1 2 O Output

2IN– — 6 15 6 9 I Negative input

2IN+ — 5 12 5 8 I Positive input

2OUT — 7 17 7 10 O Output

3IN– — — — 9 13 I Negative input

3IN+ — — — 10 14 I Positive input

3OUT — — — 8 12 O Output

4IN– — — — 13 19 I Negative input

4IN+ — — — 12 18 I Positive input

4OUT — — — 14 20 O Output

IN– 2 — — — — I Negative input

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061

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TL061B

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TL062A

TL062B

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TL064B

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

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Pin Functions (continued)

TL061 TL062 TL064 TYPE DESCRIPTION

NAME D, JG, P, D, J, N, NS,

D, P, PS FK FK

PS, PW PW, W

IN+ 3 — — — — I Positive input

NC 8 — — — Do not connect

11 11

14 15

18 17

OFFSET N1 1 — — — — — Input offset adjustment

OFFSET N2 5 — — — — — Input offset adjustment

OUT 6 — — — — O Output

VCC– 4 4 10 11 16 — Power supply

VCC+ 7 8 20 4 6 — Power supply

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VCC+ 18

Supply voltage(2) V

VCC– –18

VID Differential input voltage(3) ±30 V

VIInput voltage(2)(4) ±15 V

Duration of output short circuit(5) Unlimited

TJOperating virtual junction temperature 150 °C

Case temperature for 60 seconds FK package 260 °C

Lead temperature 1.6 mm (1/16 inch) from J, JG, U, or W package 300 °C

case for 60 seconds

Lead temperature 1.6 mm (1/16 inch) from D, N, NS, P, PS, or PW package 260 °C

case for 10 seconds

Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−.

(3) Differential voltages are at IN+, with respect to IN−.

(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.

(5) The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the

dissipation rating is not exceeded.

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

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SLOS078L –NOVEMBER 1978–REVISED MAY 2015

6.2 ESD Ratings VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000

V(ESD) Electrostatic discharge V

Charged-device model (CDM), per JEDEC specification JESD22- 2000

C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

VCC+ Supply voltage 5 15 V

VCC– Supply voltage –5 –15 V

VCM Common-mode voltage VCC– + 4 VCC+ – 4 V

TL06xM –55 125

TL06xQ –40 125

TAAmbient temperature °C

TL06xI –40 85

TL06xC 0 70

6.4 Thermal Information - 8 Pins TL06xx

THERMAL METRIC(1) D (SOIC) P (PDIP) PS (SO) PW (TSSOP) JG (CDIP) UNIT

8 PINS 8 PINS 8 PINS 8 PINS 8 PINS

RθJJunction-to-ambient thermal 97 85 95 149 — °C/W

Aresistance(2)(3)

RθJJunction-to-case (top) thermal

C(to — — — — 14.5 °C/W

resistance(4)(5)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient

temperature is PD= (TJ(max) – TA)/RθJA. Operating at the absolute maximum TJof 150°C can affect reliability.

(3) The package thermal impedance is calculated in accordance with JESD 51-7.

(4) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient

temperature is PD= (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJof 150°C can affect reliability.

(5) The package thermal impedance is calculated in accordance with MIL-STD-883.

6.5 Thermal Information - 14 Pins TL06xx

D (SOIC) N (PDIP) NS (SO) PS (SO) PW J (CDIP) W (CFP)

THERMAL METRIC(1) UNIT

(TSSOP)

14 PINS 14 PINS 14 PINS 8 PINS 14 PINS 14 PINS 14 PINS

RθJJunction-to-ambient thermal 113

86 80 76 95 — — °C/W

Aresistance(2)(3)

RθJJunction-to-case (top) thermal

C(to — — — — — 15.05 14.65 °C/W

resistance(2)(3)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient

temperature is PD= (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJof 150°C can affect reliability.

(3) The package thermal impedance is calculated in accordance with MIL-STD-883.

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

www.ti.com

6.6 Thermal Information - 20 Pins TL06xx

THERMAL METRIC(1) FK (LCCC) UNIT

20 PINS

RθJA Junction-to-ambient thermal resistance(2)(3) — °C/W

RθJC(top) Junction-to-case (top) thermal resistance(4)(5) 5.61 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient

temperature is PD= (TJ(max) – TA)/RθJA. Operating at the absolute maximum TJof 150°C can affect reliability.

(3) The package thermal impedance is calculated in accordance with JESD 51-7.

(4) Maximum power dissipation is a function of TJ(max), RθJC, and TC. The maximum allowable power dissipation at any allowable ambient

temperature is PD= (TJ(max) – TC) / RθJC. Operating at the absolute maximum TJof 150°C can affect reliability.

(5) The package thermal impedance is calculated in accordance with MIL-STD-883.

6.7 Electrical Characteristics for TL06xC and TL06xxC

VCC± = ±15 V (unless otherwise noted) TL061AC, TL062AC,

TL061C, TL062C, TL064C TL064AC

PARAMETER TEST CONDITIONS(1) UNIT

MIN TYP MAX MIN TYP MAX

TA= 25°C 3 15 3 6

VIO Input offset voltage VO= 0, RS= 50 ΩmV

TA= Full range 20 7.5

Temperature coefficient

αVIO VO= 0, RS= 50 Ω, TA= Full range 10 10 μV/°C

of input offset voltage

TA= 25°C 5 200 5 100 pA

IIO Input offset current VO= 0 TA= Full range 5 3 nA

TA= 25°C 30 400 30 200 pA

IIB Input bias current(2) VO= 0 TA= Full range 10 7 nA

–12 –12

Common-mode input

VICR TA= 25°C ±11 to ±11 to V

voltage range 15 15

RL= 10 kΩ, TA= 25°C ±10 ±13.5 ±10 ±13.5

Maximum peak output

VOM V

voltage swing RL≥10 kΩ, TA= Full range ±10 ±10

TA= 25°C 3 6 4 6

Large-signal differential VO= ±10 V,

AVD V/mV

voltage amplification RL≥2 kΩTA= Full range 3 4

B1Unity-gain bandwidth RL= 10 kΩ, TA= 25°C 1 1 MHz

riInput resistance TA= 25°C Ω

1012 1012

Common-mode VIC = VICRmin,

CMRR 70 86 80 86 dB

rejection ratio VO= 0, RS= 50 Ω, TA= 25°C

Supply-voltage VCC = ±9 V to ±15 V,

kSVR rejection ratio 70 95 80 95 dB

VO= 0, RS= 50 Ω, TA= 25°C

(ΔVCC±/ΔVIO)

Total power dissipation

PDVO= 0, No load, TA= 25°C 6 7.5 6 7.5 mW

(each amplifier)

Supply current

ICC VO= 0, No load, TA= 25°C 200 250 200 250 µA

(each amplifier)

VO1/VO2 Crosstalk attenuation AVD = 100, TA= 25°C 120 120 dB

(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full

range for TAis 0°C to 70°C for TL06xC, TL06xAC, and TL06xBC and –40°C to 85°C for TL06xI.

(2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as

shown in Figure 12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

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SLOS078L –NOVEMBER 1978–REVISED MAY 2015

6.8 Electrical Characteristics for TL06xxC and TL06xI

VCC± = ±15 V (unless otherwise noted) TL061BC, TL062BC, TL061I, TL062I, TL064I

TL064BC

PARAMETER TEST CONDITIONS(1) UNIT

MIN TYP MAX MIN TYP MAX

TA= 25°C 2 3 3 6

VIO Input offset voltage VO= 0, RS= 50 ΩmV

TA= Full range 5 9

Temperature coefficient

αVIO VO= 0, RS= 50 Ω, TA= Full range 10 10 μV/°C

of input offset voltage

TA= 25°C 5 100 5 100 pA

IIO Input offset current VO= 0 TA= Full range 3 10 nA

TA= 25°C 30 200 30 200 pA

IIB Input bias current(2) VO= 0 TA= Full range 7 20 nA

–12 –12

Common-mode input

VICR TA= 25°C ±11 to ±11 to V

voltage range 15 15

RL= 10 kΩ, TA= 25°C ±10 ±13.5 ±10 ±13.5

Maximum peak output

VOM V

voltage swing RL≥10 kΩ, TA= Full range ±10 ±10

TA= 25°C 4 6 4 6

Large-signal differential VO= ±10 V,

AVD V/mV

voltage amplification RL≥2 kΩTA= Full range 4 4

B1Unity-gain bandwidth RL= 10 kΩ, TA= 25°C 1 1 MHz

riInput resistance TA= 25°C Ω

1012 1012

Common-mode VIC = VICRmin,

CMRR 80 86 80 86 dB

rejection ratio VO= 0, RS= 50 Ω, TA= 25°C

Supply-voltage VCC = ±9 V to ±15 V,

kSVR rejection ratio 80 95 80 95 dB

VO= 0, RS= 50 Ω, TA= 25°C

(ΔVCC±/ΔVIO)

Total power dissipation

PDVO= 0, No load, TA= 25°C 6 7.5 6 7.5 mW

(each amplifier)

Supply current

ICC VO= 0, No load, TA= 25°C 200 250 200 250 µA

(each amplifier)

VO1/VO2 Crosstalk attenuation AVD = 100, TA= 25°C 120 120 dB

(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified. Full

range for TAis 0°C to 70°C for TL06xC, TL06xAC, and TL06xBC and –40°C to 85°C for TL06xI.

(2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as

shown in Figure 12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.

6.9 Electrical Characteristics for TL06xM and TL064M

VCC± = ±15 V (unless otherwise noted) TL061M, TL062M TL064M

PARAMETER TEST CONDITIONS(1) UNIT

MIN TYP MAX MIN TYP MAX

TA= 25°C 3 6 3 9

VIO Input offset voltage VO= 0, RS= 50 ΩmV

TA= –55°C to 9 15

125°C

Temperature coefficient VO= 0, RS= 50 Ω,

αVIO 10 10 μV/°C

of input offset voltage TA= –55°C to 125°C

TA= 25°C 5 100 5 100 pA

IIO Input offset current VO= 0 TA= –55°C 20(2) 20(2) nA

TA= 125°C 20 20

TA= 25°C 30 200 30 200 pA

IIB Input bias current(3) VO= 0 TA= –55°C 50(2) 50(2) nA

TA= 125°C 50 50

–12 –12

Common-mode input

VICR TA= 25°C ±11 to ±11 to V

voltage range 15 15

(1) All characteristics are measured under open-loop conditions, with zero common-mode voltage, unless otherwise specified.

(2) This parameter is not production tested.

(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as

shown in Figure 12. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

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Electrical Characteristics for TL06xM and TL064M (continued)

VCC± = ±15 V (unless otherwise noted) TL061M, TL062M TL064M

PARAMETER TEST CONDITIONS(1) UNIT

MIN TYP MAX MIN TYP MAX

RL= 10 kΩ, TA= 25°C ±10 ±13.5 ±10 ±13.5

Maximum peak output

VOM V

voltage swing RL≥10 kΩ, TA= –55°C to 125°C ±10 ±10

TA= 25°C 4 6 4 6

Large-signal differential VO= ±10 V,

AVD V/mV

TA= –55°C to

voltage amplification RL≥2 kΩ4 4

125°C

B1Unity-gain bandwidth RL= 10 kΩ, TA= 25°C MHz

riInput resistance TA= 25°C Ω

1012 1012

Common-mode VIC = VICRmin,

CMRR 80 86 80 86 dB

rejection ratio VO= 0, RS= 50 Ω, TA= 25°C

Supply-voltage VCC = ±9 V to ±15 V,

kSVR rejection ratio 80 95 80 95 dB

VO= 0, RS= 50 Ω, TA= 25°C

(ΔVCC±/ΔVIO)

Total power dissipation

PDVO= 0, No load, TA= 25°C 6 7.5 6 7.5 mW

(each amplifier)

Supply current

ICC VO= 0, No load, TA= 25°C 200 250 200 250 µA

(each amplifier)

VO1/VO2 Crosstalk attenuation AVD = 100, TA= 25°C 120 120 dB

6.10 Operating Characteristics

VCC± = ±15 V, TA= 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VI= 10 V, CL= 100 pF,

SR Slew rate at unity gain(1) 1.5 3.5 V/μs

RL= 10 kΩ, see Figure 16

trRise-time 0.2 μs

VI= 20 V, CL= 100 pF,

RL= 10 kΩ, see Figure 16

Overshoot factor 10%

VnEquivalent input noise voltage RS= 20 Ωf = 1 kHz 42 nV/√Hz

(1) Slew rate at –55°C to 125°C is 0.7 V/μs min.

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

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TL062A

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SLOS078L –NOVEMBER 1978–REVISED MAY 2015

6.11 Typical Characteristics

Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the

various devices.

Table 1. Table of Graphs

FIGURE

Maximum peak output voltage versus Supply voltage Figure 1

Maximum peak output voltage versus Free-air temperature Figure 2

Maximum peak output voltage versus Load resistance Figure 3

Maximum peak output voltage versus Frequency Figure 4

Differential voltage amplification versus Free-air temperature Figure 5

Large-signal differential voltage amplification versus Frequency Figure 6

Phase shift versus Frequency Figure 6

Supply current versus Supply voltage Figure 7

Supply current versus Free-air temperature Figure 8

Total power dissipation versus Free-air temperature Figure 9

Common-mode rejection ratio versus Free-air temperature Figure 10

Normalized unity-gain bandwidth versus Free-air temperature Figure 11

Normalized slew rate versus Free-air temperature Figure 11

Normalized phase shift versus Free-air temperature Figure 11

Input bias current versus Free-air temperature Figure 12

Voltage-follower large-signal pulse response versus Time Figure 13

Output voltage versus Elapsed time Figure 14

Equivalent input noise voltage versus Frequency Figure 15

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

AVD

(left scale)

0.001

f − Frequency − Hz

10 100 1 k 10 k 100 k 1 M 10 M

0.01

0.1

100

Phase Shift

135°

90°

180°

45°

0°

VCC±=±15 V

Rext = 0

RL= 10 kΩ

TA= 25°C

Phase Shift

(right scale)

− Large-Signal Differential

AVD

Voltage Amplification − V/mV

− Differential Voltage Amplification − V/mV

AVD

RL= 10 kΩ

VCC±=±15 V

−75

TA− Free-Air Temperature − °C

−50 −25 0 25 50 75 100 125

See Figure 2

TA= 25°C

VCC±=±15 V

100

RL− Load Resistance − Ω

1 k 10 k

2.5±

5±

7.5±

10±

12.5±

15±

200 400 700 2 k 4 k 7 k

− Maximum Peak Output Voltage − V

VOM

VCC±=±12 V

VCC±=±5 V

f − Frequency − Hz

1 k

10 k 100 k 1 M 10 M

2.5±

5±

7.5±

10±

12.5±

RL= 10 kΩ

TA= 25°C

See Figure 2

VCC±=±15 V

− Maximum Peak Output Voltage − V

VOM

−75

TA− Free-Air Temperature − °C

2.5±

5±

7.5±

10±

12.5±

15±

−50 −25 0 25 50 75 100 125

VCC±=±15 V

RL= 10 kΩ

See Figure 2

− Maximum Peak Output Voltage − V

VOM

− Maximum Peak Output Voltage − V

|VCC±| − Supply Voltage − V

2.5±

5±

7.5±

10±

12.5±

15±

2 4 6 8 10 12 14 16

RL= 10 kΩ

TA= 25°C

See Figure 2

VOM

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

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Figure 1. Maximum Peak Output Voltage vs Supply Voltage Figure 2. Maximum Peak Output Voltage vs Free-Air

Temperature

Figure 4. Maximum Peak Output Voltage vs Frequency

Figure 3. Maximum Peak Output Voltage vs Load

Resistance

Figure 5. Differential Voltage Amplification vs Free-Air Figure 6. Large-Signal Differential Voltage Amplification and

Temperature Phase Shift vs Frequency

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

0.7

Normalized Unity-Gain Bandwidth and Slew Rate

125

1007550250−25−50

TA− Free-Air Temperature − °C

−75

0.8

0.9

1.1

1.2

1.3

1.02

1.01

0.99

0.98

0.97

Normalized Phase Shift

1.03

VCC±=±15 V

RL= 10 kΩ

f = B1 for Phase Shift

Unity-Gain Bandwidth

(left scale) Phase Shift

(right scale)

Slew Rate

(left scale)

1251007550250−25

0.01

IIB − Input Bias Current − nA

−50

TA− Free-Air Temperature − °C

0.04

0.1

0.4

100

VCC±=±15 V

IIB

−75

TA− Free-Air Temperature − °C

−50 −25 0 25 50 75 100 125

VCC±=±15 V

No Signal

No Load

TL064

TL062

TL061

PD − Total Power Dissipation − mW

CMRR − Common-Mode Rejection Ratio − dB

1251007550250−25−50

TA− Free-Air Temperature − °C

−75

VCC±=±15 V

RL= 10 kΩ

TA= 25°C

No Signal

No Load

2 4 6 8 10 12 14 16

100

150

200

250

|VCC±| − Supply Voltage − V

ICC − Supply Current − µA

ICC±

ICC − Supply Current − µA

−75

TA− Free-Air Temperature − °C

100

150

200

250

ICC±

VCC±=±15 V

No Signal

No Load

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

www.ti.com

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

Figure 8. Supply Current vs Free-Air Temperature

Figure 7. Supply Current vs Supply Voltage

Figure 10. All Except TL06_C Common-Mode Rejection

Figure 9. Total Power Dissipation vs Free-Air Temperature Ratio vs Free-Air Temperature

Figure 12. Input Bias Current vs Free-Air Temperature

Figure 11. Normalized Unity-Gain Bandwidth, Slew Rate,

and Phase Shift vs Free-Air Temperature

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

− Equivalent Input Noise Voltage −

f − Frequency − Hz

100

10 40 100 400 1 k 4 k 10 k 40 k 100 k

VCC±=±15 V

RS= 20 Ω

TA= 25°C

nV/ Hz

−6

Input and Output Voltages − V

t − Time − µs

Input

Output

VCC±=±15 V

RL= 10 kΩ

CL= 100 pF

TA= 25°C

0 2 4 6 8 10

−4

−2

−4

− Output Voltage − mV

t − Elapsed Time − µs

0 0.2 0.4 0.6 0.8 1 1.2 1.4

VCC±=±15 V

RL= 10 kΩ

TA= 25°C

10%

Overshoot

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

www.ti.com

Figure 14. Output Voltage vs Elapsed Time

Figure 13. Voltage-Follower Large-Signal Pulse Response

vs Time

Figure 15. Equivalent Input Noise Voltage vs Frequency

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

100 kΩ

1.5 kΩ

VCC−

−

TL061

IN−

OUT

IN+

10 kΩ

1 kΩ

RLCL= 100 pF

−

OUT

RL= 2 kΩ

−

CL= 100 pF

OUT

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

www.ti.com

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

7 Parameter Measurement Information

Figure 16. Unity-Gain Amplifier

Figure 17. Gain-of-10 Inverting Amplifier

Figure 18. Input Offset-Voltage Null Circuit

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

IN+

50 Ω

100 Ω

VCC+

OUT VCC−

OFFSET N1

TL061 Only

OFFSET N2

IN−

C1 = 10 pF on TL061, TL062, and TL064

Component values shown are nominal.

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

www.ti.com

8 Detailed Description

8.1 Overview

The JFET-input operational amplifiers of the TL06x series are designed as low-power versions of the TL08x

series amplifiers. They feature high input impedance, wide bandwidth, high slew rate, and low input offset and

input bias currents. The TL06x series features the same terminal assignments as the TL07x and TL08x series.

Each of these JFET-input operational amplifiers incorporates well-matched, high-voltage JFET and bipolar

transistors in an integrated circuit.

The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for

operation from −40°C to 85°C, and the M-suffix devices are characterized for operation over the full military

temperature range of −55°C to 125°C.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Common-Mode Rejection Ratio

The common-mode rejection ratio (CMRR) of an amplifier is a measure of how well the device rejects unwanted

input signals common to both input leads. It is found by taking the ratio of the change in input offset voltage to

the change in the input voltage and converting to decibels. Ideally the CMRR is infinite, but in practice, amplifiers

are designed to have it as high as possible. The CMRR of this device is 86 dB.

8.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on the

input. These devices have a 3.5-V/μs slew rate.

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

www.ti.com

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

8.4 Device Functional Modes

These devices are powered on when the supply is connected. This device can be operated as a single supply

operational amplifier or dual supply amplifier depending on the application.

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

Vsup+

+VOUT

VIN

Vsup-

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

www.ti.com

9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TL06x series of operational amplifiers can be used in countless applications. The few applications in this

section show principles used in all applications of these parts.

9.2 Typical Applications

9.2.1 Inverting Amplifier Application

A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage

on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes

negative voltages positive.

Figure 19. Schematic for Inverting Amplifier Application

9.2.1.1 Design Requirements

The supply voltage must be chosen such that it is larger than the input voltage range and output range. For

instance, this application will scale a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to

accommodate this application.

9.2.1.2 Detailed Design Procedure

Determine the gain required by the inverting amplifier:

(1)

(2)

Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kilohm range is

desirable because the amplifier circuit will use currents in the milliamp range. This ensures the part will not draw

too much current. This example will choose 10 kΩfor RI which means 36 kΩwill be used for RF. This was

determined by Equation 3.

(3)

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061

−

C1 C2

C3 VCC−

VCC+

OutputInput

R1 R2 2 R3 1.5 MΩ

C1 C2 110 pF

f 1 kHz

2π R1 C1

= = ´ =

= = =

= =

´ ´

−

TL064 Output C

VCC+

Output B

TL064

−

VCC+

Output A

TL064

−

VCC+

TL064

VCC+

100 kΩ

100 µF

Input

1µF

1 MΩ

100 kΩ

TL061

−

−15 V

15 V

Output

1 kΩ

9.1 kΩ

3.3 kΩ

CF= 3.3 µF

RF= 100 kΩ

3.3 kΩ

F F

f2π R C

´ ´

−

TL064

VCC+

VCC−

100 kΩ

Input B

10 kΩ

0.1% 0.1%

10 kΩ

VCC−

VCC+

TL064

Input A

VCC+

TL064

VCC−

100 kΩ

10 kΩ

0.1%

10 kΩ

0.1%

TL064

VCC−

VCC+

100 kΩ

Output

1 MΩ

-2

-1.5

-1

-0.5

0.5

1.5

0 0.5 1 1.5 2

Volts

Time (ms)

VIN

VOUT

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

www.ti.com

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

Typical Applications (continued)

9.2.1.3 Application Curve

Figure 20. Input and Output Voltages of the Inverting Amplifier

9.3 System Examples

9.3.1 General Applications

Figure 21. Instrumentation Amplifier Figure 22. 0.5-Hz Square-Wave Oscillator

Figure 23. High-Q Notch Filter Figure 24. Audio-Distribution Amplifier

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

IN−

IN+

100 kΩ

TL062

1 kΩ

100 kΩ

−

Output

1.2 MΩ100 kΩ

20 µF

−

0.1 µF

47 kΩ

TL061

2.7 kΩ

270 Ω0.003 µF 0.001 µF

0.002 µF

1µF

10 kΩ

100 kΩ

50 kΩ

0.06 µF

50 kΩ

10 kΩ100 kΩ1 kΩ

0.06 µF

10 kΩ

0.02 µF

100 kΩ

TL061

−

0.1 Fµ

10 kΩ

50 Ω

250 kΩ

Output

1 MΩ

VCC+

10 kΩ

0.1 µF

−

TIL601

10 kΩ

15 V

Output

−15 V

5 kΩ

100 pF TL061

10 kΩ

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

www.ti.com

System Examples (continued)

Figure 25. Low-Level Light Detector Preamplifier Figure 26. AC Amplifier

Figure 27. Microphone Preamplifier With Tone Figure 28. Instrumentation Amplifier

Control

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL062

220 kΩ

−

0.00375 µF

TL062

−

10 pF

68 kΩ

0.003 µF

0.03 µF

10 kΩ3.3 kΩ

0.003 µF

VCC−

VCC+

Output

Input

VCC−

VCC+

10 pF

MIN

MAX

100 kΩ

Treble

MIN

MAX

100 kΩ

Bass

10 kΩ

0.01 µF27 kΩ

100 Ω

Balance

100 Ω

50 pF

75 µF

47 µF

5 kΩ

Gain

47 kΩ

1µF

TA= 25°C

VCC±=±15 V

Max

Treble

Max Bass

200 10 k4 k2 k1 k40040 100

−5

−10

−15

−20

−25

20 k

f − Frequency − Hz

Voltage Amplification − dB

IC PREAMPLIFIER RESPONSE CHARACTERISTICS

Min

Treble

Min Bass

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

www.ti.com

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

System Examples (continued)

Figure 29. IC Preamplifier

10 Power Supply Recommendations

CAUTION

Supply voltages larger than 36 V for a single supply, or outside the range of ±18 V for

a dual supply can permanently damage the device (see the Absolute Maximum

Ratings).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high

impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout.

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

VCC+

IN1í

IN1+

VCCí

OUT

RIN

GND

VIN

VS-GND

VS+

GND

Run the input traces as far

away from the supply lines

as possible

Only needed for

dual-supply

operation

Place components close to

device and to each other to

reduce parasitic errors

Use low-ESR, ceramic

bypass capacitor

(or GND for single supply) Ground (GND) plane on another layerVOUT

RIN

RG RF

VOUT

VIN

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

www.ti.com

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the

operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance

power sources local to the analog circuitry.

– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single

supply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to

Circuit Board Layout Techniques,(SLOA089).

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as

opposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting

input minimizes parasitic capacitance, as shown in Layout Examples.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

11.2 Layout Examples

Figure 30. Operational Amplifier Schematic for Noninverting Configuration

Figure 31. Operational Amplifier Board Layout for Noninverting Configuration

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

TL061

TL061A

TL061B

TL062

TL062A

TL062B

TL064

TL064A

TL064B

www.ti.com

SLOS078L –NOVEMBER 1978–REVISED MAY 2015

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

Circuit Board Layout Techniques,SLOA089

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &

PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

TL061 Click here Click here Click here Click here Click here

TL061A Click here Click here Click here Click here Click here

TL061B Click here Click here Click here Click here Click here

TL062 Click here Click here Click here Click here Click here

TL062A Click here Click here Click here Click here Click here

TL062B Click here Click here Click here Click here Click here

TL064 Click here Click here Click here Click here Click here

TL064A Click here Click here Click here Click here Click here

TL064B Click here Click here Click here Click here Click here

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser based versions of this data sheet, refer to the left hand navigation.

Product Folder Links: TL061 TL061A TL061B TL062 TL062A TL062B TL064 TL064A TL064B

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

81023022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023022A

TL062MFKB

8102302PA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8102302PA

TL062M

81023032A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023032A

TL064MFKB

8102303CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8102303CA

TL064MJB

8102303DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8102303DA

TL064MWB

TL061ACD ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 061AC

TL061ACDE4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 061AC

TL061ACDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 061AC

TL061ACP ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL061ACP

TL061BCP ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL061BCP

TL061BCPE4 ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL061BCP

TL061CD ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL061C

TL061CDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL061C

TL061CP ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL061CP

TL061CPSR ACTIVE SO PS 8 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T061

TL061ID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL061I

TL061IDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL061I

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TL061IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL061I

TL061IP ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL061IP

TL061IPE4 ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL061IP

TL062ACD ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 062AC

TL062ACDE4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 062AC

TL062ACDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 062AC

TL062ACDRE4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 062AC

TL062ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 062AC

TL062ACP ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL062ACP

TL062ACPSR ACTIVE SO PS 8 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T062A

TL062ACPSRG4 ACTIVE SO PS 8 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T062A

TL062BCD ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 062BC

TL062BCDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 062BC

TL062BCDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 062BC

TL062BCP ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL062BCP

TL062BCPE4 ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL062BCP

TL062CD ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C

TL062CDE4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 3

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TL062CDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C

TL062CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C

TL062CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL062C

TL062CP ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL062CP

TL062CPE4 ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL062CP

TL062CPSR ACTIVE SO PS 8 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T062

TL062CPW ACTIVE TSSOP PW 8 150 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T062

TL062CPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T062

TL062CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T062

TL062CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T062

TL062ID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I

TL062IDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I

TL062IDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I

TL062IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL062I

TL062IP ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL062IP

TL062IPE4 ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL062IP

TL062IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z062

TL062IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z062

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 4

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TL062MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023022A

TL062MFKB

TL062MJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 TL062MJG

TL062MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8102302PA

TL062M

TL064ACD ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL064AC

TL064ACDR ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL064AC

TL064ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL064AC

TL064ACN ACTIVE PDIP N 14 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL064ACN

TL064BCD ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL064BC

TL064BCDG4 ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL064BC

TL064BCDR ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL064BC

TL064BCN ACTIVE PDIP N 14 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL064BCN

TL064BCNE4 ACTIVE PDIP N 14 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL064BCN

TL064CD ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL064C

TL064CDE4 ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL064C

TL064CDR ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL064C

TL064CDRE4 ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL064C

TL064CN ACTIVE PDIP N 14 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL064CN

TL064CNSR ACTIVE SO NS 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL064

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 5

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TL064CPW ACTIVE TSSOP PW 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T064

TL064CPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T064

TL064CPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T064

TL064CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T064

TL064ID ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I

TL064IDG4 ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I

TL064IDR ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 TL064I

TL064IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I

TL064IN ACTIVE PDIP N 14 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL064IN

TL064INE4 ACTIVE PDIP N 14 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL064IN

TL064INS ACTIVE SO NS 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I

TL064INSR ACTIVE SO NS 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL064I

TL064IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z064

TL064MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023032A

TL064MFKB

TL064MJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 TL064MJ

TL064MJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8102303CA

TL064MJB

TL064MWB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8102303DA

TL064MWB

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 6

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TL062, TL062M, TL064, TL064M :

•Catalog: TL062, TL064

•Military: TL062M, TL064M

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 7

•Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TL061ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL061CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL061CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

TL061IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL062ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL062ACPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

TL062BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL062CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL062CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

TL062CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

TL062CPWRG4 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

TL062IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL062IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

TL064ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 28-Apr-2016

Pack Materials-Page 1

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TL064BCDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL064CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TL064IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL064IDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL064INSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

TL064IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TL061ACDR SOIC D 8 2500 340.5 338.1 20.6

TL061CDR SOIC D 8 2500 340.5 338.1 20.6

TL061CDR SOIC D 8 2500 367.0 367.0 35.0

TL061CPSR SO PS 8 2000 367.0 367.0 38.0

TL061IDR SOIC D 8 2500 367.0 367.0 35.0

TL061IDR SOIC D 8 2500 340.5 338.1 20.6

TL062ACDR SOIC D 8 2500 340.5 338.1 20.6

TL062ACPSR SO PS 8 2000 367.0 367.0 38.0

TL062BCDR SOIC D 8 2500 340.5 338.1 20.6

TL062CDR SOIC D 8 2500 367.0 367.0 35.0

TL062CDR SOIC D 8 2500 340.5 338.1 20.6

PACKAGE MATERIALS INFORMATION

www.ti.com 28-Apr-2016

Pack Materials-Page 2

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TL062CPSR SO PS 8 2000 367.0 367.0 38.0

TL062CPWR TSSOP PW 8 2000 367.0 367.0 35.0

TL062CPWRG4 TSSOP PW 8 2000 367.0 367.0 35.0

TL062IDR SOIC D 8 2500 367.0 367.0 35.0

TL062IDR SOIC D 8 2500 340.5 338.1 20.6

TL062IPWR TSSOP PW 8 2000 367.0 367.0 35.0

TL064ACDR SOIC D 14 2500 367.0 367.0 38.0

TL064BCDR SOIC D 14 2500 367.0 367.0 38.0

TL064CPWR TSSOP PW 14 2000 367.0 367.0 35.0

TL064IDR SOIC D 14 2500 367.0 367.0 38.0

TL064IDRG4 SOIC D 14 2500 367.0 367.0 38.0

TL064INSR SO NS 14 2000 367.0 367.0 38.0

TL064IPWR TSSOP PW 14 2000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 28-Apr-2016

Pack Materials-Page 3

www.ti.com

PACKAGE OUTLINE

14X .008-.014

[0.2-0.36]

TYP

-15

AT GAGE PLANE

-.314.308 -7.977.83[ ]

14X -.026.014 -0.660.36[ ]

14X -.065.045 -1.651.15[ ]

.2 MAX TYP

[5.08] .13 MIN TYP

[3.3]

TYP-.060.015 -1.520.38[ ]

4X .005 MIN

[0.13]

12X .100

[2.54]

.015 GAGE PLANE

[0.38]

-.785.754 -19.9419.15[ ]

B -.283.245 -7.196.22[ ]

CDIP - 5.08 mm max heightJ0014A

CERAMIC DUAL IN LINE PACKAGE

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for

reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This package is hermitically sealed with a ceramic lid using glass frit.

4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.

5. Falls within MIL-STD-1835 and GDIP1-T14.

PIN 1 ID

(OPTIONAL)

SCALE 0.900

SEATING PLANE

.010 [0.25] C A B

www.ti.com

EXAMPLE BOARD LAYOUT

ALL AROUND

[0.05] MAX.002

.002 MAX

[0.05]

ALL AROUND

SOLDER MASK

OPENING

METAL

(.063)

[1.6]

(R.002 ) TYP

[0.05]

14X ( .039)

[1]

( .063)

[1.6]

12X (.100 )

[2.54]

(.300 ) TYP

[7.62]

CDIP - 5.08 mm max heightJ0014A

CERAMIC DUAL IN LINE PACKAGE

4214771/A 05/2017

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED

SCALE: 5X

SEE DETAIL A SEE DETAIL B

SYMM

DETAIL A

SCALE: 15X

SOLDER MASK

OPENING

METAL

DETAIL B

13X, SCALE: 15X

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.310 (7,87)

0.290 (7,37)

0.014 (0,36)

0.008 (0,20)

Seating Plane

4040107/C 08/96

0.065 (1,65)

0.045 (1,14)

0.020 (0,51) MIN

0.400 (10,16)

0.355 (9,00)

0.015 (0,38)

0.023 (0,58)

0.063 (1,60)

0.015 (0,38)

0.200 (5,08) MAX

0.130 (3,30) MIN

0.245 (6,22)

0.280 (7,11)

0.100 (2,54)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

www.ti.com

PACKAGE OUTLINE

TYP

6.6

6.2

1.2 MAX

6X 0.65

8X 0.30

0.19

1.95

0.15

0.05

(0.15) TYP

0 - 8

0.25

GAGE PLANE

0.75

0.50

NOTE 3

3.1

2.9

NOTE 4

4.5

4.3

4221848/A 02/2015

TSSOP - 1.2 mm max heightPW0008A

SMALL OUTLINE PACKAGE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153, variation AA.

0.1 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

(5.8)

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

8X (1.5)

8X (0.45)

6X (0.65)

(R )

TYP

0.05

4221848/A 02/2015

TSSOP - 1.2 mm max heightPW0008A

SMALL OUTLINE PACKAGE

SYMM

LAND PATTERN EXAMPLE

SCALE:10X

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(5.8)

6X (0.65)

8X (0.45)

8X (1.5)

(R ) TYP0.05

4221848/A 02/2015

TSSOP - 1.2 mm max heightPW0008A

SMALL OUTLINE PACKAGE

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

TL064CN TL064CD TL064CPWR TL064ID TL064IN TL064INS TL064INSG4 TL064INSR TL064INSRG4

TL064CNSRG4 TL064CDBRG4 TL064CDG4 TL064CDRG4 TL064CPWG4 TL064CPWRG4 TL064CDBR

TL064CDBRE4 TL064CDE4 TL064CDR TL064CDRE4 TL064CNE4 TL064CNSR TL064CNSRE4 TL064CPW

TL064CPWE4 TL064CPWRE4 TL064IDE4 TL064IDG4 TL064IDR TL064IDRE4 TL064IDRG4 TL064INE4

TL064CP TL064IPWR