1. General description
The 74LVC2G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device.
The 74LVC2G53 provides one analog multiplexer/demultiplexer with a digital select
input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an
active LOW enable input (E). When pin E is HIGH, the switch is turned off.
Schmitt-trigger action at the select and enable inputs makes the circuit tolerant of slower
input rise and fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features
nWide supply voltage range from 1.65 V to 5.5 V
nVery low ON resistance:
u7.5 Ω (typical) at VCC = 2.7 V
u6.5 Ω (typical) at VCC = 3.3 V
u6Ω (typical) at VCC =5V
nSwitch current capability of 32 mA
nHigh noise immunity
nCMOS low-power consumption
nTTL interface compatibility at 3.3 V
nLatch-up performance meets requirements of JESD 78 Class I
nESD protection:
uHBM JESD22-A114E exceeds 2000 V
uMM JESD22-A115-A exceeds 200 V
uCDM JESD22-C101C exceeds 1000 V
nControl inputs accepts voltages up to 5 V
nMultiple package options
nSpecified from −40 °C to +85 °C and from −40 °C to +125 °C
74LVC2G53
2-channel analog multiplexer/demultiplexer
Rev. 05 — 18 June 2008 Product data sheet
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 2 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
3. Ordering information
4. Marking
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC2G53DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm SOT505-2
74LVC2G53DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm SOT765-1
74LVC2G53GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1
74LVC2G53GD −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm SOT996-2
74LVC2G53GM −40 °C to +125 °C XQFN8U plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 ×1.6 ×0.5 mm SOT902-1
Table 2. Marking codes
Type number Marking code
74LVC2G53DC V53
74LVC2G53DP V53
74LVC2G53GT V53
74LVC2G53GD V53
74LVC2G53GM V53
Fig 1. Logic symbol
001aah795
S
Z
E
Y0
Y1
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 3 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
Fig 2. Logic diagram
001aad387
Z
Y0
S
Y1
E
Fig 3. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8) Fig 4. Pin configuration SOT833-1 (XSON8)
74LVC2G53
ZV
CC
EY0
GND Y1
GND S
001aae798
1
2
3
4
6
5
8
7
74LVC2G53
Y1
Y0
VCC
S
GND
E
Z
GND
001aae800
36
27
18
45
Transparent top view
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 4 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Fig 5. Pin configuration SOT996-2 (XSON8U) Fig 6. Pin configuration SOT902-1 (XQFN8U)
001aai274
74LVC2G53
Transparent top view
8
7
6
5
1
2
3
4
Z
E
GND
GND
VCC
Y0
Y1
S
001aag724
EY1
Z
VCC
GND
Y0
GND
S
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
74LVC2G53
Table 3. Pin description
Symbol Pin Description
SOT505-2, SOT765-1, SOT996-2 and
SOT833-1 SOT902-1
Z 1 7 common output or input
E 2 6 enable input (active LOW)
GND 3 5 ground (0 V)
GND 4 4 ground (0 V)
S 5 3 select input
Y1 6 2 independent input or output
Y0 7 1 independent input or output
VCC 8 8 supply voltage
Table 4. Function table[1]
Input Channel on
S E
L L Y0 to Z or Z to Y0
H L Y1 to Z or Z to Y1
X H Z (switch off)
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 5 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
8. Limiting values
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3] For TSSOP8 packages: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
[1] To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit
for the voltage drop across the switch.
[2] Applies to control signal levels.
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +6.5 V
VIinput voltage [1] −0.5 +6.5 V
IIK input clamping current VI<−0.5 V or VI>V
CC + 0.5 V −50 - mA
ISK switch clamping current VI<−0.5 V or VI>V
CC + 0.5 V - ±50 mA
VSW switch voltage enable and disable mode [2] −0.5 VCC + 0.5 V
ISW switch current VSW >−0.5 V or VSW < VCC + 0.5 V - ±50 mA
ICC supply current - 100 mA
IGND ground current −100 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb =−40 °C to +125 °C[3] - 250 mW
Table 6. Operating conditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 1.65 5.5 V
VIinput voltage 0 5.5 V
VSW switch voltage enable and disable mode [1] 0V
CC V
Tamb ambient temperature −40 +125 °C
∆t/∆V input transition rise and fall rate VCC = 1.65 V to 2.7 V [2] - 20 ns/V
VCC = 2.7 V to 5.5 V [2] - 10 ns/V
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 6 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
10. Static characteristics
[1] Typical values are measured at Tamb =25°C.
[2] These typical values are measured at VCC = 3.3 V.
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter Conditions Tamb =−40 °C to +85 °C Tamb =−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC - - 0.65 × VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 3 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7 × VCC - - 0.7 × VCC -V
VIL LOW-level
input voltage VCC = 1.65 V to 1.95 V - - 0.35 ×VCC - 0.35 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 3 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 × VCC 0.3 × VCC V
IIinput leakage
current pin S and pin E;
VI= 5.5 Vor GND;
VCC = 0 V to 5.5 V
[2] -±0.1 ±2-±10 µA
IS(OFF) OFF-state
leakage
current
VI = VIH or VIL;
VCC = 5.5 V;
see Figure 7
[2] -±0.1 ±5-±20 µA
IS(ON) ON-state
leakage
current
VI = VIH or VIL;
VCC = 5.5 V;
see Figure 8
[2] -±0.1 ±5-±20 µA
ICC supply current VI= 5.5 V or GND;
VSW = GND or VCC;
IO=0A;
VCC = 1.65 V to 5.5 V
[2] - 0.1 10 - 40 µA
∆ICC additional
supply current pin S and pin E;
VI=V
CC −0.6 V;
IO=0A;
VSW = GND or VCC;
VCC = 5.5 V
[2] - 5 500 - 5000 µA
CIinput
capacitance - 2.5 - - - pF
CS(OFF) OFF-state
capacitance - 6.0 - - - pF
CS(ON) ON-state
capacitance -18- - -pF
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 7 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
10.1 Test circuits
10.2 ON resistance
VI=V
CC or GND; VO= GND or VCC.
Fig 7. Test circuit for measuring OFF-state leakage current
VO
IS
001aad390
S
ZE
Y0
Y1
VCC
GND
switch
switch
1
12
2
VIH
VIL
S
VIH
VIH
E
VI
VIL or VIH
VIH
VI=V
CC or GND and VO= open circuit.
Fig 8. Test circuit for measuring ON-state leakage current
IS
001aad391
S
ZE
Y0
Y1
VCC
GND
VI
VIL or VIH
VIL
switch
1
2V
IH
VIL
S
VIL
VIL
E
VO
switch
1
2
Table 8. ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
RON(peak) ON resistance (peak) VI= GND to VCC; see Figure 9
ISW = 4 mA;
VCC = 1.65 V to 1.95 V - 34.0 130 - 195 Ω
ISW = 8 mA; VCC = 2.3 V to 2.7 V - 12.0 30 - 45 Ω
ISW = 12 mA; VCC = 2.7 V - 10.4 25 - 38 Ω
ISW = 24 mA; VCC = 3 V to 3.6 V - 7.8 20 - 30 Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V - 6.2 15 - 23 Ω
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 8 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
[1] Typical values are measured at Tamb =25°C and nominal VCC.
[2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
10.3 ON resistance test circuit and graphs
RON(rail) ON resistance (rail) VI= GND; see Figure 9
ISW = 4 mA;
VCC = 1.65 V to 1.95 V - 8.2 18 - 27 Ω
ISW = 8 mA; VCC = 2.3 V to 2.7 V - 7.1 16 - 24 Ω
ISW = 12 mA; VCC = 2.7 V - 6.9 14 - 21 Ω
ISW = 24 mA; VCC = 3 V to 3.6 V - 6.5 12 - 18 Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V - 5.8 10 - 15 Ω
VI=V
CC; see Figure 9
ISW = 4 mA;
VCC = 1.65 V to 1.95 V - 10.4 30 - 45 Ω
ISW = 8 mA; VCC = 2.3 V to 2.7 V - 7.6 20 - 30 Ω
ISW = 12 mA; VCC = 2.7 V - 7.0 18 - 27 Ω
ISW = 24 mA; VCC = 3 V to 3.6 V - 6.1 15 - 23 Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V - 4.9 10 - 15 Ω
RON(flat) ON resistance
(flatness) VI= GND to VCC [2]
ISW = 4 mA;
VCC = 1.65 V to 1.95 V - 26.0 - - - Ω
ISW = 8 mA; VCC = 2.3 V to 2.7 V - 5.0 - - - Ω
ISW = 12 mA; VCC = 2.7 V - 3.5 - - - Ω
ISW = 24 mA; VCC = 3 V to 3.6 V - 2.0 - - - Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V - 1.5 - - - Ω
Table 8. ON resistance
…continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
RON = VSW / ISW.
Fig 9. Test circuit for measuring ON resistance
ISW
VSW
001aad392
S
ZE
Y0
Y1
VCC
GND
switch
switch
1
12
2
VIH
VIL
S
VIL
VIL
E
VI
VIL or VIH
VIL
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 9 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
(1) VCC = 1.8 V.
(2) VCC = 2.5 V.
(3) VCC = 2.7 V.
(4) VCC = 3.3 V.
(5) VCC = 5.0 V.
Fig 10. Typical ON resistance as a function of input voltage; Tamb = 25 °C
VI (V)
054231
mna673
20
10
30
40
RON
(Ω)
0
(1)
(2)
(3)
(4) (5)
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
Fig 11. ON resistance as a function of input voltage;
VCC = 1.8 V Fig 12. ON resistance as a function of input voltage;
VCC = 2.5 V
VI (V)
0 2.01.60.8 1.20.4
001aaa712
25
35
15
45
55
RON
(Ω)
5
(4)
(3)
(2)
(1)
VI (V)
0 2.52.01.0 1.50.5
001aaa708
9
11
7
13
15
RON
(Ω)
5
(1)
(2)
(3)
(4)
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 10 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
Fig 13. ON resistance as a function of input voltage;
VCC = 2.7 V Fig 14. ON resistance as a function of input voltage;
VCC = 3.3 V
001aaa709
VI (V)
0 3.02.01.0 2.51.50.5
9
7
11
13
RON
(Ω)
5
(1)
(2)
(3)
(4)
VI (V)
04312
001aaa710
6
8
10
RON
(Ω)
4
(1)
(2)
(3)
(4)
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
Fig 15. ON resistance as a function of input voltage; VCC = 5.0 V
VI (V)
054231
001aaa711
5
4
6
7
RON
(Ω)
3
(2)
(4)
(1)
(3)
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 11 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
11. Dynamic characteristics
[1] Typical values are measured at Tamb =25°C and nominal VCC.
[2] tpd is the same as tPLH and tPHL.
[3] Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPLZ and tPHZ.
Table 9. Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
tpd propagation delay Z to Yn or Yn to Z; see Figure 16 [2][3]
VCC = 1.65 V to 1.95 V - - 2 - 2.5 ns
VCC = 2.3 V to 2.7 V - - 1.2 - 1.5 ns
VCC = 2.7 V - - 1.0 - 1.25 ns
VCC = 3.0 V to 3.6 V - - 0.8 - 1.0 ns
VCC = 4.5 V to 5.5 V - - 0.6 - 0.8 ns
ten enable time S to Z or Yn; see Figure 17 [4]
VCC = 1.65 V to 1.95 V 2.6 6.7 10.3 2.6 12.9 ns
VCC = 2.3 V to 2.7 V 1.9 4.1 6.4 1.9 8.0 ns
VCC = 2.7 V 1.9 4.0 5.5 1.8 7.0 ns
VCC = 3.0 V to 3.6 V 1.8 3.4 5.0 1.8 6.3 ns
VCC = 4.5 V to 5.5 V 1.3 2.6 3.8 1.3 4.8 ns
E to Z or Yn; see Figure 17 [4]
VCC = 1.65 V to 1.95 V 1.9 4.0 7.3 1.9 9.2 ns
VCC = 2.3 V to 2.7 V 1.4 2.5 4.4 1.4 5.5 ns
VCC = 2.7 V 1.1 2.6 3.9 1.1 4.9 ns
VCC = 3.0 V to 3.6 V 1.2 2.2 3.8 1.2 4.8 ns
VCC = 4.5 V to 5.5 V 1.0 1.7 2.6 1.0 3.3 ns
tdis disable time S to Z or Yn; see Figure 17 [5]
VCC = 1.65 V to 1.95 V 2.1 6.8 10.0 2.1 12.5 ns
VCC = 2.3 V to 2.7 V 1.4 3.7 6.1 1.4 7.7 ns
VCC = 2.7 V 1.4 4.9 6.2 1.4 7.8 ns
VCC = 3.0 V to 3.6 V 1.1 4.0 5.4 1.1 6.8 ns
VCC = 4.5 V to 5.5 V 1.0 2.9 3.8 1.0 4.8 ns
E to Z or Yn; see Figure 17 [5]
VCC = 1.65 V to 1.95 V 2.3 5.6 8.6 2.3 11.0 ns
VCC = 2.3 V to 2.7 V 1.2 3.2 4.8 1.2 6.0 ns
VCC = 2.7 V 1.4 4.0 5.2 1.4 6.5 ns
VCC = 3.0 V to 3.6 V 2.0 3.7 5.0 2.0 6.3 ns
VCC = 4.5 V to 5.5 V 1.3 2.9 3.8 1.3 4.8 ns
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 12 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
11.1 Waveforms and test circuits
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Input (Yn or Z) to output (Z or Yn) propagation delays
tPLH tPHL
VM
VM
VM
VM
GND
VI
VOH
VOL
Yn or Z
input
Z or Yn
output
001aac361
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 17. Enable and disable times
VM
VI
GND
VCC
VOL
VOH
GND
S, E input
output
LOW to OFF
OFF to LOW
output
HIGH to OFF
OFF to HIGH
VM
001aad393
VM
tPZL
tPHZ tPZH
VX
VY
switch
disabled switch
enabled
switch
enabled
Z, Yn
Z, Yn
tPLZ
Table 10. Measurement points
Supply voltage Input Output
VCC VMVMVXVY
1.65 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH −0.15 V
2.7 V to 5.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH −0.3 V
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 13 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
11.2 Additional dynamic characteristics
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance (should be equal to output impedance Zo of the pulse generator).
CL = Load capacitance (including jig and probe capacitance).
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig 18. Load circuit for switching times
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
Table 11. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ
1.65 V to 1.95 V VCC ≤2.0 ns 30 pF 1 kΩopen GND 2VCC
2.3 V to 2.7 V VCC ≤2.0 ns 30 pF 500 Ωopen GND 2VCC
2.7 V VCC ≤2.5 ns 50 pF 500 Ωopen GND 2VCC
3 V to 3.6 V VCC ≤2.5 ns 50 pF 500 Ωopen GND 2VCC
4.5 V to 5.5 V VCC ≤2.5 ns 50 pF 500 Ωopen GND 2VCC
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); T
amb
=25
°
C.
Symbol Parameter Conditions Min Typ Max Unit
THD total harmonic distortion fi= 600 Hz to 20 kHz; RL= 600 Ω;
CL= 50 pF; VI= 0.5 V (p-p); see Figure 19
VCC = 1.65 V - 0.260 - %
VCC = 2.3 V - 0.078 - %
VCC = 3.0 V - 0.078 - %
VCC = 4.5 V - 0.078 - %
f(-3dB) −3 dB frequency response RL=50Ω; CL= 5 pF; see Figure 20
VCC = 1.65 V - 200 - MHz
VCC = 2.3 V - 300 - MHz
VCC = 3.0 V - 300 - MHz
VCC = 4.5 V - 300 - MHz
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 14 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
11.3 Test circuits
αiso isolation (OFF-state) RL=50Ω; CL= 5 pF; fi= 10 MHz;
see Figure 21
VCC = 1.65 V - −42 - dB
VCC = 2.3 V - −42 - dB
VCC = 3.0 V - −40 - dB
VCC = 4.5 V - −40 - dB
Qinj charge injection CL= 0.1 nF; Vgen =0V; R
gen =0Ω;
fi= 1 MHz; RL=1MΩ; see Figure 22
VCC = 1.8 V - 3.3 - pC
VCC = 2.5 V - 4.1 - pC
VCC = 3.3 V - 5.0 - pC
VCC = 4.5 V - 6.4 - pC
VCC = 5.5 V - 7.5 - pC
Table 12. Additional dynamic characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); T
amb
=25
°
C.
Symbol Parameter Conditions Min Typ Max Unit
Fig 19. Test circuit for measuring total harmonic distortion
D
001aad394
600 Ω
10 µF
0.1 µFS
Z
Y0
Y1
VCC 0.5VCC
GND
CL
RL
switch
switch
1
12
2
VIH
VIL
S
VIL
VIL
E
fi
VIL or VIH
E
VIL
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3dB.
Fig 20. Test circuit for measuring the frequency response when switch is in ON-state
dB
001aad395
50 Ω
0.1 µF
S
Z
E
Y0
Y1
VCC 0.5VCC
GND
CL
RL
switch
switch
1
12
2
VIH
VIL
S
VIL
VIL
E
fi
VIL or VIH
VIL
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 15 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Adjust fi voltage to obtain 0 dBm level at input.
Fig 21. Test circuit for measuring isolation (OFF-state)
dB
001aad396
50 Ω
RL
0.1 µFS
ZE
Y0
Y1
VCC 0.5VCC
0.5VCC
GND
CL
RL
switch
switch
1
12
2
VIL
VIH
S
VIH
VIH
E
fi
VIL or VIH
VIH
a. Test circuit
b. Input and output pulse definitions
Qinj =∆VO×CL.
∆VO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 22. Test circuit for measuring charge injection
001aad398
S
Z
Y0
Y1
RLCL
VCC
GND
Rgen
Vgen
switch
1
2
VIVO
E
VIL
G
001aac478
∆VO
offonoff
logic
input
VO
(S)
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 16 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
12. Package outline
Fig 23. Package outline SOT505-2 (TSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(1) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00 0.95
0.75 0.38
0.22 0.18
0.08 3.1
2.9 3.1
2.9 0.65 4.1
3.9 0.70
0.35 8°
0°
0.13 0.10.20.5
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.47
0.33
SOT505-2 - - - 02-01-16
wM
bp
D
Z
e
0.25
14
85
θ
A2A1
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
1.1
pin 1 index
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 17 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Fig 24. Package outline SOT765-1 (VSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(2) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00 0.85
0.60 0.27
0.17 0.23
0.08 2.1
1.9 2.4
2.2 0.5 3.2
3.0 0.4
0.1 8°
0°
0.13 0.10.20.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1 MO-187 02-06-07
wM
bp
D
Z
e
0.12
14
85
θ
A2A1
Q
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1
1
pin 1 index
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 18 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Fig 25. Package outline SOT833-1 (XSON8)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT833-1 - - -
MO-252
- - -
SOT833-1
07-11-14
07-12-07
DIMENSIONS (mm are the original dimensions)
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17 2.0
1.9 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
8
2
7
3
6
4
5
8×
(2)
4×
(2)
A
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 19 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Fig 26. Package outline SOT996-2 (XSON8U)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT996-2 - - -- - -
SOT996-2
07-12-18
07-12-21
UNIT A
max
mm 0.5 0.05
0.00 0.35
0.15 3.1
2.9 0.5 1.5 0.5
0.3 0.6
0.4 0.1 0.05
A1
DIMENSIONS (mm are the original dimensions)
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
0 1 2 mm
scale
b D
2.1
1.9
E e e1L L1
0.15
0.05
L2v w
0.05
y y1
0.1
C
y
C
y1
X
b
14
85
e1
eAC B
vMCw M
L2
L1
L
terminal 1
index area
B A
D
E
detail X
AA1
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 20 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Fig 27. Package outline SOT902-1 (XQFN8U)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT902-1 MO-255- - - - - -
SOT902-1
05-11-25
07-11-14
UNIT A
max
mm 0.5
A1
0.25
0.15
0.05
0.00 1.65
1.55 0.35
0.25 0.15
0.05
DIMENSIONS (mm are the original dimensions)
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
bDLe1
1.65
1.55
eE L1v
0.10.55 0.5
w
0.05
y
0.05 0.05
y1
0 1 2 mm
scale
X
C
y
C
y1
terminal 1
index area
terminal 1
index area
B A
D
E
detail X
A
A1
b
8
7
6
5
e1
e1
e
e
AC B
∅ vMC∅ wM
4
1
2
3
L
L1
metal area
not for soldering
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 21 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
13. Abbreviations
14. Revision history
Table 13. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
TTL Transistor-Transistor Logic
HBM Human Body Model
ESD ElectroStatic Discharge
MM Machine Model
CDM Charged Device Model
DUT Device Under Test
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC2G53_5 20080618 Product data sheet - 74LVC2G53_4
Modifications: •Added type number 74LVC2G53GD (XSON8U / SOT996-2 package)
74LVC2G53_4 20080228 Product data sheet - 74LVC2G53_3
74LVC2G53_3 20070828 Product data sheet - 74LVC2G53_2
74LVC2G53_2 20060331 Product data sheet - 74LVC2G53_1
74LVC2G53_1 20060110 Product data sheet - -
74LVC2G53_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 18 June 2008 22 of 23
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 June 2008
Document identifier: 74LVC2G53_5
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 5
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
10.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 7
10.3 ON resistance test circuit and graphs. . . . . . . . 8
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 11
11.1 Waveforms and test circuits . . . . . . . . . . . . . . 12
11.2 Additional dynamic characteristics . . . . . . . . . 13
11.3 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
16 Contact information. . . . . . . . . . . . . . . . . . . . . 22
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
