Winbond Bus Termination Regulator W83310DS/DG W83310DS Datasheet Revision History Pages 1 Dates Version Version on Web May/03 0.5 N.A. All versions before 0.5 are only for internal use. Main Contents 2 1 May/03 0.51 N.A. Typo corrected. 3 5 May/03 0.60 N.A. Electrical characteristics update. 4 5 Jul./03 0.61 N.A. Electrical characteristics update. 5 10,11 Feb./04 0.70 N.A. Package dimension outline and Thermal data. 6 11 Mar./04 0.71 N.A. Thermal data update. 7 All Sep./04 0.8 N.A. Add Pb-free part W83310DG. 1 May/05 0.9 N.A. Add DDR II support spec 8 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83310DS/DG PRELIMINARY 1. General Description The W83310DS/DG is a linear regulator provides a power achieves continuous 2.0Amp bi-directional sinking and driving capability for a high speed bus terminator application. The chip simply implements a stable power supply which tracks half of input power dynamically for bus terminator with a single chip; it's also can be fixed with the input of VREF1 and VREF2 pins following with setting of pin BOOT_SEL. The W83310DS/DG is promoted with small footprint 8-SOP 150mil power package. With W83310DS/DG design, a high integration, high performance, and cost-effective solution is promoted. 2. Features Regulates a bi-directional power with driving and sinking capability Provides achieve continuous 2.0Amp driving and sinking current Power MOSFET integrated Low external component count Low output voltage offset VCNTL Operates with +3.3V & 2.5 V power 8-SOP 150mil small power package Low cost and easy to use 3. Applications DDR/DDRII Bus Termination Regulator Active Termination Bus Intel(R) Springdale GMCH-VTT Support SSTL-2 SSTL-3 All Trademark and Brand name belong to their respective owners. 1 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY 4. Pin Configuration and Description - W83310DS/DG VIN 1 8 VREF2 GND 2 7 ENABLE VREF1 3 6 VCNTL VOUT 4 5 BOOT_SEL SYMBOL PIN FUNCTION VIN 1 Main power input pin. GND 2 Power ground. W83310DS/DG Internal reference voltage source 1. VREF1 3 Reference voltage on the pin will be referred with the value of pin BOOT_SEL set high. VOUT 4 Voltage output pin. BOOT_SEL 5 A signal for the chip reference voltage source selection. The function is designed for Intel(R) Springdale chipset GMCH_VTT application. VCNTL 6 Power for internal control logic use ENABLE 7 Chip function enable pin. 1: Enable; 0: Disable Internal reference voltage source 2. VREF2 8 Reference voltage of the pin will be referred with the value of pin BOOT_SEL set low. All Trademark and Brand name belong to their respective owners. 2 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY 5. Application Circuit - W83310DS/DG for DDR SDRAM Application 2.5VREF VRAM U1 C1 R1 1K 1 1000u 2 3 VREF2 GND ENABLE VREF1 4 DDRVTT R2 1K VIN VOUT VCTRL BOOTSEL 8 7 6 3VDUAL 5 C2 10u W83310DS C3 C4 1u 1500u ENABLE (0:DISABLE 1:ENABLE) C5 0.1U - W83310DS/DG for Intel(R) Springdale GMCH_VTT Application 2.5VREF CPU_VTT R1 R GMCH_VTT VCC2.5 R2 R C1 U1 1 1000u 2 3 R3 R GMCHVTT 4 VIN VREF2 GND ENABLE VREF1 VOUT VCTRL BOOTSEL 8 7 VCC3 6 5 C2 10u W83310DS/DG C3 C4 1u 1500u PWOK C5 0.1U BOOTSELECT BOOTSELECT=0 GMCHVTT=1.45V for Intel(R) NORTHWOOD CPU BOOTSELECT=1 GMCHVTT=1.225V for Intel(R) PRESCOTT CPU R1: R2: R3 = 4.66: 1.00: 5.44 ! #$ % % ! &'#! " " All Trademark and Brand name belong to their respective owners. 3 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY - Dual Layout of W83310DS/DG and W83310S-R2 for DDR VTT Application 2.5VREF VRAM R1 10K U1 C1 1 1000u 2 VIN GND 3 DDRVTT R2 10K VREF2 VREF1 4 VOUT ENABLE VCTRL BOOTSEL 8 7 6 3VDUAL 5 C5 100U W83310DS/DG C3 C4 1u 1500u C2 1u W83310S-R2, W83310DS/DG DUAL LAYOUT 6. Internal Block Diagram VCTRL VIN ENABLE VREF2 Control Logic VREF1 Control Logic Circuit VOUT BOOT_SEL GND All Trademark and Brand name belong to their respective owners. 4 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY 7. Electrical Characteristics AC CHARACTERISTICS Cout=1000uF, TA = 0C to +70C Parameter Symbol Output Offset Voltage Vos Min -5 Load Regulation Input Voltage Range Operating Current of VCNTL Short Current Limit VIN VCNTL ICNTL ILMT Typ 0 0.8 0.8 1.62 3.3 0.5 4.0 Max +5 Units mV % 3.63 3.63 1 Test Conditions Iout=0A Loading: 0A 2.0A Loading: 0A -2.0A V mA A No Load(Iout=0A) Note: Load regulation is tested by using a 1ms current pulse and VOUT measuring. Cout=1000uF, TA = 0C to +70C Parameter Symbol Output Offset Voltage Vos Min -5 Load Regulation Input Voltage Range Operating Current of VCNTL VIN VCNTL ICNTL 1.62 3.3 0.5 Max +5 3.63 3.63 1 0.2 1 BOOT_SEL Threshold Trigger 0.2 4.0 ILMT Units mV % 0.8 VREF1 Threshold trigger Short Current Limit Typ 0 0.8 0.8 Test Conditions Iout=0A Loading: 0A 2.0A Loading: 0A -2.0A V mA V V V V A No Load(Iout=0A) Output=High Output=Low BOOT_SEL=High BOOT_SEL=Low Note: Load regulation is tested by using a 1ms current pulse and VOUT measuring. Cout=1000uF, TA = 0C to +70C Parameter Symbol Output Offset Voltage Vos Min -5 Load Regulation Input Voltage Range Operating Current of VCNTL VIN VCNTL ICNTL 1.62 3.3 0.5 Max +5 3.63 3.63 1 0.2 1 BOOT_SEL Threshold Trigger 0.2 4.0 ILMT Units mV % 0.8 VREF2 Threshold trigger Short Current Limit Typ 0 0.8 0.8 Test Conditions Iout=0A Loading: 0A 2.0A Loading: 0A -2.0A V mA V V V V A No Load(Iout=0A) Output=High Output=Low BOOT_SEL=High BOOT_SEL=Low Note: Load regulation is tested by using a 1ms current pulse and VOUT measuring. All Trademark and Brand name belong to their respective owners. 5 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY 8. Typical Operating Waveform Load regulation with test condition - VCTRL=3.3V; VIN=2.5V; VOUT=1.225V; 2.0Amp pulse driving current. Load regulation with test condition - VCTRL=3.3V; VIN=2.5V; VOUT=1.225V; 2.0Amp pulse sinking current. All Trademark and Brand name belong to their respective owners. 6 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY Load regulation with test condition - VCTRL=3.3V; VIN=2.5V; VOUT=1.45V; 2.0Amp pulse driving current. Load regulation with test condition - VCTRL=3.3V; VIN=2.5V; VOUT=1.45V; 2.0Amp pulse sinking current. All Trademark and Brand name belong to their respective owners. 7 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY Load regulation with test condition - VCTRL=3.3V; VIN=2.5V; VOUT=1.25V; 2.0Amp pulse driving current. Load regulation with test condition - VCTRL=3.3V; VIN=2.5V; VOUT=1.25V; 2.0Amp pulse sinking current. All Trademark and Brand name belong to their respective owners. 8 Publication Release Date: 2005/May Revision 0.9 W83310DS/DG PRELIMINARY Short Current Limit - VCTRL = 3.3V - VCTRL = 3.6V All Trademark and Brand name belong to their respective owners. 9 Publication Release Date: 2005/May Revision 0.9 W83310DS PRELIMINARY 9. Package Dimension 8L Power SOP 150mil All Trademark and Brand name belong to their respective owners. 10 Publication Release Date: 2005/May Revision 0.90 W83310DS/DG PRELIMINARY 10. Thermal Performance Test on Four-Layer (2S2P) JEDEC Test Board o Package Power (W) PSOP-8 3.05 Component Temp. ( C) jc o Package Die Downset Lead Ambient ( C /W) 100 145 79 78 25 14.7 An area of 190mil*150mil on the top layer is use as a thermal pad for W83310DS and this is connected to the bottom layer by vias. The ja of the W83310DS mounted on this demo board is abo o o out 39 C /W.Assuming the TA=25 C and TJ=160 C,the maximum power dissipation is calculated as: PD(max)=(160-25)/39=3.46W 11. Ordering Information Part Number W83310DS Package Type Power SOP-8 Production Flow 12. How to Read the Top Marking W83 310DG 249GA W83 310DS 249GA Left line: Winbond logo st nd 1 & 2 line: W83310DS/DG - the part number 3rd line: Tracking code 318 G A 318: packages assembled in Year 03', week 18 G: assembly house ID; O means OSE, G means GR, etc. A: the IC version All Trademark and Brand name belong to their respective owners. 11 Publication Release Date: 2005/May Revision 0.90 W83310DS/DG PRELIMINARY Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Winbond Electronics Rm. 803, World Trade Square, Tower II (North America) Corp. 123 Hoi Bun Rd., Kwun Tong 2727 North First Street Kowloon, Hong Kong San Jose, California 95134 TEL: 852-27516023-7 TEL: 1-408-9436666 FAX: 852-27552064 FAX: 1-408-9436668 Taipei Office 9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. All Trademark and Brand name belong to their respective owners. 12 Publication Release Date: 2005/May Revision 0.90