MICRON TECHNOLOGY INC J4E D = 6111549 OO0e65? 7 BARN: SRAM 32K x 8 SRAM WvuS 1sv4 ff FEATURES * High speed: 20, 25, 30, 35, and 45ns _ PIN ASSIGNMENT (Top View) High-performance, low-power, CMOS double metal . Single +5 V7 (410%) power supply 28L/300/600 DIP 28L/300 SOJ 0. Easy memory expansion with CE and OE options (A-9, A-11, B-9, B-11) (E-8) Allinputs and outputs are TTL compatible A414 98 1 Voc Aidt a 28 Veg OPTIONS MARKING A122 271 WE a 3 28 han * Timing ; A7H3 267 Al3 A515 = -24 LAG 20ns access -20 AGU4 257 A8 nag 8 23 P Att 25ns access -25 A505. 240 a9 azde 21 fato 30ns access -30 Atd9 20 fl CE 35ns access 35 A4t6 23} Ail Aoqio = 19 1 OQ 45ns access 45 A347 221 0E Pap d i i ee Packa: A248 210A10 cvasgis 16h 005 ges CE ves} 14 15 P ba4 Plastic DIP (300 mil) None AIG9 200CE Plastic DIP (600 mil) WwW AO 410 191 DQ8 98L/LCC Cera OT oye < Dai 11 18} Dar (F-4) Ceramic DIP (600 mil) CW : Plastic SOJ (300 mil) Dy DQ2 412 17/1 DQ6 Ceramic LCC (28 pin) EC DQ3 413 164 DOS Ceramic LCC (82 pin) . ECW Vss 414 15} DQ4 Two Volt Data Retention L , * Temperature 28L ZIP Industrial (-40C to +85C)- IT (C-5) GENERAL DESCRIPTION oo al The Micron SRAM family employs high-speed, low- no alt? AM power CMOS designs using a four-transistor memory cell. M3 6 a4 AS Micron SRAMs are fabricated using double-layer metal, 16. WE double-layer polysilicon technology. Veo 7h le ata For flexibility inhigh speed memory applications, Micron At2 9b tio a7 offers chip enable (CE) and output enable (OF) on this or- AB THEss hao ag ganization. These enhancements can place the outputs ina AA 13h laa ag gfigsee high impedance state for additional flexibility in system AZ 15b:5 ie ae = design. AO 17 bs s an Writing to these devices is accomplished when write po2 191.." 18 bat M azn att enable (WE) and CE inputs are both LOW. Reading is ac- vss 21 b.,7322 088 as ae Ne complished when WE remains HIGH and CE and OE go pas 23{.,%|2 O04 Al 24H Ato LOW. The device offers a reduced power standby made por 256 act"}24 508 AG 2h boa - when disabled. This allows system designs to achieve low TE 7 |. 426 Dae pat f 13 aih oa7 standby power requirements. Fy 28 At0 Geaerweres All devices operate from a single +5V power supply and $3323388 all inputs and outputs are fully TTL compatible. wrscases 4-124 Micron Technology, Ine., reserves the right fo change products or specifications without notice. Tne wet te Mi cm Sha ithwvus isvs ff FUNCTIONAL BLOCK DIAGRAM V cc GND 2 s |. er Wi 5 | 8 262,144 - BIT E ; ul D>| MEMORY ARRAY 5 rh E = roo co . . O-e CE > L{ _,| (LSB) es oe oy Fy F WE COLUMN DECODER (LSB) POWER tt?tt?tett CA Ay A, A; Ay Ay Ay Ag. TRUTH TABLE MODE OE| CE WE pa POWER STANDBY X H xX HIGH-Z STANDBY READ L L H Q ACTIVE READ H L H HIGH-Z ACTIVE WRITE X L L D ACTIVE Myths BAAN esiVoltage on Vcc supply relative to Vss Storage Temperature (Ceramic) Storage Temperature (Plastic) ....... Power Dissipation Short Circuit Output Current ..sssserserssssasssssenccescesses Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (0C <T, < 70C; Vcc = 5.,0V + 10%) DESCRIPTION CONDITIONS SYMBOL| MIN MAX UNITS | NOTES Input High (Logic 1) Voltage _ Vin 2.2 Vec+1 Vv 1 Input Low (Logic 0) Voltage Vit -0.5 0.8 Vv 1,2 Input Leakage Current OV < Vin < Veo Iki 5 5 pA Output Leakage Current Output(s) Disabled, ILo 5 5 pA OV < Vout < Vec Output High Voltage lon = -4.0MA Vou 2.4 Vv 1 Output Low Voltage lo: = 8.0mMA VoL 0.4 Vv 1 ; MAX DESCRIPTION CONDITIONS SYMBOL -20 | -25 | -30 | -35 | -40 [uNits|NoTES Power Supply CEs Vit; Veo = MAX Current: Operating f = MAX = 1/'RC, Ice 1065; 95 | 95 | 90 | 90 |mA]} 3 Outputs Open Power Supply GE 2 Vin; Veo = MAX Current: Standby f = MAX = 1/'RC, IsBt 90 | 25 | 25 | 25] 25 |mA Outputs Open CE 2 Vee -0.2V; Voc = MAX . Vit s Vss +0.2V; Isp2 51515 ]7] 7 |mA Vin 2 Voc -0.2V; f= 0 CAPACITANCE DESCRIPTION CONDITIONS SYMBOL | MIN MAX UNITS NOTES Input Capacitance Ty = 25C; f = {MHz Cr 7 pF 4 Output Capacitance Vcc = 5V Co 5 pF 4 4-123 oe INVHS LS i er Sao PMc oweBD WHS Lsv4 ff T-46-23-14 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5, 13) (0C < T, $ 70C; Vee = 5V + 10%) -20 - 25 -30 -35 -45 DESCRIPTION SYM MIN | MAX | MIN MAX MIN | MAX | MIN | MAX | MIN | MAX | UNITS | NOTES READ Cycle . READ cycle time tac 20 25 30 35 45 ns Address access time AA 20 25 30 35 45 | ns Chip Enable access time tacE 20 25 30 35 45 | ns Output hold from address change | OH 3. 5 5 5 5 fis Chip Enable te output in Low-Z 'LZCE 6 6 6 6 6 ns Chip Disable to output in High-Z 'HZCE 9 9 12. 15 18 ns 6,7 Chip Enable to power-up time pu a 0 0 0 0 ns Chip Disable to power-down time pp 20 25 . 30 35 45 | ns Output Enable access time AOE 8 8 10 - 12 15 | ns Output Enable to output in Low-Z | 'LZOE | 0 0 0 0 0 ns Output Disable to output in High-Z | 'HZ0E 7 7 10 12 15 ns WRITE Cycle WRITE cycle time we | 20 20 25 30 | 3S ns Chip Enable to end of write tow 15 15 18 20 25 ns Address valid to end of write tAW 15 15 18 20 25 ns Address setup time tas 0 0 0 0 0 ns Address hold from end of write aH 0 0 0 0 0 ns Write pulse width twe 15 15 18 20 25 ns Data setup time os 10 10 12 15 20 ns Data hold time _'DH 0 0 0 0 0 ns Write Disable to outputinLow-Z | LZ2WE| 5 5 5 5 5 ns Write Enable to output in High-Z_ | 'HZWE 10 10 12 15 18 | ns 6 4-124 apn, Sh eo bin as 4 5g q ee behetsa aa a taal il ara I Sa aad 9 Sie Ra eee ER ae SOB iE. at Tee ei sks seer eS tae NR oll SO et ns MICRON TECHNOLOGY INC 3BE D MM 6332549 0002861 9 MENRN er eae T-46-23-14 AC TEST CONDITIONS -_ . sen *5V : Input pulse levels ....scccsssreseccceresens Vss to 3.0V |. Q { Q 80 4 Input rise and fall tiM@S .scsccsssssscecccsssecessosseceneessess 5ns 255 7 PF 255 7 oer * Input timing reference levels ......sersesserrsceeeseeces 1.5V Vv V oF Output reference levels... Fig.{OUTPUTLOAD Fig. 20UTPUTLOAD OUtPUt 1OAd ...sccsererecsesrseeersererees _ EQUIVALENT EQUIVALENT a 7 NOTES _ , > 1. All voltages referenced to Vss (GND). : 8, WE is HIGH for READ cycle. ) 2. -3.0V for pulse width<20ns. - - 9. Device is continuously selected. All chip enables held a 3, Icc is dependent on output loading and cycle rates. in their active state. ~ 4, This parameter is sampled. 10. Address valid prior to or coincident with latest 5, Test conditions as specified with the output loading occurring chip enable. a - as shown in Fig. 1 unless otherwise noted. 11, RC = Read Cycle Time. P 6. "HZCE, HZOR and 'HIZWE are specified with CL = 12, Chip enable (CE) and write enable (WE) can initiate = 5pF as in Fig. 2, Transition is measured + 500mV from and terminate a WRITE cycle. ; . : steady state voltage. 13. For automotive, industrial and extended temperature 2 7. Atany given temperature and voltage condifion, specifications refer to page 4-169. ; HZCE is less than 'LZCE. i DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) - DESCRIPTION CONDITIONS SYMBOL | MIN TYP MAX | UNITS | NOTES Vcc for Retention Data ; Vor 2 _ Vv Data Retention Current GE 2 (Voc -0.2V) | Vcc = 2v|_ Iccbr 95 300 pA Vin 2 (Vcc -0.2V ors0.2V |Vcc =3v 350 400 pA Chip Deselect to Data : Retention Time CDR 0 _ ns 4 Operation Recovery Time 'R 'RC ns 4,11 LOW Vcc DATA RETENTION WAVEFORM = DATA RETENTION MODE 4 Vcc 4.6V Yor >2V _, "4. topr : ta ; = YZ =" lh DON'T CARE RY UNDEFINED MUD eM tbteg haa aa ee 38E D - MM 6222549 O0028b2 O MANRN tlie cea ae ty 1 ' od , QW fi PB pe > FF _ READ CYCLE NO, 18:9 tac ADDR x VALID a a 8 taa : 'oH B PREVIOUS DATA VALID DATA VALID Wvus Lsv- ff} READ CYCLE NO. 27:8. 10 SO # PAARL yy a rab eat tac \ = . ~ . - CE \ r : tAOE _ ; . _4z0E st Po [. tHZQE | PY y OE \ tAcE _ ; ; : DATA VALID tep 4 DON'T CARE RRQ) UNDEFINEDMICRON TECHNOLOGY INC _ 386 ) MM 6122549 OOO28b3 2 WRITE CYCLE NO. 1 (Write Enable Controlled) 7 12 two ADDR cE We tos D DATA VALID a WRITE CYCLE NO. 2 (Chip Enable Controlled) 12 two ADDR q x taw | _itas [ tow TAH we we WLLL WLLL tos [ton T Do DATA VALID tHZzwe OKRA AAA AAA AAR KARA RRA KARR RRR RA AR RRR RRR ERY KR RII II IIH HII) HIGH-Z. DON'T CARE BY UNDEFINED MRN wets 3 4 \ we . . o . \ sim nena | Mae aaNet a a8