Mixed-Signal Front-End (MxFETM) Processor
For Broadband Applications
Preliminary Technical Data AD9863
FEATURES
• Receive path includes Dual 12 Bit Analog to
Digital Converters with Internal or External
Reference, 50 and 80 MSPS versions
• Transmit path includes Dual 12 Bit, 200 MSPS
Digital to Analog Converters with 1x, 2x, or 4x
Interpolation and Programmable Gain Control
• Internal Clock Distribution Block includes a
Programmable Phase-Locked-Loop and Timing
Generation circuitry allowing single or dual
reference clock operation
• 24 bit flexible I/O data interface allow various
interleaved or non-interleaved data transfers in
half-duplex mode and interleaved data
transfers in full-duplex mode
• Configurable through SPI compliant port or
MODE selection pins
• Independent Rx and Tx power down control
pins
• 64 Lead lfCSP package (9mmx9mm footprint)
APPLICATIONS
• Broadband Access
• Broadband LAN
• Communications (modems)
PRODUCT DESCRIPTION
The AD9863 is a member of the MxFETM family, a group of
integrated converters for the communications market. The AD9863
includes dual 12 bit Analog to Digital Converters (ADCs) and dual
12 bit Digital to Analog Converters (TxDACs). Two speed grades
are available, a -50 and -80. The -50 is optimized for ADC
sampling of 50 MSPS and less, while the -80 is optimized for ADC
sample rates between 50 MSPS and 80 MSPS. The dual TxDACs
operate at speeds up to 200 MHz and includes a bypassable 2x or
4x interpolation filter.. All devices are optimized for low power,
small form factor and provide a cost effective solution for the
broadband communication market.
The AD9863 utilizes two independent input clocks input for
controlling all system clocks. The ADC sampling rate is controlled
by the CLKIN1 input. The DAC sampling rate is controlled by the
CLKIN2 input and a Phase-Lock-Loop clock multiplier.
FUNCTIONAL BLOCK DIAGRAM
ADC
ADC
VIN+A
VIN-A
DATA
MUX
+
LATCH
VIN+B
VIN-B
DAC
DAC
IOUT+B
IOUT-B
DATA
LATCH
+
DEMUX
IOUT+A
IOUT-A
Tx Data
CLKIN1
Rx Data
PLL
Flexible
I/O Bus
[0:23]
LOW PASS
INTERPOLATION
FILTER
DAC CLOCK
ADC CLOCK
I/O
INTERFACE
CONFIGURATION
BLOCK
I/O Interface
Control
CLKIN2
A Flexible bi-directional 24 bit I/O bus is used to accommodate a
variety of custom digital back ends or open market DSPs. In half
duplex systems, the interface supports 24 bit parallel transfers or
12 bit interleaved transfers. In Full duplex systems, the interface
supports an interleaved 12 bit ADC bus and an interleaved 12 bit
Tx bus. The Flexible I/O bus reduces pin count and therefore
required package size
The AD9863 can use either mode pins or a serial programmable
interface (SPI) to configure the interface bus, operate the ADC in a
low power mode, configure the TxDAC interpolation rate, control
the ADC power down and TxDAC power down. The SPI allows
for more programmable options for both the TxDAC path (for
example, coarse and fine gain control, offset control for channel
matching) and ADC path (for example, internal duty cycle
stabilizer, 2’s complement data format).
The AD9863 is packaged in a 64 pin lfCSP package (low profile,
fine pitch chip scale package). The 64 pin lfCSP package footprint
is only 9mm by 9mm and is less than 0.9 mm high fitting into
tightly spaced applications such as PCMCIA cards.
Rev. PrA 03/6/2003
Information furnished by Analog Devices is believed to be accurate and reliable. However,
no responsibility is assumed by Analog Devices for its use, nor for any infringements of
patents or other rights of third parties that may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 2 of 28
TABLE OF CONTENTS
Features..........................................................................................1
Applications ...................................................................................1
Product Description.......................................................................1
Revision History .............................................................................2
AD9863 SPECIFICATIONS ..................................................................3
Timing Specifications.........................................................................5
Explanation of Test Levels ................................................................5
Test Level..........................................................................................5
Absolute Maximum Ratings ..................................................................6
ESD CAUTION...............................................................................6
Ordering Guide ...................................................................................6
Definitions................................................................................................7
DESCRIPTION........................................................................................9
System Block Description ..................................................................9
AD9863 Rx Path Block Description .................................................9
AD9863 Tx Path Block Description ...............................................12
AD9863 Digital Block Description.................................................15
AD9863 Flexible I/O Interface Options.....................................15
Configuring with Mode Pins.......................................................19
AD9863 Clock Distribution Block .............................................21
SPI Register Map...........................................................................22
AD9863 Pin Configuration..................................................................27
Timing Diagram ....................................................................................28
REVISION HISTORY
Revision PrA: Initial Version
Preliminary Technical Data AD9863
AD9863 Rev. PrA | Page 3 of 28
AD9863 SPECIFICATIONS
AD9863—Specifications1 (Analog and digital supplies = 3.0V; FCLKIN1 = FCLKIN2 = 50 MHz; PLL 4x setting; Normal Timing Mode
TxDAC settings: FDAC = 200 MSPS; 4x interpolation; RSET = ?? kOhms; Differential load resistance of ?? Ohms; TxPGA = 20 dB;
RxADC settings: FADC = 50 MSPS; INT ref; differential analog inputs; unless otherwise noted)
Tx Path Parameters
Temp
Test
Level
Min
AD9863-50/-80
Typ
Max
Unit
Resolution Full 12 Bits
Maximum DAC Update Rate Full 200 MHz
Maximum Full Scale Output Current Full 20 mA
Gain Mismatch Error -3 +3 % FS
Offset Mismatch Error -1 +1 % FS
Update Timing Mismatch Error ps
Reference Voltage 1.23 V
Output Capacitance 5 pF
Phase Noise (1kHz offset, 6 MHz tone) dBc/Hz
Tx PATH GENERAL
Output Voltage Compliance Range -1.0 1.0 V
Integral Nonlinearity (INL) Lsb
Differential Nonlinearity (DNL) Lsb
TxPGA Gain Range 20 dB
Tx PATH DC
ACCURACY
TxPGA Step Size 0.08 dB
SNR
dBc
SINAD
dBc
THD
dBc
SFDR, Wideband (dc to Nyquist) dBc
Tx PATH DYNAMIC
PERFORMANCE
(Ioutfs = ?; Fout = ?)
SFDR, Narrowband (1 MHz Window) dBc
Table 1
Rx Path Parameters
Temp
Test
Level
Min
AD9863-50/-80
Typ
Max
Unit
Resolution Full 12 Bits
Maximum ADC Sample Rate Full 50 / 80 MSPS
Gain Mismatch Error ± 0.2 % FS
Offset Mismatch Error ± 0.1 % FS
Phase Mismatch Error
Reference Voltage 1 V
Reference Voltage (REFT-REFB) Error ± 6 mV
Input Resistance (differential) 2 kOhm
Input Capacitance 5 pF
Input Bandwidth (-3dB) 50 MHz
Rx PATH GENERAL
Analog Voltage Input Range 2 V
Integral Nonlinearity (INL) ± 0.75 LSB
Differential Nonlinearity (DNL) ± 0.75 LSB
Aperature Delay 2.0 ns
Aperature Uncertainty (Jitter) 1.2 ps RMS
Rx PATH DC
ACCURACY
Input Refered Noise
SNR 64 dBc
SINAD 63 dBc
THD (2nd to 9th harmonic) -80 dBc
SFDR, Wideband (dc to Nyquist) 82 dBc
Rx PATH DYNAMIC
PERFORMANCE
(Ioutfs = ?; Fout = ?)
Crosstalk between ADC inputs >80 dB
1 Specifications subject to change without notice
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 4 of 28
AD9863—Specifications1 (Analog and digital supplies = 3.0V; FCLKIN1 = FCLKIN2 = 50 MHz; PLL 4x setting; Normal Timing Mode
TxDAC settings: FDAC = 200 MSPS; 4x interpolation; RSET = ?? kOhms; Differential load resistance of ?? Ohms; TxPGA = 20 dB
RxADC settings: FADC = 50 MSPS; INT ref; differential analog inputs; unless otherwise noted)
Power Parameters
Temp
Test Level
Min
AD9863-50/-80
Typ
Max
Unit
Analog Supply Voltage (AVDD) Full 2.7 3.6 V
Digital Supply Voltage (DVDD) Full 2.7 3.6 V
POWER SUPPLY
RANGE
Driver Supply Voltage (DRVDD) Full 2.7 3.6 V
TxPath (20 mA full scale outputs) Full 65 mA
TxPath (5mA full scale outputs) Full 35 mA
Rx Path (-80, at 80 MSPS) Full 140 mA
RxPath (-80, at 80 MSPS, Low
Power Mode)
Full 80 mA
Rx Path (-50, at 50 MSPS) 90 mA
RxPath (-50, at 50 MSPS, Low
Power Mode)
50 mA
RxPath )-50, at 25 MSPS, Low
Power Mode)
45 mA
TxPath, Power Down Mode 5 mA
RxPath, Power Down Mode 5 mA
ANALOG SUPPLY
CURRENTS
PLL 15 mA
TxPath, 1x interpoaltion, 50
MSPS DAC update for both
DACs
40 mA
TxPath, 2x interpoaltion, 100
MSPS DAC update for both
DACs
80 mA
TxPath, 4x interpoaltion, 200
MSPS DAC update for both
DACs
120 mA
DIGITAL SUPPLY
CURRENTS
RxPath Digital 15 mA
Table 3: Specifications
Digital Parameters
Temp
Test
Level
Min
AD9863-50/-80
Typ
Max
Unit
Input Logic ‘1’ Voltage, Vih DRVDD
– 0.7
V
Input Logic ‘0’ Voltage, Vil 0.4 V
Output Logic ‘1’ Voltage, Voh
(1mA load)
DRVDD
– 0.6
V
LOGIC LEVELS
Output Logic ‘0’ Voltage, Vol
(1mA load)
0.4 V
Input Leakage Current 12 uA
Input Capacitance 3 pF
Minimum RESET Low
Pulsewidth
5 Input
Clock
Cycles
DIGITAL PIN
Digital Output Rise/Fall Time 2.8 4 ns
Table 4: Specifications
1 Specifications subject to change without notice
Preliminary Technical Data AD9863
AD9863 Rev. PrA | Page 5 of 28
AD9863—Specifications1 (Analog and digital supplies = 3.0V; FCLKIN1 = FCLKIN2 = 50 MHz; PLL 4x setting; Normal Timing Mode
TxDAC settings: FDAC = 200 MSPS; 4x interpolation; RSET = ?? kOhms; Differential load resistance of ?? Ohms; TxPGA = 20 dB
RxADC settings: FADC = 50 MSPS; INT ref; differential analog inputs; unless otherwise noted)
TIMING SPECIFICATIONS
Timing Parameters
Temp
Test
Level
Min
AD9863-50/-80
Typ
Max
Unit
CLKIN1 Clock Rate 1 80 MHz
CLKIN1 Pulse Width High
CLKIN1 Pulse Width Low
CLKIN2 Clock Rate
1 200 MHz
CLKIN2 Pulse Width High
CLKIN2 Pulse Width Low
PLL Input Frequnecy 16 200
INPUT CLOCK
PLL Ouput Frequency 32 350
Setup time (time required before data latching
edge)
1.5 ns
Hold time (time required after data latching
edge)
2.1 ns
Latency 1x interpolation
Latency 2x interpolation
Latency 4x interpolation
TxPATH DATA
Wakeup Time from Power Down
Output Delay
Latency
Aperture Delay
Aperture Unceratinty
RxPATH DATA
Wakeup Time from Power Down
Table 5:Specifications
EXPLANATION OF TEST LEVELS
TEST LEVEL
I 100% production tested.
II 100% production tested at +25°C and guaranteed by design and characterization at specified temperatures.
III Sample Tested Only
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at +25°C and guaranteed by design and characterization for industrial temperature range.
1 Specifications subject to change without notice
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Parameter Rating
AVDD Voltage 3.9 V max
DRVDD Voltage 3.9 V max
Analog Input Voltage -0.3 V to AVDD + 0.3 V
Digital Input Voltage -0.3 V to DVDD – 0.3 V
Electrical
Digital Output Current 5 mA max
Operating Temperature Range (Ambient) -40°C to +85°C
Maximum Junction Temperature 150°C
Lead Temperature (Soldering, 10 sec) 300°C
Environmental
Storage Temperature Range (Ambient) -65°C to +150°C
Table 6: Absolute Maximum Ratings
Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary
ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model Temperature Range Description
AD9863 -40°C to +85°C (Ambient) 64-pin lfCSP
AD9863/PCB 25°C (Ambient) Evaluation Board
Table 7: Ordering Guide
© 2002 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A. C02959-0-11/02(0)
Preliminary Technical Data AD9863
AD9863 Rev. PrA | Page 7 of 28
DEFINITIONS
Input Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the CLKIN1
command and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Crosstalk
Coupling onto one channel being driven by a -0.5 dBFS signal
when the adjacent interfering channel is driven by a full-scale
signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input
Impedance
The real and complex impedances measured at each analog input
port. The resistance is measured statically and the capacitance and
differential input impedances are measured with a network
analyzer.
Differential Analog Input Voltage Range
The peak to peak differential voltage that must be applied to the
converter to generate a full scale response. Peak differential voltage
is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180 degrees out
of phase. Peak to peak differential is computed by rotating the
inputs phase 180 degrees and taking the peak measurement again.
Then the difference is computed between both peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
02.6
76.1 dBSNR
ENOB MEASURED
−
=
Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that a signal
pulse should be left in logic “1” state to achieve rated performance;
pulse width low is the minimum time a signal should be left in low
state, logic “0”.
Full Scale Input Power
Expressed in dBm. Computed using the following equation:
=001.
log10
2
Input
Fullscale
Fullscale
Z
V
Power
rms
Gain Error
Gain error is the difference between the measured and ideal full
scale input voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the third
harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Noise (for any range within the ADC)
−−
=10
10*001.*
dBFSdBcdBm SignalSNRFS
noise ZV
Where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level and Signal is the signal level within the ADC reported in
dB below full scale. This value includes both thermal and
quantization noise.
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 8 of 28
Output Propagation Delay
The delay between a differential crossing of CLK+ and CLK- and
the time when all output data bits are within valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power
supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale) to
the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component may
or may not be a harmonic. It also may be reported in dBc (i.e.,
degrades as signal level is lowered) or dBFS (i.e., always related back
to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value of
the peak spurious component. The peak spurious component may
or may not be an IMD product. It also may be reported in dBc (i.e.,
degrades as signal level is lowered) or in dBFS (i.e., always relates
back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the worst
spurious component (excluding the second and third harmonic)
reported in dBc.
Transient Response Time
Transient response time is defined as the time it takes for the ADC
to reacquire the analog input after a transient from 10% above
negative full scale to 10% below positive full scale.
Out-of-Range Recovery Time
Out of range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above positive
full scale to 10% above negative full scale, or from 10% below
negative full scale to 10% below positive full scale.
Preliminary Technical Data AD9863
AD9863 Rev. PrA | Page 9 of 28
DESCRIPTION
SYSTEM BLOCK DESCRIPTION
The AD9863 is targeted to cover the mixed signal front end needs
of multiple wireless communication systems. It features a receive
path that consists of dual 12 bit receive ADCs and a transmit path
that consists of dual 12 bit transmit DACs (TxDACTM). The
AD9863 integrates additional functionality typically required in
most systems, such as Tx gain control and clock multiplication
circuitry.
The AD9863 minimizes both size and power consumption to
address the need of the portable market. The package is a 64 pin
low profile, fine pitched chip scale package (lfCSP) that has a
footprint of only 9 mm by 9mm. Power consumption is optimized
to suit the particular application with power down controls, a low
power ADC mode, a sub-50 MHz speed grade (AD9863-50) and
half duplex mode which automatically disable the unused digital
path.
The following sections discuss the three main blocks of the
AD9863: Rx Block, Tx Block and the Digital Block (contain
Clock Generation Block).
AD9863 RX PATH BLOCK
DESCRIPTION
The AD9863 Rx path consists of two 12 bit, 50 MSPS (for the
AD9863-50) or 80 MSPS (for the AD9863-80) analog-to-digital
converters (ADCs). The dual ADC paths share the same clocking
and reference circuitry to provide optimal matching characteristics.
Each of the ADC’s consists of a 9 stage differential pipelined
switched capacitor architecture with output error correction logic.
The pipelined architecture permits the first stage to operate on a
new input sample, while the remaining stages operate on preceding
samples. Sampling occurs on the falling edge of the input clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the flash ADC
output to control a switched capacitor digital-to-analog converter
(DAC) of the same resolution. The DAC output is subtracted from
the stage’s input signal and the residual is amplified (multiplied) to
drive the next pipeline stage. The residual multiplier stage is also
called a multiplying DAC (MDAC). One bit of redundancy is used
in each one of the stages to facilitate digital correction of flash
errors. The last stage simply consists of a flash ADC.
The differential input stage is dc self biased and allows differential
or single-ended inputs. The output-staging block aligns the data,
carries out the error correction, and passes the data to the output
buffers.
The latency of the Rx path is about 5 clock cycles.
Analog Input Equivalent Circuit
The Rx Path analog inputs of the AD9863 incorporate a novel
structure that merges the function of the input sample-and-hold
amplifiers (SHA) and the first pipeline residue amplifiers into a
single, compact switched capacitor circuit. This structure achieves
considerable noise and power savings over a conventional
implementation that uses separate amplifiers by eliminating one
amplifier in the pipeline.
The figure below illustrates the equivalent analog inputs of the
AD9863 (a switched capacitor input). Bringing CLK to a logic
high opens Switch S3 and closes Switches S1 and S2. The input
source is connected to AIN and must charge capacitor CH during
this time. Bringing CLK to a logic low opens S2, and then Switch
S1 opens followed by closing S3. This puts the input in the hold
mode.
VIN+
VIN-
VCM
RIN
RIN
CIN
CIN
CH
CH
+
-
S1
S2
S3
Figure #. Differential Input Architecture
The structure of the input SHA places certain requirements on the
input drive source. The differential input resistors are typically 2k
ohms each. The combination of the pin capacitance, CIN, and the
hold capacitance, CH, is typically less than 5 pF. The input source
must be able to charge or discharge this capacitance to its 12-bit
accuracy in one-half of a clock cycle. When the SHA goes into
track mode, the input source must charge or discharge capacitor CH
from the voltage already stored on CH to the new voltage. In the
worst case, a full-scale voltage step on the input source must
provide the charging current through the RON (typically 100 ohms)
of Switch S1 and quickly (within 1/2 CLK period) settle. This
situation corresponds to driving a low input impedance. On the
other hand, when the source voltage equals the value previously
stored on CH, the hold capacitor requires no input current and the
equivalent input impedance is extremely high. Adding series
resistance between the output of the signal source and the VIN
pins reduce the drive requirements placed on the signal source. The
figure below shows this configuration.
VIN+
VIN-
CSHUNT
RSERIES
RSERIES
AD9863
Figure #. Typical Input
The bandwidth of the particular application limits the size of this
resistor. To maintain the performance outlined in the data sheet
specifications, the resistor should be limited to XX ohms or less.
For applications with signal bandwidths less than 10 MHz, the user
may proportionally increase the size of the series resistor.
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 10 of 28
Alternatively, adding a shunt capacitance between the AIN pins
can lower the ac load impedance. The value of this capacitance
will depend on the source resistance and the required signal
bandwidth. In systems that must use dc-coupling, use an op amp to
comply with the input requirements of the AD9863.
The ADCs in the AD9863 are designed to sample differential input
signals. The differential input provides the benefit of improved
noise immunity and better THD and SFDR performance for the Rx
path. In systems that use single ended signals, these inputs can be
digitized, but it is recommended that a single ended to differential
conversion is performed. A single ended to differential conversion
can be performed by using a transformer coupling circuit or using
an operational amplifier such as the AD8131, which can perform
the conversion.
The inputs accept a signal with a 2v pkpk differential input swing,
centered about one half of the supply voltage (AVDD/2). The Rx
input pins are self biased to provide this mid supply, common
mode bias voltage, so it is recommended to ac couple the signal to
the inputs.
ADC Voltage References
The AD9863 12 bit ADCs use internal references that are designed
to provide a 2 V p-p input (differential or 1V p-p single ended)
range. The internal bandgap reference generates a stable 1 V
reference level and is decoupled through the Vref pin. REFT and
REFB are the differential references generated based on the
voltage level of Vref. Figure 2 shows the proper decoupling of the
reference pins REFT and REFB when using the internal reference.
An external reference may be used for systems that require high
accuracy gain matching between multiple devices or improvements
in temperature drift and noise characteristics. External references
REFT and REFB will be centered at AVDD/2 with a differential
offset voltage corresponding to half the desired input span. For
example, for a 2V p-p differential input swing, the offset voltage
should be:
REFT: AVDD/2 + 0.5 V,
REFB: AVDD/2 – 0.5 V
The internal Rx bandgap reference can be bypassed and an external
reference used to drive the Vref voltage level. This is desirable for
example to accommodate a different fullscale input swing, an
extremely low temperature drift reference or to improve matching
across multiple converters. To supply an external reference, the
internal bandgap reference can be powered down through the SPI
and the external reference can be used to drive the Vref pin. The
resulting can be driven to the new voltages should be:
REFT: AVDD/2 +Vref/2 V,
REFB: AVDD/2 – Vref/2 V
If an external reference is used, it is not recommended to exceed a
differential offset voltage for the reference of greater than 1V. The
full scale, differential input voltage is 2x Vref voltage.
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be sensitive
to clock duty cycle. Commonly, a 5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9863 contains two clock duty cycle stabilizers (DCS), one
for each ADC in the Rx path that re-times the non-sampling edge,
providing an internal clock with a nominal 50% duty cycle. Input
clock rates of over 40 MHz can use the DCS so that a wide range
of input clock duty cycles can be accommodated (conversely, DCS
should not be used for Rx sampling below 40 MSPS). Maintaining
a 50% duty cycle clock is particularly important in high speed
applications, when proper track-and-hold times for the converter
are required to maintain high performance. The DCS can be
enabled by writing a high to the appropriate bits in registers 6 and
7.
The duty cycle stabilizer utilizes a delay locked loop to create the
nonsampling edge. As a result, any changes to the sampling
frequency will require approximately 2 to 3 microseconds to allow
the DLL to acquire and settle to the new rate. High speed, high
resolution ADCs converters are sensitive to the quality of the clock
input. The degradation in SNR at a given full-scale input frequency
(fINPUT) due only to aperture jitter (tA) can be calculated with the
following equation:
SNR degradation = 20 x log [ ½ (pi) x FIN x tA ]
In the equation, the rms aperture jitter, tA, represents the root-sum-
square of all jitter sources, which include the clock input, analog
input signal, and ADC aperture jitter specification. Undersampling
applications are particularly sensitive to jitter. The clock input is a
digital signal that should be treated as an analog signal with logic
level threshold voltages, especially in cases where aperture jitter
may affect the dynamic range of the AD9863. Power supplies for
clock drivers should be separated from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter crystal controlled oscillators make the best clock
sources. If the clock is generated from another type of source (by
gating, dividing, or other methods), it should be retimed by the
original clock at the last step.
POWER DISSIPATION AND STANDBY MODE
The power dissipated of the AD9863 Rx path is proportional to its
sampling rates. The Rx path portion of the digital (DRVDD) power
dissipation is determined primarily by the strength of the digital
drivers and the load on each output bit. The digital drive current
can be calculated by:
IDRVDD = VDRVDD x CLOAD x fCLOCK x N
where N is the number of bits changing and CLOAD is the average
Preliminary Technical Data AD9863
AD9863 Rev. PrA | Page 11 of 28
load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed grade
provides excellent performance while affording reduced power
consumption. Each speed grade dissipates a baseline power at low
sample rates that increases with clock frequency. The baseline
power dissipation for either speed grade can be reduced by
asserting the ADC_LO_PWR pin, which reduces internal ADC
bias currents by half at the sake of degraded performance.
Either of the ADCs in the AD9863 Rx path can be placed in
standby mode independently by writing to the appropriate SPI
register bits in Registers 3, 4 and 5. The minimum standby power
is achieved when both channels are placed in full power down
mode using the appropriate SPI register bits in Registers 3, 4 and 5.
Under this condition, the internal references are powered down.
When either or both of the channel paths are enabled after a power-
down, the wake-up time will be directly related to the recharging
of the REFT and REFB decoupling capacitors and the duration of
the power-down. Typically, it takes approximately 5 ms to restore
full operation with fully discharged 0.1 uF and 10 uF decoupling
capacitors on REFT and REFB.
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 12 of 28
AD9863 TX PATH BLOCK
DESCRIPTION
The AD9863 Transmit (Tx) path includes dual interpolating 12- bit
current output DACs that can be operated independently or
coupled to form a complex spectrum in an image reject transmit
architecture. Each channel includes two FIR filters, making the
AD9863 capable of 1x, 2x, or 4xinterpolation. High speed input
and output data rates can be achieved within the following
limitations:
Interpolation
Rate
24 bit
Interface
Mode
Input Data
Rate (MSPS)
per channel
DAC
Sampling
Rate (MSPS)
FD, HD12,
Clone
80 80 1x
HD24 160 160
FD, HD12,
Clone
80 160 2x
HD24 80 160
FD, HD12,
Clone
50 200 4x
HD24 50 200
By using the dual DAC outputs to form a complex signal, an
external analog quadrature modulator, such as the Analog Devices
AD8349, can enable an image rejection architecture. To optimize
the image rejection capability, as well as LO feed-through
suppression in this architecture, the AD9863 offers programmable
(via the SPI port) fine (trim) gain and offset adjust for each DAC.
Also included in the AD9863 are a phase-locked loop (PLL) clock
multiplier and a 1.2 V band gap voltage reference. With the PLL
enabled, a clock applied to the CLKIN2 input is multiplied
internally and generates all necessary internal synchronization
clocks. Each 12-bit DAC provides two complementary current
outputs whose full-scale currents can be determined from a single
external resistor.
An external pin, TxPwrDwn, can be used to power down the Tx
path when not used to optimize system power consumption. Using
the TxPwrDwn pin disables clocks and some analog circuitry
saving both digital and analog power. The power down mode
leaves the biases enabled to facilitate a quick recovery time
(typically < 10 us). Additional a SLEEP mode is available that
turns off the DAC output current, but leaves all other circuits
active, for a modest power savings. A SPI-compliant serial port is
used to program the many features of the AD9863. Note that in
power-down mode, the SPI port is still active.
DAC Equivalent Circuits
The AD9863 Tx Path consisting of dual 12-bit DACs is shown
below. The DACs integrates a high performance TxDAC core, a
programmable gain control through a Programmable Gain
Amplifier (TxPGA), coarse gain control, and offset adjustment and
fine gain control to compensate for system mismatches. Coarse
gain applies a gross scaling to either DAC by 1x, 1/2 x or 1/11x.
The TxPGA provides gain control from 0 dB to -20 dB in steps of
0.1 dB and is control via the 8 bit TxPGA setting. And a fine gain
adjustment of +/- 4% for each channel is controlled through a 6 bit
Fine Gain register. By default, coarse gain is 1x, the TxPGA is set
to 0 dB and the fine gain is set to 0%.
The TxDAC core of the AD9863 provides dual, differential,
complementary current outputs generated from the 12-bit data. The
12-bit Dual DACs support update rates up to 200 MSPS. The
differential outputs (i.e., IOUT+ and IOUT–) of each dual DAC
are complementary, meaning they always sum to the full-scale
current output of the DAC, IOUTFS. Optimum ac performance is
achieved with the differential current interface drives balanced
loads or a transformer.
The fine gain control allows for improved balance of QAM
modulated signals, resulting in improved modulation accuracy and
image rejection.
The independent DAC A and DAC B offset control adds a small dc
current to either IOUT+ or IOUT- (not both). The selection of
which IOUT this offset current is directed toward is programmable
via Register setting. Offset control can be used for suppression of
an LO leakage signal that typically results at the output of the
modulator. If the AD9863 is dc-coupled to an external modulator,
this feature can be used to cancel the output offset on the AD9863
as well as the input offset on the modulator.
The reference circuitry is shown in the Figure below.
Preliminary Technical Data AD9863
AD9863 Rev. PrA | Page 13 of 28
Referring to the transfer functions in the Equation below,
IOUTFSMAX is the maximum current output of the DAC with the
default gain setting (0 dB) and is based on a reference current, IREF.
IREF is set by the internal 1.2 V reference and the external RSET
resistor.
IOUTFSMAX = 64 x (REFIO[V] / RSET [Ohms])
Typically, RSET is 4 kohms, which sets IOUTFSMAX to 20 mA, the
optimal dynamic setting for the TxDACs. Increasing RSET by a
factor of 2 will proportionally decrease IOUTFSMAX by a factor of 2.
IOUTFSMAX of each DAC can be re-scaled either simultaneously
with the TxPGA Gain register or independently with DAC A/B
Coarse Gain registers.
The TxPGA function provides 20 dB of simultaneous gain range
for both DACs and is controlled by writing to SPI register TxPGA
Gain for a programmable full-scale output of 10% to 100%
IOUTFSMAX. The gain curve is linear in dB, with steps of about 0.1
dB. Internally, the gain is controlled by changing the main DAC
bias currents with an internal TxPGA DAC whose output is heavily
filtered via an on-chip R-C filter to provide continuous gain
transitions. Note, the settling time and bandwidth of the TxPGA
DAC can be improved by a factor of 2 by writing to the TxPGA
Fast register.
Each DAC has independent coarse gain control. Coarse gain
control can be used to accommodate different IOUTFS from the
dual DACs. The coarse full-scale output control can be adjusted
using the DAC A/B Coarse Gain registers to 1/2 or 1/11th of the
nominal full scale current.
Fine Gain controls and dc offset controls can be used to
compensate for mismatches (for system level calibration), allowing
improved matching characteristics of the two Tx channels and
aiding in suppressing LO feedthrough. This is especially useful in
image rejection architectures. The 10-bit dc offset control of each
DAC can be used independently to provide a +/-12% IOUTFSMAX of
offset to either differential pin, thus allowing calibration of any
system offsets. The fine gain control with 5-bit resolution allows
the IOUTFSMAX of each DAC to be varied over a +/-4% range, thus
allowing compensation of any DAC or system gain mismatches.
Fine gain control is set through the DAC A/B Fine Gain registers
and the offset control of each DAC is accomplished using DAC
A/B Offset registers.
CLOCK INPUT CONFIGURATION
The quality of the clock and data input signals is important in
achieving optimum performance. The external clock driver
circuitry should provide the AD9863 with a low jitter clock input
that meets the min/max logic levels while providing fast edges..
When a driver is used to buffer the clock input, it should be placed
very close to the AD9863 clock input, thereby negating any
transmission line effects such as reflections due to mismatch.
PROGRAMMABLE PLL
CLKIN2 can function either as an input data rate clock (PLL
enabled) or as a DAC data rate clock (PLL disabled).
The PLL clock multiplier and distribution circuitry produce the
necessary internal timing to synchronize the rising edge triggered
latches for the enabled interpolation filters and DACs. This
circuitry consists of a phase detector, charge pump, voltage
controlled oscillator (VCO) and clock distribution block, all under
SPI port control. The charge pump, phase detector and VCO are
powered from PLLVDD while the clock distribution circuits are
powered from the DVDD supply.
To ensure optimum phase noise performance from the PLL clock
multiplier circuits PLLVDD should
originate from a clean analog supply. The speed of the VCO within
the PLL also has an effect on phase noise.
The PLL will lock with a VCO speeds as low as 32 MHz up to 350
MHz, but optimal phase noise with respect to VCO speed is
achieved by running it in the range of 64 to 200 MHz.
POWER DISSIPATION
The AD9863 Tx Path power is derived from four voltage supplies:
AVDD, DVDD and DRVDD.
IDRVDD and IDVDD is very dependent on the input data rate, the
interpolation rate, and the activation of the internal digital
modulator. IAVDD has the same type of sensitivity to data,
interpolation rate, and the modulator function but to a much lesser
degree (<10%).
SLEEP/POWER-DOWN MODES
The AD9863 provides multiple methods for programmable power
saving modes. The externally controlled TxPwrDwn or SPI
programmed SLEEP mode and full power down mode are the main
options.
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 14 of 28
TxPwrDwn is used to disable all clocks and much of the analog
circuitry in the Tx path when asserted. In the mode, the biases
remain active therefore reducing the time required for re-enabling
the Tx path. Recovery from power down time for this mode is
typically less than 10 us.
The sleep mode, when activated, turns off the DAC output currents
but the rest of the chip remains functioning. When coming out of
sleep mode, the AD9863 will immediately return to full operation.
A full power-down mode can be enabled through the SPI register,
which turns off all Tx path related analog and digital circuitry in
the AD9863. When returning from full power-down mode, enough
clock cycles must be allowed to flush the digital filters of random
data acquired during the power-down cycle.
Interpolation Stage
Interpolation filters are available for use in the AD9863 transmit
path, providing 1x(bypassed), 2x, or 4x interpolation.
The interpolation filters effectively increase the Tx data rate while
suppressing the original images. The interpolation filters digitally
shift the worst case image further away from the desired signal,
thus reducing the requirements on the analog output reconstruction
filter.
There are two 2x interpolation filters available in the Tx path. An
interpolation rate of 4x is achieved using both interpolation filters;
an interpolation rate of 2x is achieved by enabling only the first 2x
interpolation filter.
The first interpolation filter provides 2x interpolation using a 39
tap filter. It suppresses out-of-band signals by 60 dB or more and
has a flat passband response (less than 0.1 dB ripple) extending to
38% of the AD9863 input Tx data rate (19% of the DAC update
rate, fDAC). The maximum input data rate is 80 MSPS per channel
when using 2x interpolation.
The second interpolation filter will provide an additional 2x
interpolation for an overall 4x interpolation. The second filter is a
15 tap filter. It suppresses out-of-band signals by 60 dB or more.
The flat passband response (less than 0.1 dB attenuation) is 38% of
the Tx input data rate (9.5% of fDAC). The maximum input data
rate per channel is 50 MSPS per channel when using 4x
interpolation.
Latch/Demultiplexer
Data for the dual channel Tx path can be latched in parallel
through 2 ports in half duplex operations (HD24 mode) or through
a single port by interleaving the data (FD, HD12 and Clone
modes). See the Flexible Interface section for further description
of each mode.
Preliminary Technical Data AD9863
AD9863 Rev. PrA | Page 15 of 28
AD9863 DIGITAL BLOCK DESCRIPTION
The AD9863 digital block allows the device to be configured in various timing and operation modes. The following sections discuss
the flexible I/O interfaces, the clock distribution block and programming of the device through Mode pins or SPI Registers.
AD9863 FLEXIBLE I/O INTERFACE OPTIONS
The AD9863 can accommodate various data interface transfer options (Flexible I/O). The AD9863 use two 12 bit buses, an upper bus
(U12) and a Lower bus (L12) to transfer the dual channel 12 bit ADCs and dual channel 12 bit DACs data by means of interleaved data, parallel
data or a mix of both. Below is a graphical look up table that shows the different I/O configurations between the modes depending on half
duplex or full duplex operation. After that a table summarizing the pin configuration and a summary of the mode is given.
U[0:11]
L[0:11]
IFACE1
IFACE2
IFACE3
AD9863
Tx_A Data
Tx_B Data
Tx/nRx
Output Clock
Output Clock
Digital
Back End
U[0:11]
L[0:11]
IFACE1
IFACE2
IFACE3
AD9863
Rx_B Data
Rx_A Data
Tx/nRx
Output Clock
Output Clock
Digital
Back End
Tx Only Mode
(Half Duplex)
Rx Only Mode
(Half Duplex)
Concurrent Tx+Rx Mode
(Full Duplex)
Mode Name: HD24
Rx Data Rate = 1 x ADC Sample Rate
Two 12 bit Parallel Rx Data Buses
Tx Data Rate = 1 x ADC Sample Rate
Two 12 bit Parallel Tx Data Buses
N/A
U[0:11]
L[11]
IFACE1
IFACE2
IFACE3
AD9863
Tx_A/B Data
Tx/nRx
Output Clock
Output Clock
Digital
Back End
TxSYNC
U[11]
L[0:11]
IFACE1
IFACE2
IFACE3
AD9863
Rx_A/B Data
Tx/nRx
Output Clock
Output Clock
Digital
Back End
RxSYNC Mode Name: HD12
Rx Data Rate = 2 x ADC Sample Rate
One12bitInterleavedRxDataBus
Tx Data Rate = 2 x ADC Sample Rate
One12bitInterleavedRxDataBus
N/A
HD24
HD12
FD
Clone
U[0:11]
L[0:11]
IFACE1
IFACE2
IFACE3
AD9863
Tx_A/B Data
Output Clock
Output Clock
Digital
Back End
TxSYNC
U[0:11]
L[0:11]
IFACE1
IFACE2
IFACE3
AD9863
Rx_A/B Data
Output Clock
Output Clock
Digital
Back End
Mode Name: FD
Rx Data Rate = 2 x ADC Sample Rate
One 12 bit Interleaved Rx Data Bus
Tx Data Rate = 2 x ADC Sample Rate
One 12 bit Interleaved Tx Data Bus
U[0:11]
L[0:11]
IFACE1
IFACE2
IFACE3
AD9863
Tx_A/B Data
Output Clock
Output Clock
Digital
Back End
TxSYNC
Rx_A/B Data
U[0:11]
L[0:11]
IFACE 1
IFACE 2
IFACE 3
AD9863
Rx_A Data
Rx_B Data
Tx/nRx
Output Clock
Output Clock
Digital
Back End
U[0:11]
L[11]
IFACE1
IFACE2
IFACE3
AD9863
Tx_A/B Data
Tx/nRx
Output Clock
Output Clock
Digital
Back End
TxSYNC
Mode Name: Clone
Rx Data Rate = 1 x ADC Sample Rate
Two 12 bit Parallel Rx Data Buses
Tx Data Rate = 2 x ADC Sample Rate
One 12 bit Interleaved Rx Data Bus
Requires SPI interface to configure;
similar to AD9862 data interface
N/A
General Notes
Mode
Name
Figure #. Graphical illustration of the flexible data interface modes.
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 16 of 28
AD9863 Pin Function vs. interface mode [No SPI cases]
Mode Name U12 L12 IFACE1 IFACE2 IFACE3
FD Interleaved Tx
Data
Interleaved Rx Data TxSYNC Buffered Rx Clock Buffered Tx Clock
HD12
(Tx/nRx=HI)
Interleaved Tx
Data
MSB=TxSYNC
Others=Tri-state
Tx/nRx = Tied HI 12/n24 pin control
Tied HIGH
Buffered Tx Clock
HD12
(Tx/nRx=LO)
MSB=RxSYNC
Other=Tri-state
Interleaved Tx Data Tx/nRx = Tied LO 12/n24 pin control
Tied HIGH
Buffered Rx Clock
HD24
(Tx/nRx=HI)
Tx_A Data Tx_B Data Tx/nRx = Tied HI 12/n24 pin control
Tied LO
Buffered Tx Clock
HD24
(Tx/nRx=LO)
Rx_B Data Rx_A Data Tx/nRx = Tied LO 12/n24 pin control
Tied LO
Buffered Rx Clock
Clone Mode
(Tx/nRx=HI)
Clone Mode
(Tx/nRx=LO)
CLONE MODE NOT AVAILABLE WITHOUT SPI
Table #. AD9863 Pin function (when Mode pins are used) relative to I/O mode, and for half duplex modes whether Transmitting or Receiving
AD9863 Pin Function vs. interface mode [configured through the SPI registers]
Mode Name U12 L12 IFACE1 IFACE2 IFACE3
FD Interleaved Tx Data Interleaved Rx Data TxSYNC Buffered System
Clock
Buffered Tx Clock
HD12
(Tx/nRx=HI)
Interleaved Tx Data MSB=TxSYNC
Others=Tri-state
Tx/nRx = Tied HI Buffered System
Clock
Buffered Tx Clock
HD12
(Tx/nRx=LO)
MSB=RxSYNC
Other=Tri-state
Interleaved Tx Data Tx/nRx = Tied LO Buffered System
Clock
Buffered Rx Clock
HD24
(Tx/nRx=HI)
Tx_A Data Tx_B Data Tx/nRx = Tied HI Buffered System
Clock
Buffered Tx Clock
HD24
(Tx/nRx=LO)
Rx_B Data Rx_A Data Tx/nRx = Tied LO Buffered System
Clock
Buffered Rx Clock
Clone Mode
(Tx/nRx=HI)
Interleaved Tx Data MSB=TxSYNC
Others=Tri-state
Tx/nRx = Tied HI Buffered System
Clock
Buffered Tx Clock
Clone Mode
(Tx/nRx=LO)
Rx_B Data Rx_A Data Tx/nRx = Tied LO Buffered System
Clock
Buffered Rx Clock
Table #. AD9863 Pin function (when SPI programming is used) relative to Flexible I/O mode, and for half duplex modes whether Transmitting
or Receiving
Preliminary Technical Data AD9863
AD9863 Rev. PrA | Page 17 of 28
Summary of Flexible I/O Modes
FD Mode (using Mode pins, additional flexibility available with SPI capability)
FD mode is the only mode that supports full duplex, receive and transmit concurrent operation. The Upper 12- bit bus (U12) is used to accept
Interleaved Tx Data and the Lower 12- bit bus (L12) is used to output Interleaved Rx data. Either the Rx path or the Tx path (or both paths) can
be independently powered down using either (or both) the RxPwrDwn and the TxPwrDwn pins. Below are some general notes regarding the FD
mode configuration, for more information see the FD Mode description in the next section.
General Tx Path Notes:
Clock input (CLKIN2) accepts 16 MHz to 80 MHz (2x interpolation) OR 8 MHz to 50 MHz (4x interpolation)
With SPI the PLL can be bypassed, in which case CLKIN2 accepts a master clock between 1 MHz to 200 MHz
Interpolation Rate (and PLL clock multiplication factor) of 2x or 4x programmed with Mode pins or SPI
Max DAC Update Rate = 200 MSPS, Max Tx Input Data Rate = 80 MSPS/channel (160 MSPS interleaved)
TxSYNC is used to direct Tx Input Data; TxSYNC=HI indicates channel Tx_A data, LO indicates Tx_B data
Buffered Tx Clock Output (from IFACE3 pin) equals 2 times the DAC update rate; 1 rising edge per interleaved Tx sample.
General Rx Path Notes:
Clock input (CLKIN1) accepts 1 MHz to 50 MHz input (AD9863-50) or 1 MHz to 80 MHz (AD9863-80)
Max ADC sampling rate = 50 MSPS (AD9863-50) OR 80 MSPS (AD9863-80)
Output Data rate = 2 times ADC sample rate = 2 x CLKIN1
Buffered Rx Clock Output (from IFACE2 pin) equal phase delayed CLKIN1 and is aligned with Rx output data
Rx path data output at 2 time CLKIN1; 2 Rx path data outputs per 1 Buffered Rx Clock Output cycle
Rx_A output while IFACE2 logic level = HI; Rx_B output when IFACE2 logic level = LO
HD12 Mode (using Mode pins, additional flexibility available with SPI capability)
HD12 mode supports half duplex only operations and can interface to a single 12 bit data bus with independent Rx and Tx synchronization pins
(RxSYNC and TxSYNC). Both the U12 and L12 buses are used on the AD9863, but the logic level of the Tx/nRx selector (controlled through
IFACE1 pin) is used to disable and tri-state the unused bus allowing U12 and L12 to be tied together. The MSB of the unused bus acts as the
RxSYNC (during Rx operation) or TxSYNC (during Tx operation). A single pin is used to output the clocks for Rx and Tx data latching (from
the IFACE3 pin) switching depending which path is enabled. Below are some general notes regarding the HD12 mode configuration, for more
information see the HD12 Mode description in the next section.
General Tx Path Notes:
Clock input (CLKIN2) accepts 16 MHz to 80 MHz (2x interpolation) OR 8 MHz to 50 MHz (4x interpolation)
With SPI the PLL can be bypassed, in which case CLKIN2 accepts a master clock between 1 MHz to 200 MHz
Interpolation Rate (and PLL clock multiplication factor) of 2x or 4x programmed with Mode pins or SPI
Interleaved Tx Data accepted on U12 bus, L12 bus MSB acts as TxSYNC
Max DAC Update Rate = 200 MSPS, Max Tx Input Data Rate = 80 MSPS/channel (160 MSPS interleaved)
TxSYNC is used to direct Tx Input Data; TxSYNC=HI indicates channel Tx_A data, LO indicates Tx_B data
Buffered Tx Clock Output (from IFACE3 pin) equals 2 times CLKIN2; 1 rising edge per interleaved Tx sample.
General Rx Path Notes:
AD9863: Clock input (CLKIN1) accepts 1 MHz to 50 MHz input (AD9863-50) or 1 MHz to 80 MHz (AD9863-80)
Max ADC sampling rate = 50 MSPS (AD9863-50) OR 80 MSPS (AD9863-80)
Output Data rate = 2 times ADC sample rate = 2 x CLKIN1
Interleaved Rx data output from L12 bus
Buffered Rx Clock Output (from IFACE3 pin) equal phase delayed CLKIN1
Rx path data output at 2 time CLKIN1; 2 Rx path data outputs per 1 Buffered Rx Clock Output cycle
Rx_A output while IFACE3 logic level = HI; Rx_B output when IFACE2 logic level = LO
HD24 Mode (using Mode pins, additional flexibility available with SPI capability)
HD24 mode supports half duplex only operations and can interface to a single 24 bit data bus (two parallel 12 bit buses). Both the U12 and L12
buses are used on the AD9863, but the logic level of the Tx/nRx selector (controlled through IFACE1 pin) is used to configure the buses as Rx
outputs (during Rx operation) or as Tx inputs (during Tx operation). A single pin is used to output the clocks for Rx and Tx data latching (from
the IFACE3 pin) switching depending which path is enabled. Below are some general notes regarding the HD24 mode configuration, for more
information see the HD24 Mode description in the next section.
General Tx Path Notes:
Clock input (CLKIN2) accepts 32 MHz to 200 MHz input
With SPI the PLL can be bypassed, in which case CLKIN2 accepts a master clock between 1 MHz to 200 MHz
Interpolation Rate (and PLL clock multiplication factor) of 1x, 2x or 4x programmed with Mode pins
Max DAC Update Rate = 200 MSPS, Max Tx Input Data Rate = 200 MSPS/channel, bypassed interpolation filters; 80 MSPS for 2x or
4x interpolation
Buffered Tx Clock Output (from IFACE3 pin) is a buffered version of CLKIN2
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 18 of 28
Tx_A output on U12 bus; Tx_B output on L12 bus
General Rx Path Notes:
AD9863: Clock input (CLKIN1) accepts 1 MHz to 50 MHz input (AD9863-50) or 1 MHz to 80 MHz (AD9863-80)
Max ADC sampling rate = 50 MSPS (AD9863-50) OR 80 MSPS (AD9863-80)
Output Data rate = ADC sample rate (= CLKIN1); two 12 bit parallel outputs per 1 Buffer Rx Clock Output cycle
Rx_A output on L12 bus; Rx_B output on U12 bus
Clone Mode (requires SPI programming)
Clone mode enables a half duplex interface similar to the AD9862 data interface. It provide parallel Rx data output (24 bits) while in Rx mode,
and accepts interleaved Tx data (12 bit) while in Tx mode. Both the U12 and L12 buses are used on the AD9863, but the logic level of the
Tx/nRx selector (controlled through IFACE1 pin) is used to configure the buses for Rx outputs (during Rx operation) or as Tx inputs (during Tx
operation). A single pin is used to output the clocks for Rx and Tx data latching (from the IFACE3 pin) depending upon which path is enabled.
Below are some general notes regarding the Clone mode configuration, for more information see the Clone Mode description in the next section.
General Tx Path Notes:
AD9863: Clock input (CLKIN2) accepts 16 MHz to 80 MHz (2x interpolation) OR 8 MHz to 50 MHz (4x interpolation)
Interpolation Rate (and PLL clock multiplication factor) of 2x or 4x programmed with Mode pins
Max DAC Update Rate = 200 MSPS, Max Tx Input Data Rate = 80 MSPS/channel (160 MSPS interleaved)
TxSYNC is used to direct Tx Input Data; TxSYNC=HI indicates channel Tx_A data, LO indicates Tx_B data
Buffered Tx Clock Output (from IFACE3 pin) equals 2 times CLKIN2; 1 rising edge per interleaved Tx sample.
General Rx Path Notes:
AD9863: Clock input (CLKIN1) accepts 1 MHz to 50 MHz input (AD9863-50) or 1 MHz to 80 MHz (AD9863-80)
Max ADC sampling rate = 50 MSPS (AD9863-50) OR 80 MSPS (AD9863-80)
Output Data rate = ADC sample rate (= CLKIN1); two 12 bit parallel outputs per 1 Buffer Rx Clock Output cycle
Rx_A output on L12 bus; Rx_B output on U12 bus
Preliminary Technical Data AD9863
AD9863 Rev. PrA | Page 19 of 28
CONFIGURING WITH MODE PINS
The Flexible interface can be configured with or without the SPI, although more options and flexibility are available when using
the SPI to program the AD9863. Mode pins can be used to power down sections of the device, reduce overall power
consumption, configure the flexible I/O interface and program the interpolation setting. The SPI register map which provides
many more options is discussed in the SPI Register section.
Mode Pins / Power Up Configuration options:
There are various options that are configurable at power up through mode pins and also control pins for power down modes. The
logic value of the configuration mode pins are latched when the device is brought out of reset (rising edge of RESETb). The
mode pin names and there function are shown in the table below.
Pin Name Duration Function
RxPwrDwn Permanent When high, digital clocks to Rx block are disabled.
Analog Blocks that require <10 us to power up are
powered off.
TxPwrDwn Permanent When high, digital clocks to Tx block are disabled
(PLL remains powered to maintain output clock with
an optional SPI shut off). Analog Blocks that require
<10 us to power up are powered off.
Tx/nRx Permanent only for HD Flex I/O
interface
When high, digital clocks to Tx block are disabled
(PLL remains powered to maintain output clock with
an optional SPI shut off). Tx Analog Blocks remain
powered up unless Tx_PwrDwn is asserted.
When low, digital clocks to Rx block are disabled. Rx
Analog Blocks remain powered up unless
Rx_PwrDwn is asserted.
ADC_LoPwr Defined at RESET or Power Up When enabled, this bit scales the ADC power down by
40%.
SPI_Bus_Enable Defined at RESET or Power Up This pin must remain low to maintain Mode pin
functionality (the SPI port remains nonfunctional).
FD/nHD Defined at RESET or Power Up Configures the Flex I/O for FD or HD mode
12/n24
only valid for HD
mode
Defined at RESET or Power Up If the Flex I/O bus is in HD mode, this bit is used to
configure parallel or interleaved data mode.
Interp0 and Interp1 Defined at RESET or Power Up These bits configure the PLL and interpolation rate to
1x, 2x or 4x
Configuring Using Mode Pins
ADC Low Power Mode Option
- ADC_LP is latched during the rising edge of RESET
o A logic low setting results in ADC operation at nominal power mode
o A logic high setting results in ADC consuming 40% less power than the nominal power mode
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 20 of 28
Flex I/O Configuration
- FD/nHD (SDO) is latched during the rising edge of RESET
o A logic low setting identifies that the DUT Flex I/O port will be configured for Half Duplex operation
12/n24 (IFACE2) is also latched during the rising edge of RESET to identify interleaved data mode or
parallel data modes
• A logic low indicates that the Flex I/O will configure itself for parallel data mode
• A logic high indicates that the Flex I/O will configure itself for interleaved data mode
Interpolation/PLL Factor Configuration
- SPI_CS is latched during the rising edge of RESET
o A logic low setting results in the SPI being disabled and SPI_DIO, SPI_CLK and SPI_SDO will be acting as mode pins
controlling Tx Interpolation rate and PLL setting
SPI_DIO and SPI_CLK config the Tx path for 1x, 2x or 4x interpolation (also enabling the PLL of the same
multiplication factor)
o A logic high setting results in the SPI being fully operational
Power Down Controls
- RxPwrDwn logic level controls the power down function of the Rx Path
o A logic low setting will result in the Rx path operating at normal power levels
o A logic high setting disables the ADC clock and disable some bias circuitry to reduce power consumption
- TxPwrDwn logic level controls the power down function of the Tx Path
o A logic low setting will result in the Tx path operating at normal power levels
o A logic high setting disables the DAC clocks and disable some bias circuitry to reduce power consumption
- Tx/nRx pin enables the appropriate Tx or Rx path in the Half Duplex modes
o A logic low disables the Tx digital clock and the I/O port will be outputs
o A logic high disables the Rx digital clocks and the I/O port will be a high impedance input
Preliminary Technical Data AD9863
AD9863 Rev. PrA | Page 21 of 28
AD9863 CLOCK DISTRIBUTION BLOCK
The AD9863 utilizes a PLL clock multiplier circuit and an internal distribution block to generate all required clocks for various timing
configurations. The AD9863 has 2 independent input clocks, CLKIN1 and CLKIN2. The CLKIN1 is primarily used to drive the Rx ADCs.
The CLKIN2 is primarily used to drive the TxDACs and Tx digital processing blocks. There are 2 options to generate the needed clocks for the
AD9863, the “Normal Timing Operation” Mode and the “Alternative Timing Operation” Mode. A block diagram of the Clock Tree and the Data
Path are shown in the figures below. Many of the options require SPI programmability. Some features of the AD9863 Clock Tree:
- The PLL has 2 controllable variables to configure a multiplication factor. One setting controls a divide by 1 or 5, and the
other controls a multiply by 1, 2, 4, 8 or 16.
- The Rx path has an independent divide by 1, 2 or 4 control for flexibility purposes.
- In the alternative timing mode, the PLL can be used to drive the Rx ADCs (expecting lower performance due to clock jitter).
CLKIN1
CLKIN2
RxADC1
RxADC2
TxDAC1
TxDAC2
1,5
~
1,2,4,8,16
Tx
Digital
Block
Tx Path Clock
1,2,4
Rx
Digital
Block
Rx Path Clock
80MHz Max
80MHz Max
PLL: 1, 2, 4, 8, 16 x
0.2, 0.4, 0.8, 1.6, 3.2 x 200MHz Max
Figure ##. Clock Distribution Block Diagram
L12
U12
RxADC1
RxADC2
TxDAC1
TxDAC2
Tx
Digital
1x, 2x, 4x
200MHz Max
80MHz Max
160
M
H
z
M
a
x
160MHz Max
Figure ##. Data Path Block Diagram
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 22 of 28
SPI REGISTER MAP
The Registers for the AD9861/AD9863 are used to control a number of features to provide flexible operation of the device. The
SPI allows access to many configurable options and information, including:
- SPI Setup: 3 wire mode, LSB First Mode, Soft Reset
- Rx Path Setup: Power Down of various Rx path blocks/channels, 2’s Complement, Clock Duty Stabilizer
- Tx Path Setup: Power Down of various Tx path blocks/channels, Tx Offset Control, Fine Gain Control, Coarse Gain
Control, PGA Control, Gain update slaved to Tx power down, Q/I order, 2’s Compl, Inverse Sample
- Clock setup: PLL multiply factor, Rx CLKOUT divide factor, Tx CLKOUT divide factor, Invert Rx CLKOUT, Inv Tx
CLKOUT, single clock input mode, Input clock control? (crystal or source),
A Register map consist of register from 0x00 to 0x29 and can be seen below:
Register
Name
Default
Setting
[Hex]
Reg
Add
7 6 5 4 3 2 1 0
General 00 0 SDIO BiDir LSB first Soft reset
Clock Mode 00 1 clk_mode[2:0] Inv clkout
(IFACE3)
Power Down 00 2 Tx Analog TxDigital RxDigital PLL Power
Down
PLL Output
Disable
RxA Power
Down 00 3 Rx_A Analog Rx_A
DC Bias
RxB Power
Down 00 4 Rx_B Analog Rx_B
DC Bias
Rx Power
Down 00 5 Rx Analog Bias VREF1 VREF, DIFF VREF2
C0 6 Rx_A Twos
Compliment
Rx_A Clk
Duty
C0 7 Rx_B Twos
Compliment
Rx_B Clk
Duty
00 0B DAC A Offset [9:2]
00 0C DAC A Offset [1:0] DAC A
Offset
Direction
C0 0D DAC A Coarse Gain Control DAC A Fine Gain [5:0]
00 0E DAC B Offset [9:2]
00 0F DAC B Offset [1:0] DAC B
Offset
Direction
C0 10 DAC B Coarse Gain Control DAC B Fine Gain [5:0]
FF 11 TxPGA Gain [7:0]
Tx Misc 00 12 TxPGA Slave
Enable
TxPGA Fast
Update
00 13 Tx Twos
Compliment
Rx Twos
Compliment
Tx Inverse
Sample
Rx Data
Interleaved
Tx Data
Interleaved
Interpolation Control [1:0]
10 14 Dig Loop On SpiFDnHD SpiTxnRx SpiB12n24 SPI IO
Control
SpiClone
00 15 PLL Bypass ADC Clock Div[1:0] Alt Timing
Mode
PLL Div5 PLL Multiplier [2:0]
00 16 PLL Lock Bypass PLL Lock
Force
PLL User
Detect
PLL Slow
17-29
Preliminary Technical Data AD9863
AD9863 Rev. PrA | Page 23 of 28
REGISTER BIT DEFINITIONS
REGISTER 0: GENERAL
BIT 7: SDIO BiDir (Bidirectional)
Default setting is low, which indicates SPI serial port uses dedicated input and output lines (i.e., 4-wire interface), SDIO and
SDO Pins, respectively. Setting this bit high configures the serial port to use the SDIO Pin as a bidirectional data pin.
BIT 6: LSB First
Default setting is low, which indicates MSB first SPI Port Access Mode. Setting this bit high configures the SPI port access to
LSB first mode.
BIT 5: Soft Reset
Writing a high to this register resets all the registers to their default values and forces the PLL to relock to the input clock. The
Soft Reset Bit is a one shot register and is cleared immediately after the register write is completed.
REGISTER 1: ???
BIT 7-5: Clk Mode
These bits represent the clocking interface for the various modes. Setting 000 is default. Setting 111 is used for Clone mode (see
Flex IO section for definition of Clone Mode).
Modes
000 Standard FD, HD12, HD24
Clock modes
001 Optional FD timing
010 Not Used
011 Optional HD12 timing
100 Not Used
101 Optional HD24 timing
110 Not Used
111 Clone Mode
Bit 1: Inv clkout (IFACE3)
Invert the output clock on IFACE3
REGISTER 2: ???
BIT 7-5: Tx Analog (Power-Down)
Three options are available to reduce analog power consumption for the Tx channels. The first two options disable the analog
output from Tx channel A or B independently, and the third option disables the output of both channels and reduces the power
consumption of some of the additional analog support circuitry for maximum power savings. With all three options, the DAC bias
current is not powered d own so recovery times are fast (typically a few clock cycles). The list below explains the different modes
and settings used to configure them.
Power-Down Option Bits Setting [7:5]
Power-Down Tx A Channel Analog Output [1 0 0]
Power-Down Tx B Channel Analog Output [0 1 0]
Power-Down Tx A and Tx B Analog Outputs [1 1 1]
BIT 4: Tx Digital (Power-Down)
By default this bit is low, enabling the transmit path digital to operate as programmed through other registers. By setting this bit
high, the digital blocks are not clocked to reduce power consumption. When enabled, the Tx outputs will be static, holding their
last update values.
BIT 3: Rx Digital (Power-Down)
Setting this bit high will power down the digital section of the receive path of the chip. Typically, any unused digital blocks are
automatically powered down.
BIT 2: PLL Power-Down
Setting this register bit high forces the CLKIN multiplier to a power-down state. This mode can be used to conserve power or to
bypass the internal DLL. To operate the AD9863 when the PLL is bypassed, an external clock equal to the fastest on-chip clock is
supplied to the CLKIN2 pin.
BIT 1: PLL Output Disable
Setting this register bit high disconnects the PLL output from the clock path. If the PLL is enabled it will lock or stay locked as
normal.
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 24 of 28
REGISTER 3/4: ???
BIT 7/7: Rx_A Analog/Rx_B Analog (Power-Down)
Either ADC or both ADCs can be powered down by setting the appropriate register bit high. The entire Rx channel is powered
down, including the differential references, input buffer, and the internal digital block. The bandgap reference remains active for
quick recovery.
BIT 6/6: Rx_A DC Bias/Rx_B DC Bias (Power-Down)
Setting either of these bits high will power down the dc bias network for the respective channel and requires an input signal to be
properly dc biased. By default, these bits are low and the Rx inputs are self biased and accept an AC coupled input.
REGISTER 5: ???
BIT 7: Rx Analog Bias (Power-Down)
Setting this bit high powers down all analog bias circuits related to the receive path (including the differential reference buffer).
Since bias circuits are powered down, an additional power saving, but also a longer recovery time relative to other Rx power
down options will result.
BIT 6: VREF1 (Power-Down)
Setting this register bit high, along with VREF2 bit, will power down the ADC reference circuit (i.e., VREF). Powering down the
Rx Bandgap reference will allow an external reference to drive the Vref pin setting full scale range of the Rx paths.
BIT 5: VREF, DIFF(Power-Down)
Setting this bit high will power down the ADC’s differential references (i.e., REFT and REFB). Recovery time will depend on
REFT and REFB decoupling caps size and amount of
BIT 4: VREF2 (Power-Down)
Setting this register bit high, along with VREF1 bit, will power down the ADC reference circuit (i.e., VREF). Powering down the
Rx Bandgap reference will allow an external reference to drive the Vref pin setting full scale range of the Rx paths.
REGISTER 6/7: ???
BIT 5: Rx_A Twos Complement/ Rx_B Twos Complement
Default data format for the Rx data is straight binary. Setting this bit high will generate two’s complement data.
BIT 4: Rx_A Clk Duty/ Rx_B Clk Duty
Setting either of these bits high enables the respective channels on-chip duty cycle stabilizer (DCS) circuit to generate the internal
clock for the Rx block. This option is useful for adjusting for high speed input clocks with skewed duty cycle. The DCS Mode can
be used with ADC sampling frequencies over 40 MHz.
REGISTER 0B/0C/0E/0F: DAC OFFSET A/B
DAC A/DAC B Offset
These 10-bit, twos complement registers control a dc current offset that is combined with the Tx A or Tx B output signal. An
offset current of up to ±12% IOUTFS (2.4 mA for a 20 mA fullscale output) can be applied to either differential pin on each
channel. The offset current can be used to compensate for offsets that are present in an external mixer stage, reducing LO leakage
at its output. Default setting is hex00, no offset current. The offset current magnitude is set using the lower nine bits. Setting the
MSB high will add the offset current to the selected differential pin, while an MSB low setting will subtract the offset value.
DAC A/DAC B Offset Direction
This bit determines to which of the differential output pins for the selected channel the offset current will be applied. Setting this
bit low will apply the offset to the negative differential pin. Setting this bit high will apply the offset to the positive differential
pin.
REGISTER 0D/10: ????
BIT 7, 6: DAC A/DAC B Coarse Gain Control
These register bits will scale the full-scale output current (IOUTFS) of either Tx channel independently. IOUT of the Tx channels
is a function of the RSET resistor, the TxPGA setting, and the Coarse Gain Control setting.
BIT 5–0: DAC A/DAC B Fine Gain
The DAC output curve can be adjusted fractionally through the Gain Trim Control. Gain trim of up to ±4% can be achieved on
00 Output current scaling by 1/11
01 Output current scaling by ½
10 No output current scaling
11 No output current scaling
Preliminary Technical Data AD9863
AD9863 Rev. PrA | Page 25 of 28
each channel individually. The Gain Trim register bits are a twos complement attention control word.
MSB, LSB
100000 Maximum positive gain adjustment
111111 Minimum positive gain adjustment
000000 No adjustment (default)
000001 Minimum negative gain adjustment
011111 Maximum negative gain adjustment
REGISTER 11: TxPGA GAIN
BIT 0–7: TxPGA Gain
This 8 bit, straight binary (Bit 0 is the LSB, Bit 7 is the MSB) register controls for the Tx programmable gain amplifier (TxPGA).
The TxPGA provides a 20 dB continuous gain range with 0.1 dB steps (linear in dB) simultaneously to both Tx channels. By
default, this register setting is hex00.
MSB, LSB
000000 Minimum gain scaling –20 dB
111111 Maximum gain scaling 0 dB
REGISTER 12: Tx MISC
BIT 6: TxPGA Slave Enable
The TxPGA Gain is controlled through register TxPGA Gain setting and by default is updated immediately after the register write.
If this bit is set, the TxPGA Gain update is synchronized with the falling edge of a signal applied to the TxPwrDwn pin and is
enabled during the wakeup from Power Down.
BIT 4: TxPGA Fast Update (Mode)
The TxPGA Fast bit controls the update speed of the TxPGA. When Fast Update mode is enabled, the TxPGA provides fast gain
settling within a few clock cycles (which may introduce spurious signals at the output of the Tx Path). Default setting for this bit
is low and the TxPGA gives a smooth transition between gain settings. Fast mode is enabled when this bit is set high.
REGISTER 13: ????
BIT 7: Tx Twos Complement
The default data format for Tx data is straight binary. Set this bit high when providing twos complement Tx data.
BIT 6: Rx Twos Complement
The default data format for Rx data is straight binary. Set this bit high when providing twos complement Rx data.
BIT 5: Tx Inverse Sample
By default, the transmit data is sampled on the rising edge of the CLKOUT. Setting this bit high will change this, and the transmit
data will be sampled on the falling edge.
BIT 4: Rx Data Interleaved
This bit can be used to configure the Rx data port to output interleaved data, overriding the I/O configuration setup through the
Mode pins.
BIT 3: Tx Data Interleaved
This bit can be used to configure the Tx data port to accept interleaved data, overriding the I/O configuration setup through the
Mode pins.
BIT 1,0: Interpolation Control
These register bits control the interpolation rate of the transmit path. Default settings are both bits low, indicating that both
interpolation filters are bypassed. The MSB and LSB are address Bits 1 and 0, respectively. Setting binary 01 provides an
interpolation rate of 2x; binary 10 provides an interpolation rate of 4x.
REGISTER 14: ????
BIT 5: Dig Loop On
When enabled this bit enables a digital loop back mode. The digital loop back mode provides a means of testing digital interfaces
and functionality at the system level. In digital loop back mode, the full duplex interface must be enabled (see Flexible I/O
section). The device will accept digital input bus according to the FD mode timing and exercise the Tx digital path (with enabled
interpolation and other digital settings); the processed data will then be output from the Rx path bus.
BIT 4: SPI_FDnHD
Control bit to configure full duplex (high) or half duplex (low) interface mode. This register setting requires a SPI IO Control
register to be enabled.
BIT 3: SpiTxnRx
Control bit for transmit or receive mode. HIGH represents TX and LOW represents RX
Bit 2: SpiB12n24
Control bir for 12 or 24 bit mode. HIGH represents 12 bit and LOW represents 24 bit
Bit 1: SPI IO Control
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 26 of 28
Use this bit in conjunction with SpiTxnRx to overide external TxnRx pin operation.
Bit 0: SpiClone
Set HIGH when in clone mode (see Flexible IO section for definition of Clone mode). Clk_mode should also be set to binary 111
(ie: Reg01[7:5] = 111)
REGISTER 15: ???
BIT 7: PLL_Bypass
Setting this bit high will bypass the PLL. When bypassed, the PLL will remain active.
BIT 6,5: ADC Clock Div [1:0]
For the AD9863, by default the ADCs are driven directly from CLKIN1 in Normal Timing Operation or from the PLL output
clock in the Alternative Timing Operation. These bits are used to divide the source of the ADC clock prior to the ADCs. A [00]
setting performs no division, the [01] setting divides the clock by 2, the [10] setting divides the clock by 4 and the [11] setting is
not used.
BIT 4: Alt Timing Mode
The timing section in the data sheet describes two timing modes, the “Normal Timing Operation” and the “Alternative Timing
Operation” modes. The default configuration is Normal timing mode and for the AD9863, the CLKIN1 drives the Rx path. In the
Alternative Timing Mode the PLL output is used to drive the Rx path. The Alternative Operation mode is configured by setting
this bit high.
BIT 3: PLL Div5
The output of the PLL can be divided by 5 by setting this bit high. By default, the PLL directly drives the Tx Digital path with no
division of its output.
BIT 2-0: PLL Multiplier
These bits control the PLL multiplication factor. A default setting is binary 000 which will configure the PLL to 1x multiplication
factor. This register, in combination with the PLL Div10 register, sets the PLL output frequency. The programmable
multiplication factors are:
000 > 1 x
001 > 2 x
010 > 4 x
011 > 8x
100 > 16 x
101 > 32 x
110 and 111 >> not used
REGISTER 16: ???
BIT 7: PLL Lock Bypass
In the Alternative Timing mode, a PLL lock detect signal is used to gate an output clock (IFACE2 pin). Setting this bit high will
force the PLL lock detect signal high after the 32 input clock cycles. This is required when configuring the PLL near its min or
maximum frequency when PLL Lock detect signal may become intermittent.
BIT 6: PLL Lock Force
In the Alternative Timing mode, a PLL lock detect signal is used to gate an output clock (IFACE2 pin). Setting this bit high will
force the PLL lock detect signal high with no delay. This may be required when configuring the PLL near its min or maximum
frequency when PLL Lock detect signal may become intermittent.
BIT 5: PLL User Detect
Flipping this bit HIGH will manually tell the PLL to switch between fast and slow clocks in IPW mode. Only valid if Register
16, bit 6 is HIGH.
BIT 2: PLL Slow
For low input clocks (< 32 MHz) to the PLL (CLKIN2 for the AD9863 or CLKIN for the AD9861), this bit will decrease the
bandwidth helping the PLL remain locked.
AD9863 PIN CONFIGURATION
Pin # Pin Name Description
1 SPI_DIO (Interp1) Serial Port Data Input (OR if no SPI: Tx Interpolation bit MSB)
2 SPI_CLK (Interp0) Serial Port Shift Clock (OR if no SPI: Tx Interpolation bit LSB)
3 SPI_SDO (FD/nHD) 4 wire Serial Port Output (OR if no SPI Full or Half Duplex Config)
4 ADC_LO_PWR ADC Low Power Mode enable defined at power up
5, 31 DVDD, DRVDD Digital Supply
6, 32 DVSS, DRVSS Digital Ground
7, 16, 50,
51, 61 AVDD Analog Supply
8 IOUT-A DAC A output
9 IOUT+A DAC A output
10, 13,
49, 53, 59 AGND Analog Ground
11 REFIO TxDAC bandgap reference decoupling pin
12 FSADJ Tx DAC Full scale adjust pin
14 IOUT+B DAC B output
15 IOUT-B DAC B output
SPI : Buffered CLKIN1 (can be configured to be system clock output)
17 IFACE2 No SPI : FD >> Buffered CLKIN1; HD24 or HD12 >> 12/n24 Configuration
18 IFACE3 Clock Output
19 - 30 U11 – U0 UPPER DATA BIT 11 [MSB] - UPPER DATA BIT 0 [LSB]
SPI : FD >> TxSYNC; HD24 >> Tx/nRx; HD12 >> Tx/nRx; Clone >> Tx/nRx
33 IFACE1 No SPI : FD >> TxSYNC; HD24 >> Tx/nRx; HD12 >> Tx/nRx
34 - 45 L11 – L0 LOWER DATA BIT 11 [MSB] – LOWER DATA DIT 0 [LSB]
46 RESETb Chip reset when low
47 CLKIN2 Tx Path Clock input
48 CLKIN1 Rx Path Clock input
52 REFB ADC bottom reference
54 VIN+B ADC B input
55 VIN-B ADC B input
56 VREF ADC band gap reference
57 VIN-A ADC A input
58 VIN+A ADC A input
60 REFT ADC top reference
62 RxPwrDwn Rx analog power down control
63 TxPwrDwn Tx analog power down control
64 SPI_CS (SPI Enable)
Serial Port Chip Select (At Power Up: Tie high to enable SPI OR tie low to disable
SPI and use Mode pins)
AD9863 Preliminary Technical Data
AD9863 Rev. PrA | Page 28 of 28
TIMING DIAGRAM
Figure 1: Timing Diagrams
Outline Dimensions
Figure 2:
Figure 3:
© 2002 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A. C02959-0-11/02(0)
