FS6377-01 Programmable 3-PLL Clock Generator IC 1.0 Features 2.0 Three on-chip PLLs with programmable Reference and Feedback Dividers * Four independently programmable muxes and post dividers * I Ca-bus serial interface * Programmable power-down of all PLLs and output clock drivers * One PLL and two mux/post-divider combinations can be modified by SEL_CD input * Tristate outputs for board testing * 5V to 3.3V operation * Accepts 5MHz to 27MHz crystal resonators * Commercial (FS6377-01) and industrial (FS6377-01i) temperature ranges 2 The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of elec2 tronic systems. Three I C-programmable phase-locked loops feeding four programmable muxes and post dividers provide a high degree of flexibility. Figure 1: Pin Configuration SDA 1 16 SCL SEL_CD 2 15 CLK_A 14 VDD 13 CLK_B PD 3 VSS 4 FS6377 * Description XIN 5 12 CLK_C XOUT 6 11 VSS OE 7 10 CLK_D VDD 8 9 ADDR 16-pin (0.150") SOIC Figure 2: Block Diagram XIN XOUT PD Reference Oscillator Mux A Post Divider A CLK_A Mux B Post Divider B CLK_B Mux C Post Divider C CLK_C Mux D Post Divider D CLK_D PLL A Power Down Control PLL B SCL SDA ADDR I2C-bus Interface PLL C SEL_CD OE FS6377 I2C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc., reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 6.5.03 FS6377-01 Programmable 3-PLL Clock Generator IC Table 1: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin 3.0 PIN TYPE 1 U NAME DI O SDA 2 DIU SEL_CD 3 DIU PD Power-Down Input 4 P VSS Ground Crystal Oscillator Input 5 AI XIN 6 AO XOUT 7 DIU OE DESCRIPTION Serial Interface Data Input/Output Selects one of two PLL C, Mux C/D, and Post Divider C/D combinations Crystal Oscillator Output Output Enable Input 8 P VDD 9 DIU ADDR Power Supply (5V to 3.3V) 10 DO CLK_D 11 P VSS 12 DO CLK_C C Clock Output 13 DO CLK_B B Clock Output 14 P VDD 15 DO CLK_A 16 DIU SCL Address Select D Clock Output Ground Power Supply (5V to 3.3V) A Clock Output Serial Interface Clock Input Figure 3: PLL Diagram Functional Block Description LFTC 3.1 Phase Locked Loops Loop Filter REFDIV[7:0] Each of the three on-chip phase-locked loops (PLLs) is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired frequency by a ratio of integers. This frequency multiplication is exact. As shown in Figure 3, each PLL consists of a Reference Divider, a Phase-Frequency Detector (PFD), a charge pump, an internal loop filter, a Voltage-Controlled Oscillator (VCO), and a Feedback Divider. During operation, the reference frequency (fREF), generated by the on-board crystal oscillator, is first reduced by the Reference Divider. The divider value is called the "modulus," and is denoted as NR for the Reference Divider. The divided reference is then fed into the PFD. The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a high-speed, low noise, continuously variable frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the Feedback Divider (the modulus is denoted by NF) to close the loop. CP fREF Reference Divider PhaseFrequency Detector (NR) fPD UP Charge Pump DOWN Voltage Controlled Oscillator fVCO FBKDIV[10:0] Feedback Divider (NF) The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is aeN f VCO = f REF cc F e NR o // . o 6.5.03 2 FS6377-01 Programmable 3-PLL Clock Generator IC To understand the operation, refer to Figure 4. The Mcounter (with a modulus always equal to M) is cascaded with the dual-modulus prescaler. The A-counter controls the modulus of the prescaler. If the value programmed into the A-counter is A, the prescaler will be set to divide by N+1 for A prescaler outputs. Thereafter, the prescaler divides by N until the M-counter output resets the Acounter, and the cycle begins again. Note that N=8, and A and M are binary numbers. Suppose that the A-counter is programmed to zero. The modulus of the prescaler will always be fixed at N; and the entire modulus of the feedback divider becomes MxN. Next, suppose that the A-counter is programmed to a one. This causes the prescaler to switch to a divide-byN+1 for its first divide cycle and then revert to a divide-byN. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycle of the Feedback Divider. The overall modulus is now seen to be equal to MxN+1. This example can be extended to show that the Feedback Divider Modulus is equal to MxN+A, where AM. 3.1.1 Reference Divider The Reference Divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-down frequency to the PFD. The Reference Divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h. 3.1.2 Feedback Divider The Feedback Divider is based on a dual-modulus prescaler technique. The technique allows the same granularity as a fully programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also called a prescaler) is placed between the VCO and the programmable Feedback Divider because of the high speeds at which the VCO can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall power consumption of the divider. For example, a fixed divide-by-eight could be used in the Feedback Divider. Unfortunately, a divide-by-eight would limit the effective modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to achieve a desired input-frequency-tooutput-frequency ratio without making both the Reference and Feedback Divider values comparatively large. A large feedback modulus means that the divided VCO frequency is relatively low, requiring a wide loop bandwidth to permit the low frequencies. A narrow loop bandwidth tuned to high frequencies is essential to minimizing jitter; therefore, divider moduli should always be as small as possible. 3.1.3 Feedback Divider Programming For proper operation of the Feedback Divider, the Acounter must be programmed only for values that are less than or equal to the M-counter. Therefore, not all divider moduli below 56 are available for use. The selection of divider values is listed in Table 2. Above a modulus of 56, the Feedback Divider can be programmed to any value up to 2047. Table 2: Feedback Divider Modulus Under 56 M-COUNTER: FBKDIV[10:3] Figure 4: Feedback Divider fVCO Dual Modulus Prescaler M Counter FBKDIV[2:0] FBKDIV[10:3] fPD A Counter A-COUNTER: FBKDIV[2:0] 000 001 010 011 100 101 110 111 00000001 8 9 - - - - - - 00000010 16 17 18 - - - - - 00000011 24 25 26 27 - - - - 00000100 32 33 34 35 36 - - - 00000101 40 41 42 43 44 45 - - 00000110 48 49 50 51 52 53 54 - 00000111 56 57 58 59 60 61 62 63 FEEDBACK DIVIDER MODULUS 6.5.03 3 FS6377-01 Programmable 3-PLL Clock Generator IC 3.2 Post Divider Muxes 4.1 As shown in Figure 2, an input mux in front of each Post Divider stage can select from any one of the PLL frequencies or the reference frequency. The frequency se2 lection is done via the I C-bus. The input frequency on two of the four muxes (Mux C and D in Figure 2) can be changed without reprogramming by a logic-level input on the SEL_CD pin. 3.3 The SEL_CD pin provides a way to alter the operation of PLL C, Muxes C and D, and Post Dividers C and D without having to reprogram the device. A logic-low on the SEL_CD pin selects the control bits with a "C1" or "D1" notation, per Table 3. A logic-high on the SEL_CD pin selects the control bits with "C2" or "D2" notation, per Table 3. Note that changing between two running frequencies using the SEL_CD pin may produce glitches in the output, especially if the post-divider(s) is/are altered. Post Dividers The Post Divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to aeN f CLK = f REF cc F e NR oae 1 //cc oe N P 4.2 Power-Down and Output Enable A logic-high on the PD pin powers down only those portions of the FS6377 which have their respective powerdown control bits enabled. Note that the PD pin has an internal pull-up. When a Post Divider is powered down, the associated output driver is forced low. When all PLLs and Post Dividers are powered down the crystal oscillator is also powered down. The XIN pin is forced low, and the XOUT pin is pulled high. A logic-low on the OE pin tristates all output clocks. Note that this pin has an internal pull-up. o // o where NF, NR, and NP are the Feedback, Reference, and Post Divider moduli respectively, and fCLK and fREF are the output and reference oscillator frequencies. The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly. The modulus on two of the four Post Dividers muxes (Post Dividers C and D in Figure 2) can be altered without reprogramming by a logic level on the SEL_CD pin. 4.0 SEL_CD Input 4.3 Oscillator Overdrive For applications where an external reference clock is provided (and the crystal oscillator is not required), the reference clock should be connected to XOUT and XIN should be left unconnected (float). For best results, make sure the reference clock signal is as jitter-free as possible, can drive a 40pF load with fast rise and fall times, and can swing rail-to-rail. If the reference clock is not a rail-to-rail signal, the reference must be AC coupled to XOUT through a 0.01F or 0.1F capacitor. A minimum 1V peak-to-peak signal is required to drive the internal differential oscillator buffer. Device Operation The FS6377 powers up with all internal registers cleared to zero, delivering the crystal frequency to all outputs. For operation to occur, the registers must be loaded in a most-significant-bit (MSB) to least-significant-bit (LSB) order. The register mapping of the FS6377 is shown in 2 Table 3, and I C-bus programming information is detailed in Section 5.0. Control of the Reference, Feedback, and Post Dividers is detailed in Table 6. Selection of these dividers directly controls how fast the VCO will run. The maximum VCO speed is noted in Table 15. 6.5.03 4 FS6377-01 Programmable 3-PLL Clock Generator IC 5.0 Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first sixteen bytes will overflow into the first register, then the second, and so on, in a first-in, firstoverwritten fashion. 2 I C-bus Control Interface This device is a read/write slave device 2 meeting all Philips I C-bus specifications except a "general call." The bus has to be controlled by a master device that generates the serial clock SCL, controls bus access, and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. 2 I C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS). 5.1 5.1.5 Acknowledge When addressed, the receiving device is required to generate an Acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the Acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. The master must signal an end of data to the slave by not generating and acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition. Bus Conditions Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition. The following bus conditions are defined 2 by the I C-bus protocol. 5.2 I2C-bus Operation All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital inter2 face. The device accepts the following I C-bus commands. 5.1.1 Not Busy Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy. 5.2.1 Slave Address After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the device is: 5.1.2 START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition. 5.1.3 STOP Data Transfer A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition. A6 A5 A4 A3 A2 A1 A0 1 0 1 1 X 0 0 where X is controlled by the logic level at the ADDR pin. The variable ADDR bit allows two different devices to 2 exist on the same bus. Note that every device on an I Cbus must have a unique address to avoid bus conflicts. The default address sets A2 to one via the pull-up on the ADDR pin. 5.1.4 Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit. 6.5.03 5 FS6377-01 Programmable 3-PLL Clock Generator IC To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to sixteen bytes of data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur. Registers are therefore updated at different times during a Sequential Register Write. 5.2.2 Random Register Write Procedure Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. If either a STOP or a repeated START condition occurs during a Register Write, the data that has been transferred is ignored. 5.2.5 Sequential Register Read Procedure Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure is more efficient than the Random Register Read if several registers must be read. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the Register Write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all sixteen bytes of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition. 5.2.3 Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the Register Write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not acknowledge the transfer but does generate a STOP condition. 5.2.4 Sequential Register Write Procedure Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the Random Register Write if several registers must be written. 6.5.03 6 FS6377-01 Programmable 3-PLL Clock Generator IC Figure 5: Random Register Write Procedure S DEVICE ADDRESS W A 7-bit Receive Device Address REGISTER ADDRESS A Register Address A P Data Acknowledge START Command DATA Acknowledge STOP Condition WRITE Command From bus host to device Acknowledge From device to bus host Figure 6: Random Register Read Procedure S DEVICE ADDRESS W A 7-bit Receive Device Address REGISTER ADDRESS A S DATA A P Data Acknowledge Repeat START WRITE Command From bus host to device R A 7-bit Receive Device Address Register Address Acknowledge START Command DEVICE ADDRESS Acknowledge STOP Condition READ Command NO Acknowledge From device to bus host Figure 7: Sequential Register Write Procedure S DEVICE ADDRESS W A 7-bit Receive Device Address REGISTER ADDRESS DATA Register Address Acknowledge START Command A A DATA DATA Data Data Acknowledge A Acknowledge Data Acknowledge WRITE Command From bus host to device A P Acknowledge STOP Command From device to bus host Figure 8: Sequential Register Read Procedure S DEVICE ADDRESS 7-bit Receive Device Address W A REGISTER ADDRESS Register Address Acknowledge START Command WRITE Command From bus host to device A S DEVICE ADDRESS R A 7-bit Receive Device Address A DATA Data Acknowledge Repeat START Acknowledge DATA READ Command A P Data Acknowledge NO Acknowledge STOP Command From device to bus host 6.5.03 7 FS6377-01 Programmable 3-PLL Clock Generator IC 6.0 Programming Information Table 3: Register Map (Note: All Register Bits are cleared to zero on power-up.) ADDRESS BYTE 15 BIT 7 BIT 6 MUX_D2[1:0] (selected via SEL_CD = 1) BIT 5 BIT 4 MUX_C2[1:0] (selected via SEL_CD = 1) BIT 3 BIT 2 BIT 1 BIT 0 PDPOST_D PDPOST_C PDPOST_B PDPOST_A BYTE 14 POST_D2[3:0] (selected via SEL_CD = 1) POST_C2[3:0] (selected via SEL_CD = 1) BYTE 13 POST_D1[3:0] (selected via SEL_CD = 0) POST_C1[3:0] (selected via SEL_CD = 0) BYTE 12 POST_B[3:0] POST_A[3:0] BYTE 11 MUX_D1[1:0] (selected via SEL_CD = 0) Reserved (0) MUX_C1[1:0] (selected via SEL_CD = 0) PDPLL_C LFTC_C1 (SEL_CD=0) MUX_B[1:0] FBKDIV_C1[10:8] M-Counter (selected via SEL_CD = 0) FBKDIV_C1[2:0] A-Counter (selected via SEL_CD = 1) PDPLL_B LFTC_B CP_B FBKDIV_B[10:8] M-Counter FBKDIV_B[7:3] M-Counter BYTE 4 FBKDIV_B[2:0] A-Counter REFDIV_B[7:0] BYTE 3 MUX_A[1:0] PDPLL_A LFTC_A CP_A FBKDIV_A[10:8] M-Counter FBKDIV_A[7:3] M-Counter FBKDIV_A[2:0] A-Counter REFDIV_A[7:0] BYTE 0 6.1 CP_C1 (SEL_CD=0) REFDIV_C1[7:0] (selected via SEL_CD = 0) BYTE 6 BYTE 1 FBKDIV_C2[2:0] A-Counter (selected via SEL_CD pin = 1) FBKDIV_C1[7:3] M-Counter (selected via SEL_CD = 0) BYTE 7 BYTE 2 FBKDIV_C2[10:8] M-Counter (selected via SEL_CD pin = 1) REFDIV_C2[7:0] (selected via SEL_CD pin = 1) BYTE 9 BYTE 5 CP_C2 (SEL_CD=1) FBKDIV_C2[7:3] M-Counter (selected via SEL_CD pin = 1) BYTE 10 BYTE 8 LFTC_C2 (SEL_CD=1) Control Bit Assignment Table 4: Power-Down Bits If any PLL control bit is altered during device operation, including those bits controlling the Reference and Feedback Dividers, the output frequency will slew smoothly (in a glitch-free manner) to the new frequency. The slew rate is related to the programmed loop filter time constant. However, any programming changes to any Mux or Post Divider control bits will cause a glitch on an operating clock output. NAME DESCRIPTION Power-Down PLL A PDPLL_A (Bit 21) Bit = 0 Power On Bit = 1 Power Off Power-Down PLL B PDPLL_B (Bit 45) Bit = 0 Power On Bit = 1 Power Off Power-Down PLL C 6.1.1 Power Down All power-down functions are controlled by enable bits. The bits select which portions of the device to powerdown when the PD input is asserted. PDPLL_C (Bit 69) Reserved (0) (Bit 69) Bit = 0 Power On Bit = 1 Power Off Set these reserved bits to zero (0) 6.5.03 8 FS6377-01 Programmable 3-PLL Clock Generator IC Table 5: Power-Down Bits, continued NAME Table 7: Divider Control Bits DESCRIPTION NAME Power-Down POST divider A PDPOSTA (Bit 120) Bit = 0 Power On Bit = 1 Power Off Power-Down POST divider B PDPOSTB (Bit 121) Bit = 0 Power On Bit = 1 Power Off Power-Down POST divider C PDPOSTC (Bit 122) Bit = 0 Power On Bit = 1 Power Off Power-Down POST divider D PDPOSTD (Bit 123) Bit = 0 Power On Bit = 1 Power Off DESCRIPTION POST_A[3:0] (Bits 99-96) POST divider A (see Table 8) POST_B[3:0] (Bits 103-100) POST divider B (see Table 8) POST_C1[3:0] (Bits 107-104) POST divider C1 (see Table 8) selected when the SEL_CD pin = 0 POST_C2[3:0] (Bits 115-112) POST divider C2 (see Table 8) selected when the SEL_CD pin = 1 POST_D1[3:0] (Bits 111-108) POST divider D1 (see Table 8) selected when the SEL_CD pin = 0 POST_D2[3:0] (Bits 119-116) POST divider D2 (see Table 8) selected when the SEL_CD pin = 1 Table 8: Post Divider Modulus Table 6: Divider Control Bits NAME DESCRIPTION REFDIV_A[7:0] (Bits 7-0) REFerence DIVider A (NR) REFDIV_B[7:0] (Bits 31-24) REFerence DIVider B (NR) REFDIV_C1[7:0] (Bits 55-48) REFerence DIVider C1 (NR) selected when the SEL_CD pin = 0 REFDIV_C2[7:0] (Bits 79-72) REFerence DIVider C2 (NR) selected when the SEL_CD pin = 1 FeedBacK DIVider A (NF) FBKDIV_A[10:0] (Bits 18-8) FBKDIV_B[10:0] (Bits 42-32) FBKDIV_C1[10:0] (Bits 66-56) FBKDIV_C2[10:0] (Bits 90-80) FBKDIV_A[2:0] A-Counter Value FBKDIV_A[10:3] M-Counter Value BIT [3] BIT [2] BIT [1] BIT [0] DIVIDE BY 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 8 0 1 1 1 9 1 0 0 0 10 1 0 0 1 12 1 0 1 0 15 1 0 1 1 16 FeedBacK DIVider B (NF) 1 1 0 0 18 FBKDIV_B[2:0] A-Counter Value 1 1 0 1 20 FBKDIV_B[10:3] M-Counter Value 1 1 1 0 25 1 1 1 1 50 FeedBacK DIVider C1 (NF) selected when the SEL_CD pin = 0 FBKDIV_C1[2:0] A-Counter Value FBKDIV_C1[10:3] M-Counter Value FeedBacK DIVider C2 (NF) selected when the SEL_CD pin = 1 FBKDIV_C2[2:0] A-Counter Value FBKDIV_C2[10:3] M-Counter Value 6.5.03 9 FS6377-01 Programmable 3-PLL Clock Generator IC Table 9: PLL Tuning Bits NAME LFTC_A (Bit 20) Table 10: Mux Select Bits DESCRIPTION NAME Loop Filter Time Constant A MUX A frequency select Bit = 0 Bit 23 Bit 22 0 0 Reference Frequency 0 1 PLL A Frequency 1 0 PLL B Frequency 1 1 PLL C Frequency Bit = 1 Short Time Constant: 7s MUX_A[1:0] (Bits 23-22) Long Time Constant: 20s Loop Filter Time Constant B LFTC_B (Bit 44) LFTC_C1 (Bit 68) Bit = 0 Short Time Constant: 7s Bit = 1 Long Time Constant: 20s MUX B frequency select Loop Filter Time Constant C1 selected when the SEL_CD pin = 0 Bit = 0 Bit = 1 LFTC_C2 (Bit 92) MUX_B[1:0] (Bits 47-46) Short Time Constant: 7s Long Time Constant: 20s Loop Filter Time Constant C2 selected when the SEL_CD pin = 1 Bit = 0 Short Time Constant: 7s Bit = 1 Long Time Constant: 20s Bit = 0 Bit = 1 MUX_C1[1:0] (Bits 71-70) Bit = 0 Bit = 1 CP_C1 (Bit 67) Bit = 1 CP_C2 (Bit 91) 0 0 Reference Frequency 0 1 PLL A Frequency 1 0 PLL B Frequency 1 1 PLL C Frequency Bit 71 Bit 70 0 0 Reference Frequency PLL A Frequency 0 1 1 0 PLL B Frequency Current = 10A 1 1 PLL C Frequency MUX C2 frequency select selected when the SEL_CD pin = 1 Current = 2A MUX_C2[1:0] (Bits 125-124) Current = 10A Charge Pump C1 selected when the SEL_CD pin = 0 Bit = 0 Bit 46 Current = 2A Charge Pump B CP_B (Bit 43) Bit 47 MUX C1 frequency select selected when the SEL_CD pin = 0 Charge Pump A CP_A (Bit 19) DESCRIPTION Current = 2A Charge Pump C2 selected when the SEL_CD pin = 1 Current = 2A Bit = 1 Current = 10A Bit 124 0 0 Reference Frequency 0 1 PLL A Frequency 1 0 PLL B Frequency 1 1 PLL C Frequency MUX D1 frequency select selected when the SEL_CD pin = 0 Current = 10A Bit = 0 Bit 125 MUX_D1[1:0] (Bits 95-94) Bit 95 Bit 94 0 0 Reference Frequency 0 1 PLL A Frequency 1 0 PLL B Frequency 1 1 PLL C Frequency MUX D2 frequency select selected when the SEL_CD pin = 1 MUX_D2[1:0] (Bits 127-126) Bit 127 Bit 126 0 0 Reference Frequency 0 1 PLL A Frequency 1 0 PLL B Frequency 1 1 PLL C Frequency 6.5.03 10 FS6377-01 Programmable 3-PLL Clock Generator IC 7.0 Electrical Specifications Table 11: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER SYMBOL MIN. MAX. UNITS VDD VSS-0.5 7 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 C Ambient Temperature Range, Under Bias TA -55 125 C Junction Temperature TJ 150 C Supply Voltage, dc (VSS = ground) Lead Temperature (soldering, 10s) 260 C 2 kV Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 12: Operating Conditions PARAMETER SYMBOL Supply Voltage VDD Ambient Operating Temperature Range TA Crystal Resonator Frequency fXIN Crystal Resonator Load Capacitance CXL Serial Data Transfer Rate Output Driver Load Capacitance CONDITIONS/DESCRIPTION 5V 10% 3.3V 10% Commercial Industrial MIN. TYP. MAX. 4.5 5 5.5 3 3.3 3.6 0 70 -40 85 5 Parallel resonant, AT cut Standard mode CL V C 27 MHz 100 kb/s 15 pF 18 10 UNITS pF 6.5.03 11 FS6377-01 Programmable 3-PLL Clock Generator IC Table 13: DC Electrical Specifications Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Supply Current, Dynamic, with Loaded Outputs IDD VDD = 5.5V, fCLK = 50MHz, CL = 15pF See Figure 10 for more information 43 mA Supply Current, Static IDDL VDD = 5.5V, device powered down 0.3 mA Power-Down, Output Enable Pins (PD, OE) High-Level Input Voltage VIH Low-Level Input Voltage VIL Hysteresis Voltage Vhys High-Level Input Current IIH Low-Level Input Current (pull-up) IIL VDD = 5.5V 3.85 VDD+0.3 VDD = 3.6V 2.52 VDD+0.3 VDD = 5.5V VSS-0.3 1.65 VDD = 3.6V VSS-0.3 1.08 VDD = 5.5V 2.20 VDD = 3.6V 1.44 -1 -36 V V V 1 A -80 A VIL = 0V -20 VDD = 5.5V 3.85 VDD+0.3 VDD = 3.6V 2.52 VDD+0.3 VDD = 5.5V VSS-0.3 1.65 VDD = 3.6V VSS-0.3 1.08 Serial Interface I/O (SCL, SDA) High-Level Input Voltage VIH Low-Level Input Voltage VIL Hysteresis Voltage Vhys High-Level Input Current VDD = 5.5V 2.20 VDD = 3.6V 1.44 IIH -1 Low-Level Input Current (pull-up) IIL VIL = 0V Low-Level Output Sink Current (SDA) IOL VOL = 0.4V, VDD = 5.5V -20 V V 1 -36 V -80 26 A A mA Mode and Frequency Select Inputs (ADDR, SEL_CD) VDD = 5.5V 2.4 VDD+0.3 VDD = 3.6V 2.0 VDD+0.3 VDD = 5.5V VSS-0.3 0.8 VDD = 3.6V VSS-0.3 0.8 High-Level Input Voltage VIH Low-Level Input Voltage VIL High-Level Input Current IIH -1 Low-Level Input Current (pull-up) IIL -20 -36 V V 1 A -80 A Crystal Oscillator Feedback (XIN) Threshold Bias Voltage VTH High-Level Input Current IIH Low-Level Input Current IIL VDD = 5.5V 2.9 VDD = 3.6V 1.7 VDD = 5.5V 54 VDD = 5.5V, oscillator powered down VDD = 5.5V 5 -25 Crystal Loading Capacitance * CL(xtal) As seen by an external crystal connected to XIN and XOUT Input Loading Capacitance * CL(XIN) As seen by an external clock driver on XOUT; XIN unconnected -54 V A 15 mA -75 A 18 pF 36 pF 6.5.03 12 FS6377-01 Programmable 3-PLL Clock Generator IC Table 14: DC Electrical Specifications, continued Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Crystal Oscillator Drive (XOUT) High-Level Output Source Current IOH VDD = V(XIN) = 5.5V, VO = 0V 10 21 30 mA Low-Level Output Sink Current IOL VDD = 5.5V, V(XIN) = 0V, VO = 5.5V -10 -21 -30 mA Clock Outputs (CLK_A, CLK_B, CLK_C, CLK_D) High-Level Output Source Current IOH VO = 2.4V -125 mA Low-Level Output Sink Current IOL VO = 0.4V 23 mA zOH VO = 0.5VDD; output driving high 29 zOL VO = 0.5VDD; output driving low 27 Output Impedance Tristate Output Current IZ -10 A 10 Short Circuit Source Current * ISCH VDD = 5.5V, VO = 0V; shorted for 30s, max. -150 mA Short Circuit Sink Current * ISCL VDD = VO = 5.5V, shorted for 30s, max. 123 mA Figure 9: CLK_A, CLK_B, CLK_C, CLK_D Clock Outputs MIN. TYP. MAX. Voltage (V) 0 0.2 0.5 0.7 1 1.2 1.5 1.7 2 2.2 2.5 2.7 3 3.5 4 0 9 22 29 39 44 51 55 60 62 65 65 66 67 68 0 11 25 34 46 52 61 66 73 77 81 83 85 87 88 0 12 29 40 55 64 76 83 92 97 104 108 112 117 119 0 0.5 1 1.5 2 2.5 2.7 3 3.2 3.5 3.7 4 4.2 4.5 4.7 4.5 5 5.5 69 High Drive Current (mA) MIN. TYP. MAX. -87 -85 -83 -80 -74 -65 -61 -53 -48 -39 -32 -21 -13 0 -112 -110 -108 -104 -97 -88 -84 -77 -71 -62 -55 -44 -36 -24 -15 -150 -147 -144 -139 -131 -121 -116 -108 -102 -92 -85 -74 -65 -52 -43 89 120 5 0 -28 91 121 5.2 -11 123 5.5 0 15 0 10 0 50 Output Current (mA) Low Drive Current (mA) Voltage (V) 0 - 0 .5 1.0 1 .5 2 .0 2.5 3.0 3 .5 4.0 4.5 5 .0 5.5 -5 0 -10 0 -15 0 M IN T YP -20 0 O utpu t V o lta ge (V ) MAX The data in this table represents nominal characterization data only. 6.5.03 13 FS6377-01 Programmable 3-PLL Clock Generator IC Figure 10: Dynamic Current vs. Output Frequency VDD = 5.0V; Reference Frequency = 27.00MHz; VCO Frequency = 200MHz, CL = 17pF except where noted 110 All outputs at the same frequency 100 All outputs at the same frequency, CL = 0pF Dynamic Current (mA) 90 80 All outputs at 200MHz except output under test 70 All outputs at 4MHz except output under test 60 50 All outputs off except output under test 40 30 20 All outputs off except output under test, CL = 0pF 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 Output Frequency (MHz) VDD = 3.3V; Reference Frequency = 27.00MHz; VCO Frequency = 100MHz, CL = 17pF except where noted 45 All outputs at the same frequency 40 Dynamic Current (mA) 35 All outputs at the same frequency, CL = 0pF 30 All outputs at 100MHz except output under test 25 All outputs at 2MHz except output under test 20 15 All outputs off except output under test 10 All outputs off except output under test, CL = 0pF 5 0 0 10 20 30 40 50 60 70 80 90 100 Output Frequency (MHz) 6.5.03 14 FS6377-01 Programmable 3-PLL Clock Generator IC Table 15: AC Timing Specifications Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION CLOCK (MHz) MIN. TYP. MAX. UNITS Overall Output Frequency * fO VCO Frequency * fVCO VCO Gain * AVCO Loop Filter Time Constant * Rise Time * tr Fall Time * tf Tristate Enable Delay * tPZL, tPZH Tristate Disable Delay * tPLZ, tPHZ Clock Stabilization Time * tSTB VDD = 5.5V 0.8 150 VDD = 3.6V 0.8 100 VDD = 5.5V 40 230 VDD = 3.6V 40 170 400 LFTC bit = 0 7 LFTC bit = 1 20 VO = 0.5V to 4.5V; CL = 15pF 1.9 VO = 0.3V to 3.0V; CL = 15pF 1.6 VO = 4.5V to 0.5V; CL = 15pF 1.8 VO = 3.0V to 0.3V; CL = 15pF 1.5 1 1 Output active from power-up, via PD pin MHz MHz/V s ns ns 8 ns 8 ns 1 ms s 100 After last register is written MHz Divider Modulus Feedback Divider NF Reference Divider NR Post Divider NP See also Table 2 See also Table 8 8 2047 1 255 1 50 45 55 Clock Outputs (PLL A clock via CLK_A pin) Duty Cycle * Jitter, Long Term (y()) * Jitter, Period (peak-peak) * tj(LT) tj(P) Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 100 On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, No other PLLs active 100 45 On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (B=60MHz, C=40MHz, D=14.318MHz) 50 165 From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, No other PLLs active 100 110 From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (B=60MHz, C=40MHz, D=14.318MHz) 50 % ps ps 390 6.5.03 15 FS6377-01 Programmable 3-PLL Clock Generator IC Table 16: AC Timing Specifications, continued Unless otherwise stated, VDD = 5.0V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. PARAMETER SYMBOL CLOCK (MHz) MIN. Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 100 45 On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, No other PLLs active 100 45 On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, C=40MHz, D=14.318MHz) 60 75 100 120 60 400 CONDITIONS/DESCRIPTION TYP. MAX. UNITS 55 % Clock Outputs (PLL B clock via CLK_B pin) Duty Cycle * Jitter, Long Term (y()) * Jitter, Period (peak-peak) * tj(LT) tj(P) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, No other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, C=40MHz, D=14.318MHz) ps ps Clock Outputs (PLL_C clock via CLK_C pin) Duty Cycle * Jitter, Long Term (y()) * Jitter, Period (peak-peak) * tj(LT) tj(P) Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 100 On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, No other PLLs active 100 On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, B=60MHz, D=14.318MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, No other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, B=60MHz, D=14.318MHz) 45 55 % 45 ps 40 105 100 120 40 440 ps Clock Outputs (Crystal Oscillator via CLK_D pin) Duty Cycle * Jitter, Long Term (y()) * Jitter, Period (peak-peak) * tj(LT) tj(P) Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 14.318 On rising edges 500s apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, No other PLLs active 14.318 20 From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, all other PLLs active (A=50MHz, B=60MHz, C=40MHz) 14.318 40 From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, No other PLLs active 14.318 90 From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, all other PLLs active (A=50MHz, B=60MHz, C=40MHz) 14.318 450 45 55 % ps ps 6.5.03 16 FS6377-01 Programmable 3-PLL Clock Generator IC Table 17: Serial Interface Timing Specifications Unless otherwise stated, all power supplies = 3.3V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION SCL STANDARD MODE MIN. MAX. 0 100 UNITS Clock frequency fSCL Bus free time between STOP and START tBUF 4.7 kHz s Set up time, START (repeated) tsu:STA 4.7 s Hold time, START thd:STA 4.0 s Set up time, data input tsu:DAT SDA 250 ns Hold time, data input thd:DAT SDA 0 s Output data valid from clock tAA Minimum delay to bridge undefined region of the falling edge of SCL to avoid unintended START or STOP Rise time, data and clock tR Fall time, data and clock tF High time, clock tHI SCL 4.0 s Low time, clock tLO SCL 4.7 s 4.0 s Set up time, STOP 3.5 s SDA, SCL 1000 ns SDA, SCL 300 ns tsu:STO Figure 11: Bus Timing Data ~ ~ SCL ~ ~ thd:STA tsu:STA tsu:STO SDA DATA CAN CHANGE ~ ~ ADDRESS OR DATA VALID START STOP Figure 12: Data Transfer Sequence tHI SCL tR ~ ~ tF tLO tsu:STA thd:STA tAA tAA ~ ~ SDA IN tsu:DAT tsu:STO ~ ~ thd:DAT tBUF SDA OUT 6.5.03 17 FS6377-01 Programmable 3-PLL Clock Generator IC 8.0 Package Information Table 18: 16-pin SOIC (0.150") Package Dimensions DIMENSIONS INCHES 16 MILLIMETERS MIN. MAX. MIN. MAX. A 0.061 0.068 1.55 1.73 A1 0.004 0.0098 0.102 0.249 A2 0.055 0.061 1.40 1.55 B 0.013 0.019 0.33 0.49 C 0.0075 0.0098 0.191 0.249 D 0.386 0.393 9.80 9.98 E 0.150 0.157 3.81 3.99 e 0.050 BSC R E 1 ALL RADII: 0.005" TO 0.01" B e 1.27 BSC H 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 0 8 0 8 H AMERICAN MICROSYSTEMS, INC. A2 D A A1 BASE PLANE h x 45 7 typ. C L SEATING PLANE Table 19: 16-pin SOIC (0.150") Package Characteristics PARAMETER SYMBOL Thermal Impedance, Junction to Free-Air 16-pin 0.150" SOIC JA Lead Inductance, Self L11 CONDITIONS/DESCRIPTION TYP. UNITS Air flow = 0 m/s 110 C/W Corner lead 4.0 Center lead 3.0 nH Lead Inductance, Mutual L12 Any lead to any adjacent lead 0.4 nH Lead Capacitance, Bulk C11 Any lead to VSS 0.5 pF 6.5.03 18 FS6377-01 Programmable 3-PLL Clock Generator IC 9.0 Ordering Information 9.1 Device Ordering Codes ORDERING CODE DEVICE NUMBER FONT PACKAGE TYPE OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION 11486-801 FS6377 -01 16-pin (0.150") SOIC (Small Outline Package) 0C to 70C (Commercial) Tape-and-Reel 11486-811 FS6377 -01 16-pin (0.150") SOIC (Small Outline Package) 0C to 70C (Commercial) Tubes 11486-901 FS6377 -01i 16-pin (0.150") SOIC (Small Outline Package) -40C to 85C (Industrial) Tape-and-Reel 11486-911 FS6377 -01i 16-pin (0.150") SOIC (Small Outline Package) -40C to 85C (Industrial) Tubes 9.2 Demo Kit Ordering Codes ORDERING CODE KIT FOR DEVICE NUMBER: 11486-201 DESCRIPTION Kit includes: * Populated board with example device * Interface Cable * Demonstration Software FS6377-01 2 Purchase of I C components of American Microsystems, Inc., or one of its sublicensed Associated Compa2 2 nies conveys a license under Philips I C Patent Rights to use these components in an I C system, provided 2 that the system conforms to the I C Standard Specification as defined by Philips. Copyright (c) 1998, 1999 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com 6.5.03 19 FS6377-01 Programmable 3-PLL Clock Generator IC The board schematic is shown below. Components listed with an asterisk (*) are not required in an actual application, and are used here to preserve signal integrity with the cabling associated with the board. A cabled interface between a computer parallel port (DB25 connector) and the board (J1) is provided. Components shown in dashed lines are optional, depending on the application. Contact your local sales representative or the company directly for more information. 10.0 Demonstration Board and Software A simple demonstration board and Windows 3.1x/95/98based software is available from American Microsystems that illustrates the capabilities of the FS6377. The software can operate under Windows NT but cannot communicate with the board. Figure 13: Board Schematic +V +V RED +5V/3.3V +V +V TP1 R12 4.7k J1* 1 +V +V R13 4.7k R11 4.7k R5 10 R14 4.7k R1 100 SCL SDA ADDR/ MODE SEL +5V GND U1 R3 100 3 1 +V H1* R10 100 4 C9 100pF C11 100pF 3 4 PD 6 C10 100pF C12 100pF +V GND 2 SEL 5 BLK C2 2.2F C4 0.1F R2 100 2 OE 5 Y1 R4 10 6 7 TP2 8 C1 2.2F SDA SCL SEL_CD CLK_A PD VDD VSS XIN XOUT OE VDD C3 0.1F CLK_B FS6377 CLK_C VSS CLK_D ADDR +V 16 15 14 R6* 47 CLK_A C5 10pF 13 12 D1 TP3 +V R7* 47 D2 TP4 CLK_B 11 C6 10pF 10 +V 9 R8* 47 D3 TP5 CLK_C C7 10pF +V AMERICAN MICROSYSTEMS, INC. FS6377 BOARD R9* 47 TP6 D4 CLK_D C8 10pF 6.5.03 20 FS6377-01 Programmable 3-PLL Clock Generator IC 10.1 * Demonstration board * Interface cable (DB25 to 6-pin connector) * Data sheet * Demonstration software, totaling 24 compressed files which will expand to 1.8MB, including fs6370.exe after installation. 10.2 PC running MS Windows 3.1x or 95/98 with an accessible parallel (LPT1) port. Software also runs on Windows NT in a calculation mode only. * 1.8MB available space on hard drive C * Connect a power supply to the board: RED = power, BLACK = ground. * Connect the supplied interface cable to the parallel port (DB25 connector) and to the demo board (6-pin connector). Make sure the cable is facing away from the board. Pin 1 is the red wire per Table 20. * Connect the clock outputs to the target application board with a twisted-pair cable. 10.4 Requirements * 10.3 * Demo Kit Contents Demo Program Operation Launch the fs6377.exe program. Note that the parallel port can not be accessed if your machine is running Windows NT. A warning message will appear stating: "This version of the demo program cannot communicate with the FS6377 hardware when running on a Windows NT operating system. Do you want to continue anyway, using just the calculation features of this program?" Clicking OK starts the program for calculation only. The opening screen is shown in Figure 14. Board Setup and Software Installation Instructions At the appropriate disk drive prompt (A:\) unzip the compressed demo files to a directory of your choice. Run setup.exe to install the software. Figure 14: Opening Screen 6.5.03 21 FS6377-01 Programmable 3-PLL Clock Generator IC PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both Mux C and Mux D are also affected by the logic level on the SEL_CD pin, as are the Post Dividers C and D. 10.4.1 Example Programming Type a value for the crystal resonator frequency in MHz in the Reference Crystal box. This frequency provides the basis for all of the PLL calculations that follow. Next, click on the PLL A box. A pop-up screen similar to Figure 15 should appear. Type in a desired Output Clock frequency in MHz, set the operating voltage (3.3V or 5V), and the desired maximum output frequency error. Pressing Calculate Solutions generates several possible divider and VCO-speed combinations. Figure 16: Post Divider Menu Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the Post Divider B as the output divider. Notice the Post Divider box has split in two (as shown in Figure 16). The Post Divider B box now shows that the divider is dependent on the setting of the SEL_CD pin for as long as Mux B is the PLL C output. Figure 15: PLL Screen Clicking on Post Divider A reveals a pull-down menu provided to permit adjustment of the Post Divider value independently of the PLL screen. A typical menu is shown in Figure 16. The range of possible post divider values is also given in Table 8. Once all of the PLLs, switches, and post dividers have been set, the information can be downloaded out the PC parallel port to the FS6377 (not available on Windows NT). The register settings are shown to the left in the screen shown in Figure 14. Clicking on a register location displays a screen shown in Figure 17. Individual bits can be poked, or the entire register value can be changed. For a 100MHz output, the VCO should ideally operate at a higher frequency, and the Reference and Feedback Dividers should be as small as possible. In this example, highlight Solution #7. Notice the VCO operates at 200MHz with a Post Divider of 2 to obtain an optimal 50% duty cycle. Now choose which Mux and Post Divider to use (that is, choose an output pin for the 100MHz output). Selecting A places the PostDiv value in Solution #7 into Post Divider A and switches Mux A to take the output of PLL A. The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in Solution #7. Also note that Mux A has been switched to PLL A and the Post Divider A has the chosen 100MHz output displayed. Repeat the steps for PLL B. Figure 17: Register Screen 6.5.03 22 FS6377-01 Programmable 3-PLL Clock Generator IC Table 20: Cable Interface Color J1 Figure 19: Board Layout DB25 Signal Red 1 2, 13 SCL White 2 3, 12 SDA Green 3 8 MODE Blue 4 5 SEL Brown 5 4 +5V Black 6 25 GND Figure 18: Cable Diagram PIN 2 RED 3 WHT 8 GRN 5 BLU 4 BRN 13 BLK 12 25 PIN 100 1 2 3 4 5 6 J1 100 DB-25 6.5.03 23