CY28159ZC - Spectra Linear, Inc.

CY28159

Clock Generator for Serverworks Grand Champion Chipset

Applications

Rev 1.0, November 24, 2006 Page 1 of 12

2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com

1CY28159

Features

• Eight differential CPU clock outputs

• One PCI output

• One 14.31818 MHz reference clock

• Two 48 MHz clocks

• All outputs compliant with Intel® specifications

• External resistor for current reference

• Selection logic for differential swing control, test mode,

Hi-Z, power-down and spread spectrum

• 48-pin SSOP and TSSOP packages

Table 1. Frequency Selection

SEL 100/133 S0 S1 CPU(0:7), CPU#(0:7) 3V33 48M(0,1) Notes

0 0 0 100 MHz 33.3MHz 48 MHz Normal Operation

0 0 1 100 MHz 33.3MHz Disable Test Mode(recommended)

0 1 0 100 MHz Disable Disable Test Mode (optional)

0 1 1 Hi-Z Hi-Z Hi-Z Hi-Z all outputs

1 0 0 133.3MHz 33.3MHz 48 MHz Optional

1 0 1 133.3MHz 33.3MHz Disable Optional

1 1 0 200MHz 33.3MHz 48 MHz o7ptional

1 1 1 N/A N/A N/A Reserved

Table 2.

kDi

agram Pin Configuration

OSC

VCO

Control

VDDI

I_Ref VSSI

REF

CPU (0:7)

CPU (0:7)#

48M(0,1)/S(0,1)

VDDL

3V33

VSSL

SSCG#

SEL100/133

XOUT

XIN

MultSel(0:1)

PD# S(0,1)

3V33

VDD

48M0/S0

48M1/S1

VSS

VDD

CPU0

CPU0#

VSS

CPU1

CPU1#

VDD

CPU2

CPU2#

VSS

CPU3

CPU3#

VDD

REF

SSCG#

VSS

XIN

XOUT

VDD

SEL100/133

VSS

VDDA

VSSA

PD#

VDD

CPU4

CPU4#

VSS

CPU5

CPU5#

VDD

CPU6

CPU6#

VSS

CPU7

CPU7#

VDD

MULT0

MULT1

VSS

VSSA

IREF

VDDA

CY28159

Rev 1.0, November 24, 2006 Page 2 of 12

Note:

1. Definition of I/O column mnemonic on pin description table above 1= Input pin, O = output pin, P = power supply pin, PU = indicates that a bidirectional pin contains

pull-up resistor. This will insure that this pin of the device will be seen by the internal logic as a logic 1 level. Likewise pins with a PD designation are guaranteed

to be seen as a logic 0 level if no external level setting circuitry is present at power up.

Pin Description

Pin Name I/O[1] Description

20 SSCG PU

When asserted LOW, this pin invokes Spread Spectrum functionality. Spread

spectrum is applicable to CPU(0:7), CPU(0:7)#. This pin has a 250-k: internal

pull-up.

7,10, 13, 16,

42, 39, 36, 33

CPU(0:7) O Differential host clock outputs. These outputs are used in pairs, (CPU0-0#,

CPU1-1#, CPU2-2#, CPU3-3#, CPU4-4#, CPU5-5#, CPU6-6#, and CPU7-7#)

for differential clocking of the host bus. CPU(0:7) are 180 degrees out of phase

with their complements, CPU(0:7)#. See Table 1 on page 1

8, 11, 14, 17,

41, 38, 35, 32

CPU(0:7)#

26 IRef P This pin establishes the reference current for the internal current steering

buffers of the CPU clocks. A resistor is connected from this pin to ground to set

the value of this current.

1 3V33 O Fixed 33.3-MHz clock output.

44 PD# PU

When asserted LOW, this pin invokes a power-down mode by shutting off all

the clocks, disabling all internal circuitry, and shutting down the crystal oscil-

lator. The 48M(0:1) and REF clocks are driven LOW during this condition and

the CPU clocks are driven HIGH and programmed with an 2X IREF current. It

has a 250-k: internal pull-up.

3, 4 48M(0,1), S(0,1) IO S0 and S1 inputs are sensed on power-up and then internally latched. After-

wards the pins are 3V 48-MHz clocks.

48 SEL100/133 PU

Input select pin. See Table 1 on page 1.

It has a 250-k: internal Pull-up

23 XOUT O Crystal Buffer output pin. Connects to a crystal only. When an external signal

other than a crystal is used or when in Test mode, this pin is kept unconnected.

22 XIN I Crystal Buffer input pin. Connects to a crystal, or an external single ended input

clock signal.

19 REF O A buffered output clock of the signal applied at Xin. Typically, 14.31818 MHz.

30, 29 Mult(0,1) I These input select pins configure the Ioh current (and thus the Voh swing

amplitude) of the CPU clock output pairs. Each pin has a 250-k: internal

Pull-up. See Table 6 for current and resistor values.

25, 46 VDDA P 3.3V power supply pins.

2, 6, 12, 18, 24,

31, 37, 43

VDD P 3.3V power supply pins for common supply to the core.

5, 9, 15, 21, 28,

34, 40, 47

VSS P Ground pins for common supply to the core.

27, 45 VSSA P Ground pins.

CY28159

Rev 1.0, November 24, 2006 Page 3 of 12

Test Load Configuration

The following shows test load configurations for the different Host Clock Outputs.(MULTsel1 = 0, MULTsel0 =1

Table 3. Group Offset Specifications

Group Offset Comments

CPU to 3V33 No requirement

CPU to REF No requirement

Table 4. Group Limits and Parameters (Applicable to all

settings: Sel133/100#=x)

Output Name Max Load

CPU[(0:7)#] See Figure 1

REF 20 pF

3V33 30 pF

CPUT

MULTSEL

TPCB

CPUT#

:

: Measurement Point

:

: 2pF

Measurement Point

2pF

:

VDD

Figure 1. 0.7V Test Load Termination

CLOAD

Probe

Output Under Test

Figure 2. Lumped Load Termination

CY28159

Rev 1.0, November 24, 2006 Page 4 of 12

2.4V

0.4V

3.3V

Tr Tf

1.5V

3.3V signals

tDC

Figure 3. 3.3V Measurement Points

CY28159

Rev 1.0, November 24, 2006 Page 5 of 12

Spread Spectrum Clock Generation (SSCG)

Spread Spectrum is a modulation technique applied here for

maximum efficiency in minimizing Electro-Magnetic Inter-

ference radiation generated from repetitive digital signals

mainly clocks. For a detailed explanation of Spread Spectrum

Clock Generation.

Power Management Functions

Notes:

2. The entries in boldface are the primary system configurations of interest. The outputs should be optimized for these configurations.

3. Rr refers to the resistance placed in series with the Iref input and VSS.

Table 5. Spectrum Spreading Selection Table

Unspread Frequency in MHz Spread Spectrum Parameter

Downspreading

F Min(MHz) F Center(MHz) F Max(MHz) Spread (%)

100 99.5 99.75 100 –0.5%

133.3 132.66 132.67 133 –0.5%

200 199.5 199.75 200 –0.5%

Table 6. Host Swing Select Functions[2]

Multsel0 MultSel1

Board Target

Trace/TermZ

Reference Rr, Iref = Vdd(3*Rr)

Note 3 Output Current

Voh@Z, Iref = 2.32

0 0 60 Ohms Rf = 475 1%,

Iref = 2.32 mA Ioh = 5*Iref 07V@60

0 0 50 Ohms Rr = 475 1%,Iref = 2.32 mA Ioh = 5*Iref 0.59V @ 50

0 1 60 Ohms Rr = 475 1%,Iref = 2.32 mA Ioh = 6*Iref 0.85V @ 60

0 1 50 Ohms Rr = 475 1%,Iref = 2.32 mA Ioh = 6*Iref 0.71V @ 50

1 0 60 Ohms Rr = 475 1%,Iref = 2.32 mA Ioh = 4*Iref 0.56V @ 60

1 0 50 Ohms Rr = 475 1%,Iref = 2.32 mA Ioh = 4*Iref 0.47V @ 50

1 1 60 Ohms Rr = 475 1%,Iref = 2.32 mA Ioh = 7*Iref 0.99V @ 60

1 1 50 Ohms Rr = 475 1%,Iref = 2.32 mA Ioh = 7*Iref 0.82V @ 50

CY28159

Rev 1.0, November 24, 2006 Page 6 of 12

Buffer Characteristics

Current Mode CPU Clock Buffer Characteristics

The current mode output buffer detail and current reference

circuit details are contained elsewhere in this datasheet. The

following parameters are used to specify output buffer charac-

teristics:

1. Output impedance of the current mode buffer circuit - Ro

(see Figure 4)

2. Minimum and maximum required voltage operation range

of the circuit - Vop (see Figure 4).

3. Series resistance in the buffer circuit - Ros (see Figure 4)

4. .Current accuracy at given configuration into nominal test

load for given configuration

Iout is selectable depending on implementation. The param-

eters above supply to all configurations. Vout is the voltage at

the pin of the device.

The various output current configurations are shown in the

host swing select functions table. For all configurations, the

deviation from the expected output current is ±7% as shown in

the table current accuracy.

1.2V0V

Iout

Ros

VDD3 (3.3V +/- 5%)

Vout = 1.2V max Vout

Figure 4.

Table 7. Host Clock (HSCL) Buffer Characteristics

Characteristics Minimum Maximum

Ro 3000 Ohms (recommended) N/A

Ros Unspecified Unspecified

Vout N/A 1.2 Volt

CY28159

Rev 1.0, November 24, 2006 Page 7 of 12

Note:

4. Inom refers to the expected current based on the configuration of the device.

Table 8. Current Accuracy

Conditions Configuration Load Min. Max.

Iout VDD = nominal (3.30V) All combinations of M0, M1 and Rr shown in

Host Swing Select Function, Table 6 on page 5

Nominal test load for

given configuration

–7% Inom +7% Inom

Iout VDD = 3.30 ± 5% All combinations of M0, m1 and Rr shown in

Host Swing Select Function, Table 6 on page 5

Nominal test load for

given configuration

–12% Inom +12% Inom

Table 9. Buffer Characteristics for REF, 48M(0,1)

Parameter Description Conditions Min. Typ. Max. Unit

IOHmin Pull-Up Current Min. VOH = VDDmin – 0.5V (2.64V) –12 –53 mA

IOHmax Pull-Up Current Max. VOH = VDDmin/2 (1.56V) –27 –92 mA

IOLmin Pull-Down Current Min. VOL = 0.4V 9 27 mA

IOLmax Pull-Down Current Max. VOL = VDDmin/2 (1.56V) 26 79 mA

Trh 3.3V Output Rise Edge Rate 3.3V ± 5% @ 0.4V–2.4V 0.5 2.0 V/ns

Tfh 3.3V Output Fall Edge Rate 3.3V ± 5% @ 2.4V–0.4V 0.5 2.0 V/ns

Table 10.Buffer Characteristics for 3V33[4]

Parameter Description Conditions Min. Typ. Max. Unit

IOHmin Pull-Up Current Min. VOH = VDDmin – 0.5V (2.64V) –11 –83 mA

IOHmax Pull-Up Current Max. VOH = VDDmin/2 (1.56V) –30 –184 mA

IOLmin Pull-Up Current Max. VOL = 0.4V 9 38 mA

IOLmax Pull-Down Current Max. VOL = VDDmin/2 (1.56V) 28 148 mA

Trh 3.3V Output Rise Edge Rate 3.3V ± 5% @ 0.4V–2.4V 1/1 4/1 V/ns

Tfh 3.3V Output Fall Edge Rate 3.3V ± 5% @ 2.4V–0.4V 1/1 4/1 V/ns

CY28159

Rev 1.0, November 24, 2006 Page 8 of 12

Maximum Ratings[5]

Input Voltage Relative to VSS:...............................VSS – 0.3V

Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V

Storage Temperature: ................................ –65qC to + 150qC

Operating Temperature:.................................... 0qC to +70qC

Maximum ESD.............................................................2000V

Maximum Power Supply:................................................5.5V

This device contains circuitry to protect the inputs against

damage due to high static voltages or electric field. However,

precautions should be take to avoid application of any voltage

higher than the maximum rated voltages to this circuit. For

proper operation, VIN and VOUT should be constrained to the

range.

VSS < (VIN or VOUT)< VDD

Unused inputs must always be tied to an appropriate logic

voltage level (either VSS or VDD).

Notes:

5. The voltage on any input or I/O pin canno t exceed th power pin during power-up. Power supply sequencing is NOT required.

6. Applicable to input signals: Sel100/133, Sel(0:1)), Spread#, PWRDN#, Mult(0:1)

7. Although internal pull-up or pull-down resistors have a typical value of 250k, this value may vary between 200k and 500k.

8. All outputs loaded as per Table 4.

DC Parameters (VDD = VDDA = 3.3V±5%, TA= 0°C to +70°C)

Parameter Description Conditions Min. Typ. Max. Unit

VIL1 Input Low Voltage Note 6 0.8 Vdc

VIH1 Input High Voltage 2.0 Vdc

IIL Input Low Current (@VIN–VDD) For internal pull-up resistors[6] –16 –4 PA

IIH Input High Current (@VIN–VDD)05PA

IIL nput Low Current (@VIN–VSS) For internal pull-down resistors[6] 0PA

IIH Input High Current (@VIN–VSS)416PA

Ioz Three-State leakage current 10 PA

Idd Static Supply Current PwrDwn = Low 80 mA

Isdd Dynamic Supply Current 133 MHz CPU[8] 200 mA

Cin Input Pin Capacitance 5pF

Cout Output Pin Capacitance 6pF

Lpin Pin Inductance 7nH

Cxtal Crystal Pin Capacitance Measured from Pin to Ground. 34 36 38 pH

Txs Crsytal Startup Time From stable 3.3V power supply 40 PS

Rpi Internal Pull-up and Pull-down

Resistor Value[7] 200 250 500 k:

CY28159

Rev 1.0, November 24, 2006 Page 9 of 12

Notes:

9. This parameter is measured at the crossing points of the differential signals, and acquired as an average over 1Ps duration, with a crystal center frequency of

14.31818 MHz.

10. All outputs loaded as per Table 4, see Figure 2.

11. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and at 20% and 80% for CPU[(0:7), (0:7)#] signals (see

Figure 3).

12. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at crossing points for CPU clocks (see Figure 3).

13. This measurement is applicable with Spread ON or Spread OFF.

14. Probes are placed on the pins, and measurements are acquired at 2.4V (see Figure 3).

15. Probes are placed on the pins, and measurements are acquired at 0.4V. (seeFigure 3).

16. As this function is available through SEL(0,1), therefore, the time specified is guaranteed by design.

17. Determined as a fraction of 2*(Trp-Trn) / (Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge.

AC Parameters (VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C)

Symbol Description 133 MHz Host 100 MHz Host Unit Notes

Min. Max. Min. Max.

CPU

TPeriod CPU(0:7), (0:7)#) Period 7.35 7.65 9.85 10.2 ns 10,12

Tr/Tf CPU[(0:7), (0:7)#] Rise and Fall Times 175 700 175 700 ps 10,11

TSKEW1 Skew from Any CPU Pair to Any CPU Pair 100 100 ps 10,12,13

TCJJ CPU[(0:7), (0:7)#] Cycle to Cycle Jitter 150 150 ps 10,12,13

Vover CPU[(0:7), (0:7)#] Overshoot Voh + 0.2 Voh + 0.2 V 10,17

Vunder CPU[(0:7), (0:7)#] Undershoot –0.2 -0.2 V 10,17

Vcrossover CPU(0:7), to CPU(0:7)# Crossover Point 45%Voh 55%Voh 45%Voh 55%Voh V 9, 10,12

Tduty Duty Cycle 45 55 45 55 % 10,12

33MHz

Tperiod 3V33 Period 15.0 16.0 15.0 15.2 ns 10,12

THIGH 3V33 High Time 5.25 5.25 ns 10,14

TLOW 3V33 Low Time 5.05 5.05 ns 10,15

Tr/Tf 3V33 Rise and Fall Times 0.5 2.0 0.5 2.0 ns 10,11

TCCJ 3V33 Cycle to Cycle Jitter 300 - 300 ps 10,12,13

Tduty Duty Cycle 45 55 45 55 % 10,12

REF

Tperiod REF Period 69.8412 71.0 69.8413 71.0 nS 10,12

Tr/Tf REF Rise and Fall Times 1.0 4.0 1.0 4.0 nS 10,11

TCCj REF Cycle to Cycle Jitter 1000 1000 pS 10,12

Tduty Duty Cycle 45 55 45 55 % 10,12

48MHz

TDC 48MHz(0,1) Duty Cycle 45 55 45 55 % 10,12

Tperiod 48MHz(0.1) Period 20.8299 20.8333 20.8299 20.8333 ns 10,12

Tr/Tf 48MHz(0,1) Rise and Fall Times 1.0 4.0 1.0 4.0 ps 10,11

TCCJ 48MHz(0,1) Cycle to Cycle Jitter 500 500 ps 10,12

Zout 48MHz Buffer Output Impedance 20 20 :

tpZL, tpZH Output Enable Delay (all outputs) 1.0 10.0 1.0 10.0 ns 16

tpLZ, tpZH Output Disable Delay (all outputs) 1.0 10.0 1.0 10.0 ns 16

tstable All Clock Stabilization from Power-up 3 3 ms

CY28159

Rev 1.0, November 24, 2006 Page 10 of 12

Sample Layout

+3.3V Supply

C1 C2

0.005 PF

10 PF

0.005PF

G G GG

VDDQ3A*

VDDQ3

CY28159

G= VIA to GND plane layer V=VIA to respective supply plane layer

Note: Each supply plane or strip should have a

ferrite bead and capacitors

Cermaic CapsC1 & C3 = 10–22 µF C2 & C4 = 0.005 µF

FB = Dale ILB1206 - 300 (300:@ 100 MHz)

All bypass caps = 0.1 PF cermamic. Low ESR

CY28159

Rev 1.0, November 24, 2006 Page 11 of 12

Ordering Information

Part Number Package Type Product Flow

CY28159PVC 48-Pin SSOP Commercial, 0q to 70qC

CY28159PVCT 48-Pin SSOP - Tape and Reel Commercial, 0q to 70qC

CY28159ZC 48-Pin TSSOP Commercial, 0q to 70qC

CY28159ZCT 48-Pin TSSOP - Tape and Reel Commercial, 0q to 70qC

Package Drawing and Dimensions

48-LeadShrunkSmallOutlinePackageO48

51 85061 *C

Rev 1.0, November 24, 2006 Page 12 of 12

CY28159

While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-

cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in

normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-

tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional

processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any

circuitry or specification without notice.

Package Drawing and Dimensions (continued)

48-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z48