fy, SGS-THOMSON Y, Scs-THomss Ics Z84C40 Z84C41-Z84C42 Z80C SIO CMOS VERSION TWO INDEPENDENT FULL-DUPLEX CHAN- NELS, WITH SEPARATE CONTROL AND STATUS LINES FOR MODEMS OR OTHER DEVICES = DATATRANSFER RATE UP TO 800K BIT/SEC- OND aw ASYNCHRONOUS PROTOCOLS : EVERY- THING NECESSARY FOR COMPLETE MESS- AGES IN 5, 6, 7 OR 8 BITS/CHARACTER. INCLUDES VARIABLE STOP BITS AND SEV- ERAL CLOCK-RATE MULTIPLIERS ; BREAK GENERATION AND DETECTION ; PARITY ; OVERRUN AND FRAMING ERROR DETEC- TION SYNCHRONOUS PROTOCOLS : EVERYTHING NECESSARY FOR COMPLETE BIT- OR BYTE- ORIENTED MESSAGES IN 5, 6,7 OR 8 BITS/CHARACTER, INCLUDING IBM BISYNC, SDLC, HDLC, CCITT-X.25 AND OTHERS. AUTOMATIC CRC GENERATION/CHECKING SYNC CHARACTER AND ZERO_ INSER- TION/DELETION, ABORT GENERATION/DE- TECTION AND FLAG INSERTION RECEIVER DATA REGISTERS QUADRUPLY BUFFERED, TRANSMITTER REGISTERS DOUBLY BUFFERED s HIGHLY SOPHISTICATED AND FLEXIBLE DAISY-CHAIN INTERRUPT VECTORING FOR INTERRUPTS WITHOUT EXTERNAL LOGIC SINGLE 5V + 10% POWER SUPPLY a LOW POWER CONSUPTION : ~ 2.5mA TYP. AT 4MHz - 4mA TYP. AT 6MHz - LESS THAN 10uA INPOWER DOWN MODE a EXTENDED OPERATING TEMPERATURE - 40C TO + 85C DESCRIPTION The Z80C SIO Serial Input/Output Controller is a dual-channel data communication interface with extraordinary versatility and capability. Its basic functions as a serial-to-parallel, parallel-to-serial September 1988 PLCOC44 (Plastic) (Ordering Information at the end of the datasheet) converter/controller can be programmed by a CPU for a broad range of serial communication applica- tions. The device supports all common asynchronous and synchronous protocols, byte- or bit-oriented and performs ali of the functions traditionally done by UARTs, USARTs and synchronous communication controllers combined, plus additional functions tradi- tionally performed by the CPU, Moreover, it does this on two fully-independent channels, with an ex- ceptionally sophisticated interrupt structure that allows very fast transfers. Full interfacing is provided for CPU or DMA control. in addition to data communication, the circuit can handle virtually all types of serial I/O with fast (or slow) peripheral devices. While designed primarily as a member of Z80 fam- ily, its versatility makes it well suited to many other CPUs. 1/24 93284C40-Z84C41-284C42 PIN DESCRIPTIONS Figures 1 through 6 illustrate the three pin configu- rations (bonding options) available in the SIO. The constraints of a 40-pin package make it impossible to bring_out the Receive Clock (RxC), Transmitt Clock (TxC), Data Terminal Ready (DTR) and Sync (SYNC) signals for both channels. Therefore, either Channel B lacks a signal or two signals are bonded together in the three bonding options offered : a 280C SIO-2 lacks SYNCB a Z80C S!O-1 lacks DTRB a Z80C S!O-0 as a four signal, but TxCB and RxCB are bonded together The first bonding option above (SIO-2) is the preferred version for most applications. The Chip- Carrier package version, having a 44-pin facility, re- sume the three bonding option configurations. It is named Z284C44 (figure 7). The pin description are as follows : B/A. Channel A Or B Select (tnput, High Selects Channel B). This input defines which channel is ac- cessed during a data transfer between the CPU and the SIO. Address bit Ao from the CPU is often used for the selection function. C/D. Control Or Data Select (Input, High Selects Control). This input defines the type of information transfer performed between the CPU and the SIO. A High at this input during a CPU write to the SIO causes the information on the data bus to be inter- preted as a command for the channel selected by Figure 1 : Z80C SIO-2 Logic Functions. B/A. A Low at C/D means that the information on the data bus is data. Address bit A; is often used for this function. CE. Chip Enable (Input, Active Low). A Low level at this input enables the SIO to accept command or data input from the CPU during a write cycle or to transmit data to the CPU during a read cycle. CLK. System Clock (Input). The SIO uses the stand- ard Z80 System Clock to synchronize internal sig- nals. This is a single-phase clock. CTSA, CTSB. Clear To Send (Inputs, Active Low). When programmed as Auto Enables, a Low on these inputs enables the respective transmitter. If not programmed as Auto Enables, these inputs may be programmed as general-purpose inputs. Both in- puts are Schmitt-trigger buffered to accommodate slow-risetime signals. The SIO detects pulses on these inputs and interrupts the CPU on both logic level transitions. The Schmitt-trigger buffering does not guarantee a specified noise-level margin. Do-D7. System Data Bus (Bidirectional, 3-state). The system data bus transfers data and commands between the CPU and the Z80C SIO. Dois the least significant bit. DCDA, DCDB. Data Carrier Detect (Inputs, Active Low). These pins function as receiver enables if the SIO is programmed for Auto Enables ; otherwise they may be used as general-purpose input pins. cpu DATA aus | Ty | CONTHOL | -~] j0#0 FROM A cpu IRTERAUPT = CONTROL | +1!0 Daisy | -J int CHAIN +] neser 284C42 R104 | --___ ACA | - t.04 -_ TaCa f--__ SYNCA | + wWiREYA -_e CHANNEL A RISA }__ crSA |~ | mooem OFR& }-e CUNTHUL DCcoA | __. AsO68 |-_. arcs |--_ hoa; 1268 [-+= wiaoya - CHANNEL B aTs }-~_ c1s8 |-- | mapEm prRe CONTROL ocos |-_. Vcc GND ctx 2/24 kyr SGS-THOMSON RISBOELECTAOR (SS 94Figure 2 : Z80C SIO-2 Dual in Line Pin Configuration. %. (jt 40 H 0, 0;()2 39 [Jo, o, (] 3 33D o, op, Cys a7 [] int C] > 4 [] ioKo iC) s as[] cE oC]? 3a] aA mi C] 6 aa LJ co Vec (Js 32] no wroya (] 10 un] cao synca C] 1 284C42 4, } winova Rada (] 12 29] ards aca CJ 13 2a[L] ance TCA CJ 14 27P] mca aoa (J 5 26 [] 108 OTRA q 16 2 a OTe atsa (] 7 za[_] atse CTSA q " 2a [J crse ocoA 9 22 |] ocos CLK q 70 21] aeser Both pins are Schmitt-trigger buffered to accommo- date slow-risetime signals. The SIO detects pulses on these pins and interrupts the CPU on both logic level transitions. Schmitt-trigger buffering does not guarantee a specific noise-level margin. Figure 3 : Z80C SIO-1 Logic Functions. 284040-284C41-284C42 DTRA, DTRB. Data Terminal Ready (Outputs, Ac- tive Low). These outputs follow the state pro- grammed into Z80C SIO. They can also be programmed as general-purpose outputs. Inthe Z80C SIO-1 bonding option, DTRB is omitted. IEL. Interrupt Enable in (Input, Active High). This sig- nal is used with IEO to form a priority daisy-chain when there is more than one interrupt-driven device. A High on this line indicates that no other device of higher priority is being serviced by a CPU interrupt service routine. IEO. interrupt Enable Out (Output, Active High). [EO is High only if IEl is High and the CPU is not servic- ing an interrupt from this SIO. Thus, this signal blocks lower priority devices form interrupting while a higher priority device is being serviced by its CPU interrupt service routine. INT. interrupt Request (Output, Open Drain, Active Low). When the SIO is requesting an interrupt, it pulls INT Low. lORQ. /nput/Output Request (Input from CPU, Ac- tive Low). IORQis used in conjunction with B/A, C/D, CE and RD to transfer commands and data between the CPU and the SIO. When CE, RD and IORQ are all active, the channel selected by B/A transfers data to the CPU (a read operation). When CE and IORQ are active but RD is inactive, the channel selected by B/A is written to by the CPU with either data or ~-+] o, . ~+] 0, Asch | -- +], Ta PR CPU} +1, r4C8 | =_. DATA _. Bus ~-~slTY, SYNC [~_~ +] 2, waa P_> CHANNEL A +], +] 5, aTsa - crs |~ | mopem ptra P}-_+ / CONTROL ] ce OTOA |~-__ +| restr Ze4Cat e] + COMTROL | +] s0%6 #66 |--_\ FROM ab cpu) ee 1108 P - = 1c [--__ -+] cin SYNca Po - winove - +] aa CHANNEL & _ a1s8 f Daisy { +fiat - MODEM CHAIN vet c1s6 |" __} contRon INTERRUPT ots |> Contmo, | ~] 0 i tt Veo GND ocx 57 S&S:THOMSON MIGREELECTES: 3/24 Cs 95284C40-Z84C41-284C42 Figure 4 : Z80C SIO-1 Dual in Line Pin Configuration. oO, 3 J 9 J 0, H] T] o, Ty ion aka [] sa co ry AG [] GND Cy] wirdve [] syaca Os o; int tet 10 Mi Voc WIRDYA | SYNCA RaDA oe Hy me em wn a RaCA THCA TaDA GTRA ATSA CTSA DCOA CLK control information as specified by C/D. If |ORQ and M1 are active simultaneously, the CPU is acknow- ledging an interrupt and the SIO automatically places its interrupt vector on the CPU data bus if it Figure 5 : ZCC SIO-0 Logic Functions. is the highest priority device requesting an interrupt. M1. Machine Cycle (Input from Z80C CPU, Active Low). When M1 is active and RD is also active, the Z80C CPU is fetching an instruction from memory ; when M1 is active while IORQ is active, the SIO ac- cepts M1 and IORQ as an interrupt acknowledge if the SIO is the highest priority device that has inter- rupted the Z80C CPU. RxCA, RxCB. Receiver Clocks (Inputs), Receive data is sampled on the rising edge of RxC. The Re- ceive Clocks may be 1, 16, 32 or 64 times the data rate in asynchronous modes. These clocks may be driven by the Z80C CTC Counter Timer Circuit for programmable baud rate generation. Both inputs are Schmitt-trigger buffered (no noise level margin is specified). In the Z80C SiO-0 bonding option, RxCB is bonded together with TxCB. RD. Read_Cycle Status (Input from CPU, Active Low). If RD is active, a memory or I/O read _oper- ation is in progress. RD is used with B/A, CE and IORQ to transfer data from the SIO to the CPU. RxDA, RxDB. Receive Data (Inputs, Active High). Serial data at TTL levels. RESET. Reset (Input, Active Low). A Low RESET disables both receivers and transmitters, forces TxDA and TxDB marking, forces the modem con- +] Dy RxDA 1 Dy RECA be. | Dy TDA | ~ cpeu | . to, TA Le DATA, lo, SYNCA fem BUS | .+| 0, WihovA} ~ CHANNEL A ~] Dg __ +] RISA f-~ CTSA f= | movem ZB4C40 BTA - ) sce w] CE BCDA be +] Reser | wr RxDB f= CONTROL} +1 10RQ PxTxCB P- FROM +] RD DB /-- cpu SYNCB Je +] cp WRDYS- | wa CHANNEL B RTsa f|~ DAISY ~J wt Cisse [.# _ MODEM nea =| OTR Pn CONTROL contro, \_*__ DCOB [* Yog GND CLK wet G57 SS:THoMson 96 MICROELESTROMICSFigure 6 : Z80C SIO-0 Dual in Line Pin Configuration. ot wof}o, o,(]2 wo, eo, (2 wPJo, ot} Do, wi(]s [J ona iC]s w[ C& no]? 4D oA wits aD os Yeo C8 a2} a6 wihova ] 10 31D ono svica i 284640 =F crave #epa [] 12 20D) svncea fics 2 af} mon fata (J a ar [Matec weda (] 9 26} tebe oma (] aD) Orne asa C] 7 aL) arse cisa (] aa) cise Btoa (] 9 227) Ochs cu CF) 20 au (D Neser 19 WM 2 22:21:26 25 2627 i ie pe ee aoe G EGER 2BEEEE * me I fe IG NC = No Connection. trols High and disables all interrupts. The control registers must be rewritten after the SIO is reset and before data is transmitted or received. RTSA, RTSB. Request To Send (Outputs, Active Low). When the RTS_bit in Write register 5 (figure 14) is set, the RTS output goes Low. When the RTS bit is reset in the Asynchronous mode, the output goes High after the transmitter is empty. In Synchronous modes, the RTS pin strictly follows the state of the RTS bit. Both pins can be used as general-purpose outputs. SYNCA, SYNCB. Synchronization (\nputs/Outputs, A391 Sinomscmones Z84C40-Z84C41-284C42 Active Low). These pins can act either as inputs or outputs. In the asynchronous receive mode, they are inputs similar to CTS and DCD. In this mode, the transitions on these lines affect the state of the Sync/Hunt status bits in Read Register 0 (figure 14), but have no other function. In the External Sync mode, these lines also act as inputs. When external synchronization is achieved, SYNC _must be driven Low on the second rising edge of RxC after that ris- ing edge of RxC on which the last bit of the sync character was received. In other words, after the sync pattern is detected, the external logic must wait for two full Receive Clock cycles to activate the SYNC input. Once SYNC is forced Low, it should be kept Low until the CPU informs the external syn- chronization detect logic that synchronization has been lost or a new message is about to start. Char- acter assembly begins on the rising edge of RxC that immediately precedes the falling edge of SYNC in the External Sync mode. In the internal synchronization mode (Monosync and Bisync) these pins act as outputs that are ac- tive during the part of the receive clock (RxC) cycle in which syne characters are recognized. The sync condition is not latched so these outputs are active each time a sync pattern in recognized, regardless of character boundaries. in the Z80C SIlO-2 bonding option, SYNCB is omitted. TxCA, TxCB. Transmitter Clocks (Inputs). In asyn- chronous modes, the Transmitter Clocks may be 1, 16, 32 or 64 times the data rate ; however, the clock multiplier for the transmitted and the receiver must be the same. The transmit Clock inputs are Schmitt- trigger buffered for relaxed rise- and fall-time re- quirements (no noise level margin is specified). Transmitter Clocks may be driven by the Z80C CTC Counter Timer Circuit for programmable baud rate generation. In the Z80C SIO-0_bonding option, TxCB is bonded together with RxCB. TxDA, TxDB. Transmitt Data (Outputs, Active High). Serial data at TTL levels. TxD changes from the falling edge of TxC. W/RDYA, W/RDYB. Wait/Ready A, Wait/Ready B (Outputs, Open Drain when Programmed for Wait Function, Driven High and Low when Programmed for Ready Function). These dual-purpose outputs may be programmed as Ready lines for a DMA con- troller or as Wait lines that synchronize the CPU to the SIO data rate. The reset state is open drain. 97Z84C40-284C41-Z84C42 Figure 8 : Block Diagram. |} _- } SERIAL DATA ~ } CHANNEL CLOCKS INTERNAL CONTROL CHANNEL A CONTAOL ano CHANNEL A jw = 88SYNC p WAITIREADY cry aus HO Locic STATUS REGISTERS CHANNEL & CONTROL ~- | MOOEM OR AND p= { OTHER CONTROLS syatus >a INTERNAL SUS CHANNEL B CONTROL je | MODEM OR aND a OTHER CONTAQLS STATUS _o INTERRUPT *-d INTERRUPT CONTROL ~e LIMES = CHANNEL & CONTROL aND Status REGISTERS je | SERIAL DATA { CHANNEL CLOCKS GHAANEL _ jv jw = SYNC WAitREAOY FUNCTIONAL DESCRIPTION The functional capabilities of the Z80C SIO can be described from two different points of view : as a data communication device, it transmits and re- ceives serial data in a wide variety of data-communi- cation protocols ; as a Z80C family peripheral, it interacts with the Z80C CPU and other peripheral circuits, sharing the data, address and control buses, as weil as being a part of the Z80C interrupt structure. As a peripheral to other microprocessors, the SIO offers valuable features such as non-vec- tored interrupts, polling and simple handshake ca- pability. Figure 9 illustrates the conventional devices that the SIO replaces. The first part of the following discussion covers SIO data-communication capabilities ; the second part de- scribes interactions between the CPU and the SIO. Figure 9 : Conventional Devices Replaced by Z80C SIO. UART CHANNEL a 1 CONTROLLER MICROPROCESSOR INTERHUPE INTERFACE 7] contaciien AL uaAT CHANMEL Le SYNCHRONOUS COMMUNICATION CONTAOLLER : - CHANNEL MICROPROCESSOR zc Poo A INTERFACE oe! a0 --_ CHANNEL e a Sie4 Gy SGS-THomMson 7 micnomsctromies 98284C40-284C41-284C42 DATA COMMUNICATION CAPABILITIES The SIO provides two independent full-duplex chan- nets that can be programmed for use in any common asynchronous or synchronous data-communication protocol. Figure 10 illustrates some of these proto- cols. The following is a short description of them. A more detailed explanation of these modes can be found in the Z80 Family Technical Manual. ASYNCHRONOUS MODES Transmission and reception can be done inde- pendently on each channel with five to eight bits per character, plus optional even or odd parity. The transmitters can supply one, one-and-a-half or two stop bits per character and.can provide a break out- put at any time. The receiver break-detection logic interrupts the CPU both at the start and end of a re- ceived break. Reception is protected from spikes by a transient spikerejection mechanism that checks the signal one-half a bit time after a Low level is de- tected on the receive data input (RxDA or RxDB in figure 6). If the Low does not persist as in the case of a transient the character assembly process is not started. Framing errors and overrun errors are detected and buffered together with the partial character on which they occurred. Vectored interrupts allow fast servic- ing of error conditions using dedicated routines. Fur- thermore, a built-in checking process avoids interpreting a framing error as a new start bit : a fram- ing error results in the addition of one-half a bit time to the point at which the search for the next start bit is begun. The SIO does not require symmetric transmit and receive clock signals a feature that allows it to be used with a Z80C CTC or many other clock sour- ces. The transitter and receiver can handle data at a rate of 1, 1/16, 1/32 or 1/64 of the clock rate sup- plied to the receive and transmit clock inputs. In asynchronous modes, the SYNC pin may be pro- grammed as an input that can be used for functions such as monitoring a ring indicator. SYNCHRONOUS MODES The SIO supports both byte-oriented and bit oriented synchronous communication. Synchronous byte-oriented protocols can be handled in several modes that allow character syn- chronization with an 8-bit syne character (Mono- sync), any 16-bit sync pattern (Bysinc), or with an external sync signal. Leading sync characters can be removed without interrupting the CPU. Five-, six- or seven-bit sync characters are detected with 8- or 16-bit patterns in the SIO by overlapping L971 Sezoltscmones the larger pattern across muttiple in-coming sync characters, as shown in figure 11. CRC checking for synchronous byte-oriented modes is delayed by one character time so the CPU may disable CRC checking on specific characters. This permits implementation of protocols such as IBM Bisync. Both CRC-16 (x6 + x'5 + x? + 1) and CCITT (x' +X' + X + 1) error checking polynomials are sup- ported. In all non-SDLC modes, the CRC generator is initialized to 0s ; in SDLC modes, it is initialized to 1's. The SIO can be used for interfacing to periph- erals such as hard-sectored floppy disk, but it can- not generate or check CRC for IBM-compatible soft-sectored disks. The SIO also provides a feature that automatically transmits CRC data when no other data is available for transmissions. This allows very high-speed transmissions under DMA control with no need for CPU intervention at the end of a message. When there is no data or CRC to send in synchronous modes, the transmitter inserts 8- or 16-bit sync characters regardless of the pro- grammed character length. The SIO supports synchronous bit-oriented proto- - cols such as SDLC and HDLC by performing auto- matic flag seding, zero insertion and CRC generation. A special command can be used to abort a frame in transmission. At the end of a mess- age the SIO automatically transmits the CRC and trailing flag when the transmit buffer becomes empty. If a transmit underrun occurs in the middle of a message, an extemal/status interrupt warns the CPU of this status change so that an abort may be issued. One to eight bits per character can be sent, which allows reception of a message with no prior information about the character structure in the in- formation field of a frame. The receiver automatically synchronizes on the leading flag of a frame in SDLC or HDLC, and pro- vides a synchronization signal on the SYNC pin ; an interrupt can also be programmed. The receiver can be programmed to search for frames addressed by a single byte to only a specified user-selected ad- dress or to a global broadcast address. In this mode, frames that do not match either the user-selected or broadcast address are ignored. The number of ad- dress bytes can be extended under software con- trol. For transmitting data, an interrupt on the first received character or on every character can be se- lected. The receiver automatically deletes all zeroes inserted by the transmitter during character assem- bly. It also calculates and automatically checks the CRC to validate frame transmission. At the end of 7124 99Z84C40-Z84C41-Z84642 transmission, the status of a received frame is avail- able in the status registers. The SIO can be conveniently used under DMA con- trol to provide high-speed reception or transmission. In reception, for example, the SIO can interrupt the CPU when the first character of a message is re- Figure 10 : Some Z80C SIO Protocols. ceived. The CPU then enables the DMA to transfer _ the message to memory. The SIO then issues an end-of-frame interrupt and the CPU can check the status of the received message. Thus, the CPU is freed for other service while the message is being received. PARITY START STOP ASYNCHRONOUS | sync | DATA | ** [cata | crc, | cats ] -" MONOSYNC [ SYNC [ SYNC | DATA | ie | DATA | CRC, ] CRC, | SIONAL BISYNC DATA - DATA crc, [cate EXTERNAL SYNC vO [ frac | avoness | 2 f INFORMATION 4 SOLC/HOLCIX.25 | crc, | cre, [ FLAG | Figure 11 : Six Bit Sync Character Recognition. eoits s ee 1% | SYNC 1 sYNG | SYNC I DATA | DATA | DATA I BATA } 8/24 100 91 Sicsouscteones284C40-Z84C41-284C42 STATUS FLOW-CHART Figure 12a : Status Flowchart. Figure 12b : Status Flowchart. (rower on ) ASYNCHRONOUS MODE TRANSMIT CM =1 CE, (ORQ <0 STATUS RESET #0? RD<0 REACOUT ARO BUFFER EMPTY. ? YES WRITE TRANSMIT TRANSMIT DATA CHARACTER Se fenenen TRANSMIT (TxD} START BIT O DO O1 DN CI =0 CE, 1ORQ=0 RO=1 COMMAND WAITE (wRo T WR7} SETT RECEIVE PARITY BIT STOP BIT 1 AUTO ENABLE? | EXTERNAL/STATUS INTERRUPT res 4A . TRANSMIT ENABLE FRAME TRANSMIT END ASYNCHRONOUS MODE TRANSMIT YES SYNCRONOUS MODE TRANSMIT Yes EXTERNAL SOLC TRANSMIT SYNCHRONOUS 5-8605 TRANSMIT Ky7 Sopomsereones vorZ84C40-284C41-Z84C42 Figure 12c : Status Change Flowchart. SOLC TRANSMIT TxD TERMINAL _. OPEN FLAG OPEN FLAG TxC INPUT | CHARACTER (7EH) F ~ 71 CHARACTER (7EH) TRANSFER CE. 104520 | STATUS READOUT RD LO ARO BUFFER EMPTY ? YES 1, ADDRESS WRITE 2, TRANSMIT DATA WAITE TRANSMIT INTERRUPTION 1. ADDRESS (00-07) | 2. TRANSMIT DATA (D0-D7} TRANSMIT (T x D) TRANSMIT UNDERRUN EOM YES |< fC TRANSFER b- 4 CRC (00-015) | YES CLOSE FLAG = ~] CLOSE FLAG TRANSFER TRANSMIT ER) FRAME TRANSMIT END 1ore4 G7 S&8;THoMsoN 102Figure 12d : Status Change Flowchart. 284C40-Z84C41-Z84C42 Txt INPUT CiD=1 CE, (ORO =0 RD=0 SYNCRONOUS MODE TRANSMIT. TxD TERMINAL SYNCHRONOUS CHARACTER TRANSFER (T x D) fb SYNCH 1 (00-07) SYNCH 2 (00-07) STATUS REACOUT RRO BUFFER EMPTY ? YES TRANSMIT DATA CHARACTER WRITE TRANSMIT END cRCc ADDITION 7 YES NO TRANSMIT INTERRUPTION 1 TRANSMIT ( {TxD) } 7 | CRC TRANSFER t-+ CRC (00-015) | cre TRANSFER END ? ves SYNCHRONOUS | SYNCH + (00-07) CHARACTER TRANSFER SYNCH 2 (00-D7) FRAME TRANSMIT END 11/24 37 SSaonsermones 103284C40-284C41-284C42 Figure 12e : Status Flowchart. CEE) Gee) ERROR SPECIAL RECEIVE INTERRUPTION 4a : i i i je Commmecet) retin) Curren) Gummemen) Cooormury 12/24 104 L97 Risoutcrmones1/0 INTERFACE CAPABILITIES The SIO offers the choice of poiling, interrupt, (vec- tored or non-vectored) and block-transfers modes to transfer data, status and contro! information to and from the CPU. The block-transfer mode can also be implemented under DMA control. POLLING Two status registers are updated at appropriate times for each function being performed (for example, CRC error-status valid at the end of a message). When the CPU is operated in a polling fashion, one of the SIOs two status registers is used to indicate whether the SIO has some data or needs some data. Depending on the contents of this register, the CPU will either write data, read data, or just go on. Two bits in the register indicate that a data transfer is needed. In addition, error and othet conditions are indicate. The second status register (special receive conditions) does not have to be read in a_ polling sequence, until a character has been received. All interrupt modes are disabled when operating the de- vice in a polled environment. INTERRUPTS The SIO has an elaborate interrupt scheme to provide fast interrupt service in real-time applica- tions. A control register and a status register in Channel B contain the interrupt vector. When pro- grammed to do so, the SIO can modify three bits of the interrupt vector in the status register so that it points directly to one of eight interrupt service rou- tines in memory, thereby servicing conditions in both channels and eliminating most of the needs for a Status-analysis routine. Transmitt interrupts, receive interrupts and exter- nal/status interrupts are the main-sources of inter- rupts. Each interrupt source is enabled under program control, with Channel A having a higher priority than Channel B, and with receive, transmit and extemal/status interrupts prioritized in that order within each channel. When the transmit interrupt is enabled, the CPU is interrupted by the transmit buff- er becoming empty. (This implies that the transmit- ter must have had a data character written into it so itcan become empty). The receiver can interrupt the CPU in one or two ways : a Interrupt on first received character a Interrupt on all received characters Interrupt-on-first-received-character is typically used with the block-transfer mode. interrupt-on-all- received-characters has the option of modifying the interrupt vector in the event of a parity error. Both of Lyf Serouscrones 284C40- 41-284C42 these interrupt modes will also interrupt under spe- cial receive conditions on a character or message basis (end-of-frame interrupt in SDLC, for example). This means that the special-receive condition can cause an interrupt only if the interrupt-on-first-re- celved-character or interrupt-on-all-received-charac- ters mode is selected. in interrupt-on-first-received- character, an interrupt can occur from special-receive conditions (exceot parity error) after the first-received- character interrupt (example : receive-overrun inter- rupt). The main function of the extemai/status interrupt is to. monitor the signal transitions of the Clear To Send (CTS), Data Carrier Detect (DCD) and Synchroni- zation (SYNC) pins (figures 1 through 6). In addi- tion, an extemal/status interrupt is also caused by a CRC-sending condition or by the detection of a break sequence (asynchronous mode) or abort se- quence (SDLC mode) in the data stream. The interrupt caused by the break/abort sequence allows the SIO to interrupt when the break/abort se- quence is detected or terminated. This feature facili- tates the proper temination of the current message, Figure 13 : Typical Z80C Environment. SYSTEM Busts cpu DMA int int aor te +3 vi zero, cre zZCiTO, int -}. 180 _ 10 wCA ONT int TCA 10 ! et nce te waeora - winove |} +| nov s10 oma 19/24 105Z84C40-284C41-284C42 correct initialization of the next message, and the accurate timing of the break/abort condition in ex- ternal logic. In a Z80C CPU environment (figure 13), SiO inter- rupt vectoring is "automatic" : the SIO passes its in- ternally-modificable 8-bit interrupt vector to the CPU, which adds an additional 8 bits from its inter- rupt-vector (I) register to from the memory address of the interrupt-routine table. This table contains the address of the beginning of the interrupt routine it- self. The process entails an indirect transfer or CPU control to the interrupt routine, so that the next in- struction executed after an interrupt acknowledge by the CPU is the first instruction of the interrupt rou- tine itself. CPU/DMA BLOCK TRANSFER The SIOs block-transfer mode accommodates both CPU block transfers and DMA controllers (Z80C DMA or other designs). The block-transfer mode uses the Wailt/Ready output signal, which is se- lected with three bits in an Internal control register. The Wait/Ready output signal can be programmed as a WAIT line in the CPU block-transfer mode or as a READY line in the DMA bliock-transfer mode. To a DMA controller, the SHO READY output indi- cates that the SIO is ready to transfer data to or from memory. To the CPU, the WAIT output indicates the SIO is not ready to transfer data, thereby request- ing the CPU to extend the I/O cycle. INTERNAL STRUCTURE The internal structure of the device includes a Z80C CPU interface, internal control and interrupt logic, and two full-duplex channels. Each channel contains its own set of control and status (write and read) registers, and control and status logic that provides the interface to modems or other external devices. The registers for each channel are designated as follows : WRO-WR7 - Write Registers 0 through 7 RRO-RR2 - Read Register 0 through 2 The register group includes five 8-bit control regis- ters, two sync-character registers and two status registers. The interrupt vector is written into an ad- ditional 8-bit register (Write Register 2) in Chan- nelB that may be read through another 8-bit register (Read Register 2) in Channel B. The bit assignment and functional grouping of each register is con- figured to simplify and organize the programming THOMSON HICHORLECTRONICS 106 process. Table / list the functions assigned to each read or write register. The logic for both channels provides formats, syn- chronization and validation for data transferred to and from the channel interface. The modem contro! inputs, Clear To Send (CTS) and Data Carrier De- tect (DCD), are monitored by the external control and status logic under program control. All external control-and-status-logic signals are general-pur- pose in nature and can be used for functions other than modem control. DATA PATH . The transmit and receive data path illustrated for Channel A in figure 13 is identical for both channels. The receiver has three 8-bit buffer registers in a FIFO arrangement, in addition to the 8-bit receive shift register. This scheme creates additional time for the CPU to service an interrupt at the beginning of a block of Reed Register Functions RRO Transmit/Receive Buffer Status, Interrupt Status and External Status RAI Special Receive Condition Status RR2 Modified Interrupt Vector (channel B only) Write Register Functions WRO | Register pointers, CRC initialize, initialization commands for the various modes, etc. . WRi Transmit/Receive Interrupt and Data Transfer Mode Definition WR2 Interrupt Vector (channel B only) WR3 Receive Parameters and Control WR4 Transmit/Receive Miscellaneous Parameters and Modes : WR5 Transmit Parameters and Controls WR6 Sync Character or SDLC Address Field WR7 Sync Character or SDLC Flag high-speed data. Incoming data is routed through one of several paths (data or CRC) depending on the selected mode andin asynchronous modesthe character length. , The transmitter has an 8-bit transmit data buffer reg- ister that is loaded from the internal data bus, and a 20-bit transmit shift register that can be loaded from the sync-character buffers or from the transmit data register. Depending on the operational mode, outgoing data is routed throught one of four main paths before it is transmitted from the Transmit Data output TxD).284C40-264C41-Z84C42 Figure 14 : Transmitt and Receive Data Path (channel A). cru a TO CHANNEL 5, EXTEAMAL STATUS LOGIC, INTERNAL DATA BUS CONTROL LOGIC, ETC. 1 wai wes RECEIVE RECEIVE SYNC REGISTER SYNC REGISTER TAANGIIT DATA b--4 ----+ GATA ERROR Fira FO v I 20-81T TRANSMIT SHIFT MEGISTER 1 staat | ABYNC sNC A DATA DATA TRANSMET TDA AECEIVE oe MUCTIPLERER bo NCA uocr EAROR ak & 2817 BELAY Logic HUNT MODE (SYNC) Losi ~NUNT MODE f seve cac i 4 soLc-cre RECEIVE Lang SYNC REGISTER BTS be] sHiFr REGISTER aA > LAY ZERO DELETE TRANSAT = | cetion | BLOC pee . { { SYNC. ASYNG DATA cnc CAC DELAY REGISTER 0 pire) cac CHECKER = [crc mEsULT SOLS CAC The system program first issues a series of com- mands that initialize the basic mode of operation and then other commands that qualify conditions within the selected mode. For example, the asyn- chronous mode, character length, clock rate, num- ber of stop bits, even or odd parity might be set first ; then the interrupt mode ; and finally, receiver or transmitter enable. Both channels contain registers that must be pro- grammed via the system program prior operation. The channel-select input (B/A) and the control/data input (C/D) are the command-structure addressing controls, and are normally controlled by the CPU ad- dress bus. Figures 17 and 18 illustrate the timing re- lationships for programming the write registers and transfering data and status. READ REGISTER The SIO contains three read registers for Chan- L597 Siponsrones nel B and two read registers for Channel A (RRO- RR2 in figure 14) that can be to obtain the status information ; RR2 contains the internally-modifi- able interrupt vector and is only in the Channel B register set. The status information includes error conditions, interrupt vector and standard com- munications-interface signals. To read the contents of a selected read register other than RRO, the system program must first write the pointer byte to WRO in exactly the same way as awrite register operation. Then, by executing a read instruction, the contents of the addressed read reg- ister can be read by the CPU. The status bits of RRO and RR1 are carefully grouped to simplify status monitoring. For example, when the interrupt vector indicates that a Special Receive Condition interrupt has occurred, all the ap- propriate error bits can be read form a single regis- ter (RRI). . 15/24 107Z84040-Z84C41-Z84C42 WRITE REGISTERS The SIO contains eight write registers for Chan- nei B and seven write registers for Channel A (WRO- WR7 in figure 15) that are programmed separately to configure the functional personality of the chan- nels ; WR2 contains the interrupt vector for both channels and is only in the Channel B register set. With the exception of WRO, programming the write registers requires two bytes. The first byte is to WRO and contains three bits (Do-Dz) that point to the se- Figure 15 : Read Register Bit Functions. lected register ; the second byte is the actual con- trol word that is written into the register to configure the SIO. WRO is a special case in that all of the basic com- mands can be written to it with a single byte. Reset (internal or external) initializes the pointer bits Do-D2 to point to WRO. This implies that a channel reset must not be combined with the pointing to any reg- ister. READ REGISTER 0 [er [es] ] 0} 0402] | | E READ REGISTER It 1 FIELD SiTS 94400250 @s4+-000 Nm OOOO PARITY EAROR a OVERRUN ERROR GACIFRAMING ERROR END OF FRAME (SOLC) tses With Specuat Peceve Conaiics Mode 1Varapie it Status Altects Vector 1s Programmed Ra CHARACTER AVAILABLE INT PENDING (CH. A ONLY) Ta GUFFER EMPTY o SYNC/HUNT crs Tx UNDERRUNIEOM BREAK/ABORT "Used With ExiernauSiakes interrupt Mode L_ ALL SENT IN PREVIOUS SECOND PREVIOUS BYTE BYTE \ 1 FIELD RITS IN eeanaven Rescue Data For Eagh Rs ausiCnasacter Programmed INTERAUPT VECTOR 16/24 108Figure 16 : Write Register Bit Functions. 284040-Z84C41-Z84C42 ~=e0 =~On0 owen oage MOO Mae WRITE REGISTER 0 REGISTER REGISTER 1 REGISTER 2 REGISTER 3 REGISTER 4 REGISTER 5S WECISTER 6 REGISTER T wae ance = 80-400 =o4Q4Oong NULL CODE SENO ABORT (SOLC) RESET EXTISTATUS INTERAUPTS CHANNEL RESET ENABLE INY OW NEXT Rx CHARACTER RESET Ts WIT PENDING RESET RETURN FROM INT (CH-A ONLY) NULL CODE RESET Re CAC CHECKER RESET Tz CRC GENERATOR RESET Tx UNDERRUNIEOM LATCH =-eo | WRITE REGISTER | F | EXT INT ENABLE Tx INT EWABLE STATUS AFFECTS VECTOR ICH. B ONLY) Re nT DISABLE Wa INT ON FIART CHARACTER INT ON ALL Ax CHARACTERS (PARITY AFFECTS VECTOR) 5. vec ON Att Rx CHARACTERS (PARITY DOES NOT AFFECT CIOR) WAITNEADY ON FUT Or On WAITREADY FUNCTION Speciat WAITIREADY ENABLE Conaition : WRITE REGISTER 2 (CHANNEL B ONLY) vi va \ wreravet va (VECTOR vs ve * Vv? WRITE REGISTER 3 | Law ENABLE SYNC CHARACTEA LOAO INHIBIT ApDnene, SEARCH MODE (SOLC) PHASE Rs -5 BITSPCHARACTER Ra ? BMITSCHARACTER As 6 BITSICHARACTER Ha 8 tT SPCHARACTER WRITE REGISTER 4 [81 [ | 05 [<j Dy] 02 50s [Os | | | | parity enasce PARITY EVEWODD 0 t 1 SYNC MODES ENABLE 1 STOP BITICHARACTER 1% STOP BITSACHARACTER 2 STOP BITSICHARACTER @ 4 BIT SYNC CHARACTER 16 BIT SYNC CHARACTER G SOLC MODE 1119919 FLAG} 1 EXTERNAL SYNC MODE ~ e 6 1 1 3X1 CLOCK MODE X18 CLOCK MODE %32 CLOCK MODE X04 CLOCK MODE WRITE REGISTER $ [o;] [05 [0.] 0, ]o, |, [0] | | L__ ts crc enasee | | | Ans SOLCICRC.-18 Tx ENABLE SEND BREAK a Ta 5 BITS (OR LESSHCHARACTER Ta 7 AYSIGHARACTER | 3 6 BF Ta 8 BITSICRARACTER --ee ~e-~ WRITE REGISTER 6 *Alto SOLC Aadats Frei WRITE REGISTER 7 Lr} Be] Ps |. [2 [ Or] Ds | Be) *For SDRC Ii Musi Ge Progeamnied fo 00518010 For Fay Recoynton 17/24 Lyf Siponsreones 109284C40-Z84041-284C42 TIMING _ The SfO must have the same clock as the CPU (same phase and frequency relationship, not necessarily the same driver). READ CYCLE The timing signals generated by a Z80C CPU input instruction to read a data or status byte from the SIO are illustrated in figure 16. WRITE CYCLE Figure 16 illustrates the timing and data signals generated by a Z80C CPU output instruction to write a data or control byte into the SIO. INTERRUPT-ACKNOWLEDGE CYCLE After receiving an interrupt-request signal from an SIO (INT pulled Low), the Z80C CPU sends an in- terrupt-acknowledge sequence (M1 Low, and |ORQ Low a few cycles later) as in figure 18. The $lO contains an internal daisy-chained interrupt structure for prioritizing nested interrupts for the vari- ous functions of its two channels, and this structure can be used within an external user-defined daisy chain that prioritizes several peripheral circuits. The IEI of the highest-priority device is terminated High. A device that has an interrupt pending or under service forces its IEO Low. For devices with no interrupt pending or under service, IEO = IEI. To insure stable conditions in the daisy chain, all in- terrupt status signals are prevented from changing while M1 is Low. When IORQ is Low, the highest priority interrupt requestor (the one with |EI High) Figure 17 : Read Cycle. places its interrupt vector on the data bus and sets its internal interrupt-under-service latch. RETURN FROM INTERRUPT CYCLE Figure 19 illustrates the return form interrupt cycle. Normally, the Z80C CPU issues a RETI (Return From interrupt) instruction at the end of an interrupt sevice routine. RET| is a 2-byte opcode (ED-4D) that resets the interrupt-under-service latch in the SIO to terminate the interrupt that has just been processed. This is accomplished by manipulating the daisy chain in the following way. The normal daisy-chain operation can be used to detect a pending interrupt ; however, it cannot dis- tinguish between an interrupt-under service and a pending unacknowledged interrupt of a higher priority. Whenever "ED" is decoded, the daisy chain is modified by forcing High the IEO of any interrupt that has not yetbeen acknowledged. Thus the daisy chain identifies the device presently under service as the only one with an IEI High and an IEO Low. If the next opcode byte is "4D", the interrupt-under- service latch is reset. The ripple time of the interrupt daisy chain (both the High-to-Low and the Low-to-High transitions) limits the number of devices that can be placed in the daisy chain. Ripple time can be improved with carry- look-ahead, or by extending the interrupt-acknow- ledge cycle. For further information about techniques for increas- ing the number of daisy-chained devices, refer to the Z80C CPU Data Sheet. Figure 18 : Write Cycle. cLocK CE, crD, WA h Te Tw Wy ty cLocK are aa cme ! w oe Ty mi DATA wae } DATA Xx 18/24 ky7 $63-THOMsoN 110284C40-284C41-284C42 Figure 19 : Interrupt Acknowledge Cycle. Figure 20 : Return from Interrupt Cycle. aD DoD, (co } { wo) I w T7TTTTTT Too P| eee es ee ee es ee ee I _ ee JEL DATA VECTOR j= Figure 21 : Daisy chain at RETI Instruction. [1] Status where SIOs Request Interruption. yw it 1 1" t INT oO tT {__}-{ eo} {__} {30 }-{__] TEI [EO 1EI 1EO IE! IEO IEI IEO {El IEO [2] $1Os are under Interruption Service yr y" or Te} $30} [3] Status where PIO has requested interruption immediately before SIOs decode ED. By the request of PIO for interruption IEO of PIO becomes 0". sye we I" t INT or o" oO PIO SIO {4} As EDH has been decoded, the interruption request of PIO is not acknowledged. Therefore, IEO of PIO returns to 1. ant - ww tH} no} -{_+4YE 0 }+- [J [5] As 4DH" has been decoded, IEO of SiOs becomes 1. ye yo ye y yr (6} Interruption request by PIO is acknowledged, and the IEO of PIO becomes 0. ope ye gr 9 gr io} -Ls_}- t{__} {#6} -{__} 0 } +] 19/24 A357 Sesouncnanes 111284C40-Z84C41-Z84C42 ABSOLUTE MAXIMUM RATINGS Parameter Voc Voc with to Vss Vin Pp Power a = 85 TsoLven time 10 T. T CAPACITANCE (T, = 25C) Parameter CoLock | Clock Cin Cour Value ~ 0.5 to 7 0.5 to Veco + 0.5 250 260 - 65 to 150 40 to 85 Test Condition f = 1MHz DC CHARACTERISTICS (T, =- 40 T to 85 C, Vog = 5 V4 10 %, Veg =0 Vv) Symbol! Parameter Test Conditions Min. Typ. Max. Unit Vitc Clock Input Low Voltage ~ 0.3 - 0.6 Vv Vine Clock Input High Voltage Voo-0.6] - |Vec+031 V Vit Input Low Voltage -0.5 - 0.8 (except CLK) Vin Input High Voltage 2.2 - Voc Vv (except CLK) VoL Output Low Voltage lo. =2.0 mA - - 0.4 Vv Vout Output High Voltage (1) low =- 1.6 mA 2.4 - - Vv Voue Output High Voltage (2) lon = 250 pA Veco- 0.8) - - Vv lu Input Leakage Current Vss $ Vin $ Voc - - +10 pA lLo 3-State Output Leakage Vss + 0.4 < Vout S$ Veco - - +10 pA Current In Float lLisyy SYNC Pin Leakage Current Vss + 0.4 $ Vout S$ Vec - 40 - 10 HA Voc =5 V, CLK =4 MHz lees Operating Supply Current : Vin = Vinc = Veco - 0.2 V 4 MHz Vit = Vic = 0.2 V - 2.5 6 mA 6 MHz Voc =5 V, {CLK = To C(min) - 4 10 mA Ioce Stand-by Supply Current Vin = Voc - 0.2 V - - 10 pA (except SYNC pin) CLK = Vy =0.2 V, Voc = 5 V TEST CONDITIONS Ta= 40C to+85'C Veco =5V+10% Vss =0V AC TEST CONDITIONS a Inputs except CLK (clock) are driven at 2.4 V for a logic "1" and 0.4 V for a logic "0". Clock input is 20/24 112 A397 Seonscreones driven at Voc 0.6 V for a logic "1" and 0.6 V for a logic "0". = Timing measurements are made at 2.2 V fora logic "1" and 0.8 V for a logic "0". All AC parameters assume a load capacitance of 100 pFZ84C40-284C41-284C42 AC CHARACTERISTICS 2 oF . & un " PL FAS 3 5 +B) Hlcs? .ciB, 8/4, ORG } we, kOO+Le L-) bo DATA (Dg - D9) - foro F + 2) al \ / @+4 Te) i te) 10 \ int (8) @ WiRoy 57 S&8;THOMSoN ene4 113Z84C40-Z84041-284C42 AC CHARACTERISTICS (continued) 284040 |.z84C40 (1/2A /1/2B N Symbol Parameter Min. |Max.| Min. |Max. Unit 1 TeC Clock Cycle Time 250 | DC | 165 | DC ns 2 TwCh Clock Width (high) 105 | DC | 70 | DC ns 3 TiC Clock Fall Time 30 15 ns 4 Trc Clock Rise Time 30 15 ns 5 TwCl Clock Width (low) 105 | DC | 70 | OC ns 6 | TsCS(C) | CE, C/D, B/A, IORQ to Clock T Setup Time 145 60 ns 7 | TsRO(C) | RD to Clock T Setup Time 115 60 ns 8 TdC(D0) Clock T to Data Out Delay 220 150 ns 9 TsDI(C) Data In to Clock T Setup (write or M! Cycle) 50 30 ns 10 | TdRD(DO2) | RD T to Data Out Float Delay 110 90 ns 11] Tdlo(Do1) | IORQ | to Data Out Delay (INTACK cycle) 160 120 ns 12] TsMi\G) | M1 to Clock T Setup Time 90 75 ns 13] TslEKIO) IEI to IORQ | Setup Time {INTACK cycle) 140 120 ns 14| TdMI(IEO) M1 J to 1EO 4 Delay (interrupt before M1) 190 160 ns 15*| TdlEI(iEOr) | IEl T to IEO T Delay (after ED decode) 160 110 ns 16| TdiEWIEOF) | IEI L to IEO J Delay 100 70 ns 17] TdC(INT) | Clock T to INT 4 Delay 200 150 ns 18 |TdILO(W/RWA)| IORO J or CE J to WRDY J Delay (wait mode) 210 175 ns 19| TdC(WAR) | Clock T to WADY | Delay (ready mode) 120 100 ns. 20 | TdC(W/RWZ) | Clock J to W/RDY Float Delay (wait mode) 130 110 ns 21| Th, Th(CS) | Any unspecified hold when setup is specified. 0 0 ns >" Not compatible with NMOS Specifications. 22/24 114 57 Sieonaemanes284C40-784641-284C42 AC CHARACTERISTICS (continued) -__@-| L CTS.DCD, SYNE \ } t= 84 L - _@-_ wiry \ Pe _ Tht \ RID S557 K57_ 865:THomson eared 1152Z84C40-Z84C41-284C42 AC CHARACTERISTICS (continued) Z84C40 | 284040 wel Symbol p M/2A | 1/28 Unit ymbo arameter Min. |Max.| Min. |Max. " 22 TwPH Pulse Width (high) 200 200 ns 23 TwPI Pulse Width (low) 200 200 ns 24 TeTxc Txc Cycle Time 400 330 ns 25] TwTxel Txe Width (low) 180 | | 100] ns 26| TwTxch | Txe Width (high) 180 | 2 | 100] ns 27 | TdTxC(TxD) TXC J to TxD Delay (X1 mode) 300 220 ns 28 |TdTxC(W/RRN| TXC 4 to W/RDY J Delay (ready mode) 5 {9 |5 1/9 CLK , Periods 28 | TdTxC(INT) | TXC J to INT J Delay 5 [9/51/19 CLK Periods 30] TeRxC Axe Cycle Time 400} | 330| ns 31] TwAxci | Axe Width (low) 180| o | 100] , ns 32| TwRxCh | Rxc Width (high) 180 | - | 100] ns 33 | TsRxD(RxC) | RxD to RxC T Setup Time (x! mode) 0 0 ns 34] ThRxD(RxC) RxC T to RxD Hold Time (xl mode) 140 100 ns 35 ITARxC(W/RRf| RxC T to WRDY J Delay (ready mode) 40 | 13 | 10 | 13 | CLK Periods 36 | TdRxC(INT) | RxC T to INT J Delay 10 | 13 | 10 | 13 CLK Periods 37 |TdRxC(SYNC)| AxC T to SYNC 1 Delay (output modes) 4/7/4117 CLK Periods 38 | TSSYNC(RxC) | SYNC J to Rx@ T Setup (external sync modes) 100 100 ns ORDERING INFORMATION Type Package Temp. Clock Description Z84C40/1/2AB6 | DIP-40 (plastic) 40/+ 85C Z80C Serial (0 Z84C40/1/2AD6 | DIP-40 (ceramic) -40/+ 85C A MHz | Controller Z84C40/1/2AD2 | DiIP-40 (ceramic) ~55/+ 125C ZB4CA4ACE PLCC44 (plastic chip-carrier) 40/+ 85C Z84C40/1/2B86 | DIP-40 (plastic) -40/+ 85C 284C40/1/2BD6 DIP-40 (ceramic) 40/+ 85C 6 MH Z84C40/1/2BD2 | DIP-40 (ceramic) 55/ + 125C 2 Z84C44BC6 PLCC44 (plastic chip-carrier) -40/+ 85C 24/24 S6s-' 57 S-THOMSom 116