DS04-27237-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2005-2006 FUJITSU LIMITED All rights reserved
ASSP for Power Supply Applications
(DC/DC converter for DSC/camcorder)
5 ch DC/DC Converter IC with
Synchronous Rectification
MB39A108
■DESCRIPTION
The MB39A108 is 5-channel DC/DC conver ter IC using pulse width modulation (PWM), and is suitable for up
conversion, down conversion, and up/down conversion. The MB39A108 is built in 5 channels into TSSOP-38P/
BCC-40P package and operates at 2 MHz maximum. Each channel can be controlled with soft-start.
The MB39A108 is suitable for power supply of high performance portable instruments such as DSC.
■FEATURES
• Supports for down-conversion with synchronous rectification (CH1)
• Supports for down-conversion and up/down Zeta conversion (CH2, CH3)
• Supports for up-conversion and up/down Sepic conversion (CH4, CH5)
• Low voltage start-up (CH4, CH5) : 1.7 V
• Power supply voltage range : 2.5 V to 11 V
• Reference voltage : 2.0 V ± 1%
• Error amplifier threshold voltage : 1.00 V ± 1% (CH1), 1.23 V ± 1% (CH2 to CH5)
• Oscillation frequency range : 200 kHz to 2.0 MHz
• Standby current : 0 µA (Typ)
• Built-in soft-start circuit independent of loads
• Built-in totem-pole type output for MOS FET
• Short-circuit detection capability by external signal ( − INS terminal)
• Two types of package (TSSOP-38 pin : 1 type, BCC-40 pin : 1 type)
■APPLICATIONS
• Digital still camera (DSC)
• Digital video camera (DVC)
• Surveillance camera etc.
MB39A108
2
■PIN ASSIGNMENT
(Continued)
(TOP VIEW)
(FPT-38P-M03)
CS2
−INE2
FB2
DTC2
VCC
CTL
CTL3
CTL4
CTL5
−INS
V
REF
RT
CT
GND
C
SCP
DTC3
FB3
−INE3
CS3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CS1
−INE1
FB1
VCCO
OUT1
-1
OUT1
-2
OUT2
OUT3
OUT4
OUT5
GNDO
CS5
−INE5
FB5
DTC5
DTC4
FB4
−INE4
CS4
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
MB39A108
3
(Continued)
<TOP VIEW (Penetration diagram from surface)>
(LCC-40P-M07)
DTC
2
FB2
−INE
2
CS2
NC
CS1
−INE
1
FB1
VCC
O
2
3
4
5
6
7
8
9
10 22
C
SCP
DTC3
FB3
−INE3
CS3
NC
CS4
−INE4
FB4
DTC4
34
18
33
19 20
35 32
14 15 16 1711 12 13
31
21
OUT1
-1
OUT1
-2
OUT2
OUT3
OUT4
OUT5
GNDO
CS5
−INE5
FB5
DTC5
38 37 3614039
VCC
CTL
CTL3
CTL4
CTL5
−INS
V
REF
RT
CT
GND
30
29
28
27
26
25
24
23
MB39A108
4
■PIN DESCRIPTION
(Continued)
Block
Pin No.
Pin name I/O DescriptionPKG
TSSOP BCC
CH1
36 33 FB1 O Error amplifier output terminal.
37 34 − INE1 I Error amplifier inverted input terminal.
38 35 CS1 ⎯Soft-start setting capacitor connection terminal.
34 31 OUT1-1 O P-ch drive output terminal
(External main side FET gate driving).
33 30 OUT1-2 O N-ch drive output terminal
(External synchronous rectification side FET gate driving).
CH2
4 40 DTC2 I Dead time control terminal.
3 39 FB2 O Error amplifier output terminal
238 − INE2 I Error amplifier inverted input terminal.
137CS2⎯Soft-start setting capacitor connection terminal.
32 29 OUT2 O P-ch drive output terminal.
CH3
16 12 DTC3 I Dead time control terminal.
17 13 FB3 O Error amplifier output terminal
18 14 − INE3 I Error amplifier inverted input terminal.
19 15 CS3 ⎯Soft-start setting capacitor connection terminal.
31 28 OUT3 O P-ch drive output terminal.
CH4
23 20 DTC4 I Dead time control terminal.
22 19 FB4 O Error amplifier output terminal.
21 18 − INE4 I Error amplifier inverted input terminal.
20 17 CS4 ⎯Soft-start setting capacitor connection terminal.
30 27 OUT4 O N-ch drive output terminal.
CH5
24 21 DTC5 I Dead time control terminal.
25 22 FB5 O Error amplifier output terminal.
26 23 − INE5 I Error amplifier inverted input terminal.
27 24 CS5 ⎯Soft-start setting capacitor connection terminal.
29 26 OUT5 O N-ch drive output terminal.
OSC 13 9 CT ⎯Triangular wave frequency setting capacitor connection
terminal.
12 8 RT ⎯Triangular wave frequency setting resistor connection terminal.
MB39A108
5
(Continued)
Note : The term inal number which has been described in the te xt is the one of the TSSOP-38P package after this .
Block
Pin No.
Pin name I/O DescriptionPKG
TSSOP BCC
Control
6 2 CTL I Power supply control terminal.
7 3 CTL3 I CH3 control terminal.
8 4 CTL4 I CH4 control terminal.
9 5 CTL5 I CH5 control terminal.
15 11 CSCP ⎯Short-circuit detection circuit capacitor connection terminal.
10 6 − INS I Short-circuit detection comparator inverted input terminal.
Power
35 32 VCCO ⎯Drive output block power supply terminal.
51VCC⎯Power supply terminal.
11 7 VREF O Reference voltage output terminal.
28 25 GNDO ⎯Drive output block ground terminal.
14 10 GND ⎯Ground terminal.
MB39A108
6
■BLOCK DIAGRAM
FB1
−INE2
OUT2
OSC
0.9 V
0.4 V
Power
ON/OFF
CTL
VR
1.23 V
VREF
VCC
bias
2.0 V
CTL
GND
CS2
FB2
DTC2
−INE3
OUT3
CS3
FB3
DTC3
−INE4
OUT4
CS4
FB4
DTC4
1 V
−INE5
CS5
FB5
DTC5
GNDO
OUT5
VREF SCP
Comp.
−INS
CSCP
RT CT VREF
Drive3
Error
Amp3 PWM
<<CH3>>
VREF
UVLO1
Drive5
Error
Amp5 PWM
<<CH5>>
N-ch
VREF
−INE1 VCCO
OUT1-
1
CS1
Error
Amp1
1.0 V
1.23 V
1.23 V
1.23 V
1.23 V
PWM
Comp.1
<<CH1>>
P-ch
VREF
10 µA
10 µA
1 µA
1 µA
1 µA
Io = 130 mA
at VCCO = 4 V
Drive2
Error
Amp2 PWM
<<CH2>>
VREF
Drive4
Error
Amp4 PWM
<<CH4>>
VREF
N-ch
Io = 130 mA
at VCCO = 4 V
Io = 130 mA
at VCCO = 4 V
Io = 130 mA
at VCCO = 4 V
Io = 130 mA
at VCCO = 4 V
SCP
UVLO2
Max Duty
90% ± 5%
Max Duty
90% ± 5%
Max Duty
90% ± 5%
Max Duty
90% ± 5%
N-ch
Io = 130 mA
at VCCO = 4 V
Dead Time
Dead Time
(td = 50 ns)
OUT1-
2
P-ch
P-ch
CH
CTL
CTL3
CTL4
CTL5
2
1
3
4
32
18
19
17
31
21
20
22
30
26
27
25 28
29
5
6
14
10
15
111312
37
38
36
35
34
16
23
24
33
8
9
7
−
+
+
−
+
+
−
+
+
−
+
+
−
+
+
−
+
−
+
+
−
+
+
−
+
+
−
+
+
−
+
Comp.2
Comp.3
Comp.4
Comp.5
VREF
VREF
VREF
VREF
Drive1-1
Drive1-2
100 kΩ
L
priority
L
priority
L
priority
L
priority
L
priority
H: release UVLO
Accuracy
±
0.8%
L
priority
L
priority
L
priority
L
priority
Threshold voltage
1.0 V ± 1%
Threshold voltage
1.23 V ± 1%
Threshold voltage
1.23 V ± 1%
Threshold voltage
1.23 V ± 1%
Threshold voltage
1.23 V ± 1%
H: at SCP
Error Amp power supply
SCP Comp. power supply
Error Amp reference
S
hort-circuit detection signal
(L: at short-circuit)
MB39A108
7
■ABSOLUTE MAXIMUM RATINGS
*1 : When mounted on a 76 mm × 76 mm × 1.6 mm FR-4 boards.
*2 : When mounted on a 117 mm × 84 mm × 0.8 mm FR-4 boards.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Conditions Ratings Unit
Min Max
Power supply voltage VCC VCC, VCCO terminal ⎯12 V
Output current IOOUT1 to OUT5 terminal ⎯20 mA
Peak output current IOP OUT1 to OUT5 terminal
Duty ≤ 5% (t = 1/fosc × Duty) ⎯400 mA
Power dissipation PDTa ≤ + 25 °C (TSSOP-38P) ⎯ 1680*1mW
Ta ≤ + 25 °C (BCC-40P) ⎯ 1020*2mW
Storage temperature TSTG ⎯ − 55 + 125 °C
MB39A108
8
■RECOMMENDED OPERATING CONDITIONS
* : Refer to “■ SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY”.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Conditions Value Unit
Min Typ Max
Start power supply voltage VCC VCC, VCCO terminal (CH4, CH5) 1.7 ⎯11 V
Power supply voltage VCC VCC, VCCO terminal (CH1 to CH5) 2.5 4 11 V
Reference voltage output
current IREF VREF terminal − 1 ⎯0mA
Input voltage VINE − INE1 to − INE5 terminal 0 ⎯VCC − 0.9 V
− INS terminal 0 ⎯VREF V
VDTC DTC2 to DTC5 terminal 0 ⎯VREF V
Control input voltage VCTL CTL, CTL3 to CTL5 terminal 0 ⎯11 V
Output current IOOUT1 to OUT5 terminal − 15 ⎯ + 15 mA
Oscillation frequency fOSC * 0.2 0.97 2.0 MHz
Timing capacitor CT⎯27 100 680 pF
Timing resistor RT⎯3.0 6.8 39 kΩ
Soft-start capacitor CSCS1 to CS5 terminal ⎯0.1 1.0 µF
Short-circuit detection
capacitor CSCP ⎯⎯0.1 1.0 µF
Reference voltage output
capacitor CREF ⎯⎯0.1 1.0 µF
Operating ambient
temperature Ta ⎯ − 30 + 25 + 85 °C
MB39A108
9
■ELECTRICAL CHARACTERISTICS (VCC = VCCO = 4 V, Ta = + 25 °C)
* : Standard design value (Continued)
Parameter Symbol Pin No. Conditions Value Unit
Min Typ Max
Reference
voltage block
[VREF]
Output
voltage
VREF1 11 VREF = 0 mA 1.98 2.00 2.02 V
VREF2 11 VCC = 2.5 V to 11 V 1.975 2.000 2.025 V
VREF3 11 VREF = 0 mA to − 1 mA 1.975 2.000 2.025 V
Input stability Line 11 VCC = 2.5 V to 11 V ⎯2* ⎯mV
Load stability Load 11 VREF = 0 mA to − 1 mA ⎯2* ⎯mV
Temperature
stability ∆VREF/
VREF 11 Ta = 0 °C to + 85 °C⎯0.20* ⎯%
Short-circuit
output current IOS 11 VREF = 0 V ⎯ − 130* ⎯mA
Under voltage
lockout protection
circuit block
(CH1 to CH3)
[UVLO1_3]
Threshold
voltage VTH 34 VCC = 1.7 1.8 1.9 V
Hysteresis
width VH34 ⎯0.05 0.1 0.2 V
Reset voltage VRST 34 VCC = 1.55 1.7 1.85 V
Under voltage
lockout protection
circuit block
(CH4, CH5)
[UVLO4_5]
Threshold
voltage VTH 30 VCC = 1.35 1.5 1.65 V
Hysteresis
width VH30 ⎯0.02 0.05 0.1 V
Reset voltage VRST 30 VCC = 1.27 1.45 1.63 V
Short-circuit
detection block
[SCP]
Threshold
voltage VTH 15 ⎯0.65 0.70 0.75 V
Input source
current ICSCP 15 ⎯ − 1.4 − 1.0 − 0.6 µA
Triangular wave
oscillator block
[OSC]
Oscillation
frequency
fOSC1 29 to 34 CT = 100 pF, RT = 6.8 kΩ0.92 0.97 1.02 MHz
fOSC2 29 to 34 CT = 100 pF, RT = 6.8 kΩ
VCC = 2.5 V to 11 V 0.917 0.97 1.023 MHz
Frequency
input stability ∆fOSC/
fOSC 29 to 34 CT = 100 pF, RT = 6.8 kΩ
VCC = 2.5 V to 11 V ⎯1.0* ⎯%
Frequency
temperature
stability
∆fOSC/
fOSC 29 to 34 CT = 100 pF, RT = 6.8 kΩ
Ta = 0 °C to + 85 °C⎯1.0* ⎯%
Soft-start block
(CH1, CH2)
[CS1, CS2]
Charge
current ICS 1, 38 CS1, CS2 = 0 V − 13 − 10 − 7 µA
Soft-start block
(CH3 to CH5)
[CS3 to CS5]
Charge
current ICS 19, 20,
27 CS3 to CS5 = 0 V − 1.3 − 1.0 − 0.7 µA
MB39A108
10
(VCC = VCCO = 4 V, Ta = + 25 °C)
* : Standard design value (Continued)
Parameter Symbol Pin No. Conditions Value Unit
Min Typ Max
Error amp block
(CH1)
[Error Amp1]
Threshold voltage VTH1 37 VCC = 2.5 V to 11 V
Ta = + 25 °C0.990 1.000 1.010 V
VTH2 37 VCC = 2.5 V to 11 V
Ta = 0 °C to + 85 °C0.988 1.000 1.012 V
Temperature
stability ∆VTH/
VTH 37 Ta = 0 °C to + 85 °C⎯0.1* ⎯%
Input bias current IB37 − INE1 = 0 V − 120 − 30 ⎯nA
Voltage gain AV36 DC ⎯100* ⎯dB
Frequency
bandwidth BW 36 Av = 0 dB ⎯ 1.4* ⎯MHz
Output voltage VOH 36 ⎯1.7 1.9 ⎯V
VOL 36 ⎯⎯40 200 mV
Output source
current ISOURCE 36 FB1 = 0.65 V ⎯ − 2 − 1mA
Output sink
current ISINK 36 FB1 = 0.65 V 150 200 ⎯µA
Error amp block
(CH2 to CH5)
[Error Amp2 to
Error Amp5]
Threshold voltage VTH1 2, 18,
21, 26 VCC = 2.5 V to 11 V
Ta = + 25 °C1.217 1.230 1.243 V
VTH2 2, 18,
21, 26 VCC = 2.5 V to 11 V
Ta = 0 °C to + 85 °C1.215 1.230 1.245 V
Temperature
stability ∆VTH/
VTH 2, 18,
21, 26 Ta = 0 °C to + 85 °C⎯0.1* ⎯%
Input bias current IB2, 18,
21, 26 − INE2 to − INE5 =
0 V − 120 − 30 ⎯nA
Voltage gain AV3, 17,
22, 25 DC ⎯100* ⎯dB
Frequency
bandwidth BW 3, 17,
22, 25 AV = 0 dB ⎯ 1.4* ⎯MHz
Output voltage VOH 3, 17,
22, 25 ⎯1.7 1.9 ⎯V
VOL 3, 17,
22, 25 ⎯⎯40 200 mV
Output source
current ISOURCE 3, 17,
22, 25 FB2 to FB5 = 0.65 V ⎯ − 2 − 1mA
Output sink
current ISINK 3, 17,
22, 25 FB2 to FB5 = 0.65 V 150 200 ⎯µA
MB39A108
11
(Continued) ( VCC = VCCO = 4 V, Ta = + 25 °C)
* : Standard design value
Parameter Symbol Pin No. Conditions Value Unit
Min Typ Max
PWM compara-
tor block (CH1)
[PWM Comp.1]
Threshold
voltage
VT0 33, 34 Duty cycle = 0% 0.35 0.4 0.45 V
VT100 33, 34 Duty cycle = 100% 0.85 0.9 0.95 V
PWM compara-
tor block
(CH2 to CH5)
[PWM Comp.2 to
PWM Comp.5]
Threshold
voltage VT0 29 to 32 Duty cycle = 0% 0.35 0.4 0.45 V
VT100 29 to 32 Duty cycle = 100% 0.85 0.9 0.95 V
Maximum
duty cycle Dtr 29 to 32 CT = 100 pF,
RT = 6.8 kΩ85 90 95 %
Output block
(CH1 to CH5)
[Drive1 to Drive5]
Output source
current ISOURCE 29 to 34 Duty ≤ 5%
(t = 1/fosc × Duty)
OUT = 0 V ⎯ − 130 − 75 mA
Output sink
current ISINK 29 to 34 Duty ≤ 5%
(t = 1/fosc × Duty)
OUT = 4 V 75 130 ⎯mA
Output on
resistor ROH 29 to 34 OUT = − 15 mA ⎯18 27 Ω
ROL 29 to 34 OUT = 15 mA ⎯18 27 Ω
Dead time tD1 33, 34 OUT2 − OUT1 ⎯50* ⎯ns
tD2 33, 34 OUT1 − OUT2 ⎯50* ⎯ns
Short-circuit
detection block
[SCP Comp.]
Threshold
voltage VTH 34 ⎯0.97 1.00 1.03 V
Input bias
current IB10 − INS = 0 V − 25 − 20 − 17 µA
Control block
(CTL, CTL3 to
CTL5)
[CTL, CHCTL]
Output on
condition VIH 6, 7 to 9 CTL, CTL3 to CTL5 1.5 ⎯11 V
Output off
condition VIL 6, 7 to 9 CTL, CTL3 to CTL5 0 ⎯0.5 V
Input current ICTLH 6, 7 to 9 CTL, CTL3 to CTL5 = 3 V 5 30 60 µA
ICTLL 6, 7 to 9 CTL, CTL3 to CTL5 = 0 V ⎯⎯ 1µA
General
Standby
current ICCS 5 CTL, CTL3 to CTL5 = 0 V ⎯02µA
ICCSO 35 CTL = 0 V ⎯01µA
Power supply
current ICC 5CTL = 3 V ⎯46mA
MB39A108
12
■TYPICAL CHARACTERISTICS
(Continued)
Ta = + 25 °C
CTL = 3 V
02468101
2
5
4
3
2
1
0
Ta = + 25 °C
CTL = 3 V
VREF = 0 mA
02468101
2
5
4
3
2
1
0
2
.05
2
.04
2
.03
2
.02
2
.01
2
.00
1
.99
1
.98
1
.97
1
.96
1
.95
−40 −20 0 +20 +40 +60 +80 +10
0
VCC = 4 V
CTL = 3 V
VREF = 0 mA
Ta = + 25 °C
VCC = 4 V
VREF = 0 mA
02468101
2
5
.0
4
.0
3
.0
2
.0
1
.0
0
.0
Ta = + 25 °C
VCC = 4 V
024681012
250
200
150
100
50
0
Power supply current ICC (mA)
Reference voltage VREF (V)
Power supply current vs. Power supply voltage Reference voltage vs. Power supply voltage
Power supply voltage VCC (V) Power supply voltage VCC (V)
Reference voltage vs. CTL terminal voltage
Reference voltage VREF (V)
Operating ambient temperature Ta ( °C)
Reference voltage VREF (V)
Reference voltage vs. Operating ambient temperature
CTL terminal voltage VCTL (V)
CTL terminal current ICTL (µA)
CTL terminal current vs. CTL terminal voltage
CTL terminal voltage VCTL (V)
MB39A108
13
(Continued)
110
10 100
100
100
0
1000
1
0000
CT = 27 pF
CT = 100 pF
CT = 220 pF
CT = 680 pF
Ta = + 25 °C
VCC = 4 V
CTL = 3 V
10 100
10 1000
100
1000
1000
0000
RT = 2.4 kΩ
RT = 6.8 kΩ
RT = 13 kΩ
RT = 36 kΩ
Ta = + 25 °C
VCC = 4 V
CTL = 3 V
1
.20
1
.10
1
.00
0
.90
0
.80
0
.70
0
.60
0
.50
0
.40
0
.30
0
.20 0 200 400 600 800 100012001400 1600 1800 2000220
0
Ta = + 25 °C
VCC = 4 V
CTL = 3 V
RT = 6.8 kΩ
Upper limit
Lower limit
−40 −20 0 +20 +40 +60 +80 +10
0
VCC = 4 V
CTL = 3 V
RT = 6.8 kΩ
CT = 100 pF
1
.20
1
.10
1
.00
0
.90
0
.80
0
.70
0
.60
0
.50
0
.40
0
.30
0
.20
Upper limit
Lower limit
VCC = 4 V
CTL = 3 V
RT = 6.8 kΩ
CT = 100 pF
1
100
1
080
1
060
1
040
1
020
1
000
980
960
940
920
900
−40 −20 0 +20 +40 +60 +80 +10
0
Triangular wave oscillation frequency vs.
Timing resistor
Triangular wave oscillation
frequency fOSC (kHz)
Timing resistor RT (kΩ)
Triangular wave oscillation frequency vs.
Timing capacitor
Triangular wave oscillation
frequency fOSC (kHz)
Timing capacitor CT (pF)
Triangular wave oscillation frequency vs.
Operating ambient temperature
Triangular wave oscillation
frequency fOSC (kHz)
Operating ambient temperature Ta ( °C)
Triangular wave upper and lower limit voltage vs.
Operating ambient temperature
Triangular wave upper and
lower limit voltage VCT (V)
Operating ambient temperature Ta ( °C)
Triangular wave upper and
lower limit voltage VCT (V)
Triangular wave upper and lower limit voltage vs.
Triangular wave oscillation frequency
Triangular wave oscillation frequency fOSC (kHz)
MB39A108
14
(Continued)
Ta = + 25 °C
VCC = 4 V
CTL = 3 V
FB = 2 V
RT = 6.8 kΩ
CT = 100 pF
0.6 0.65 0.7 0.75 0.8 0.85 0
.9
1
00
95
90
85
80
75
70
65
60
55
50
Calculating
value Measurement value
11010
0
2
1
.5
1
Ta = − 30 °C
Ta = + 25 °C
CTL = VCC
CT = 100 pF
At evaluating Fujitsu
EV board system
225
180
135
90
45
0
−45
−90
−135
−180
−225
50
40
30
20
10
0
−10
−20
−30
−40
−501 k 10 k 100 k 1 M 10 M
Av
Ta = + 25 °C
VCC = 4 V
ϕ
−
+
+
+
36
38
37
10 kΩ
10 kΩ
240 kΩ
2.4 kΩ
1.5 V 1.0 V
2.0 V
1 µF
OU
T
IN
2
000
1
800
1
600
1
400
1
200
1
000
800
600
400
200
0
1
680
−40 −20 0 +20 +40 +60 +80 +10
0
1
200
1
000
800
600
400
200
0
1
020
−40 −20 0 +20 +40 +60 +80 +10
0
Error amplifier voltage gain and phase vs. Frequency
Error amplifier voltage gain
AV (dB)
Phase ϕ (deg)
Frequency f (Hz)
Power dissipation vs.
Operating ambient temperature (TSSOP-38P)
Power dissipation PD (mW)
Operating ambient temperature Ta ( °C)
Error Amp1
the same as other
channels
Power dissipation vs.
Operating ambient temperature (BCC-40P)
Power dissipation PD (mW)
Operating ambient temperature Ta ( °C)
ON Duty vs. DTC terminal voltage
ON Duty (%)
DTC terminal voltage VDTC (V)
Start power supply voltage vs. Timing resistor
Start power supply voltage
VCC (V)
Timing resistor RT (kΩ)
MB39A108
15
■FUNCTIONAL DESCRIPTION
1. DC/DC Converter Function
(1) Reference voltage block (VREF)
The reference voltage circuit generates the reference voltage (2.0 V Typ) to which it makes amends for the
temperature b y the voltage supplied b y the power supply terminal (pin 5). It is used as a ref erence in IC voltage .
It is also possible to supply the load current of up to 1 mA to e xternal device as a output reference voltage through
the VREF terminal (pin 11).
(2) Triangular wave oscillator block (OSC)
The triangular wave oscillator block generates the triangular wave oscillation waveforms of amplitude 0.4 V to
0.9 V by connecting the timing capacitor for and timing resistor to the CT terminal (pin 13) and R T terminal (pin
12) respectively.
The triangular wave is input to the PWM comparator in the IC.
(3) Error amplifier block (Error Amp1 to Error Amp5)
The error amplifier detects output voltage of DC/DC converter and outputs PWM control signals.
In addition, an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the output
terminal to inverted input terminal of the error amplifier, enabling stable phase compensation to the system.
The CS1 ter minal (pin 38) to CS5 terminal (pin 27) that are non-inver ted input ter minal of error amplifier can
prevent rush currents at power supply startup, by connecting a soft-start capacitor . The soft-start time is detected
by the error amplifier, which provides a constant soft-start time independent of output load of DC/DC converter .
Also , it is possib le to prev ent rush current at power supply start-up by connecting a soft-start capacitor with CS1
ter minal (pin 38) to CS5 ter minal (pin 27) which are the non-inverted input ter minal for Error Amp. The use of
Error Amp for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is
independent of the output load on the DC/DC converter.
(4) PWM comparator block (PWM Comp.1 to PWM Comp.5)
The PWM comparator block is a voltage-pulse width converter that controls the output duty depending on the
input/output voltage.
When the error amplifier output v oltage and DTC voltage remain higher than the triangular wa v e voltage , output
transistor is turned on.
(5) Output block (Drive1 to Drive5)
The output block is in the totem-pole type, capable of driving an external P-ch MOS FET (CH1 main side, and
CH2 and CH3) and N-ch MOS FET (CH1 synchronous rectification side, and CH4 and CH5).
MB39A108
16
2. Channel Control Function
Main and each channel are set to ON/OFF by CTL terminal (pin 6) , CS1 terminal (pin 38) , CS2 terminal
(pin 1) , CTL3 terminal (pin 7) , CTL4 terminal (pin 8) , and CTL5 terminal (pin 9) .
ON/OFF setting condition of each channel
Note : Note that current over stand-by current flows into VCC terminal when the CTL terminal is in "L" level and
one of terminals between CTL3 to CTL5 is set to "H" level (Refer to “• CTL3 to CTL5 terminal equivalent
circuit”).
CTL CS1 CS2 CTL3 CTL4 CTL5 Power CH1 CH2 CH3 CH4 CH5
LXXXXXOFFStopsStopsStopsStopsStops
HGNDGNDLLLONStops Stops Stops Stops Stops
HHiZ GNDLLLON
Operation Stops Stops Stops Stops
HGND HiZ LLLONStops Operation Stops Stops Stops
HGND GND H LLONStops Stops Operation Stops Stops
HGND GND L H LONStops Stops Stops Operation Stops
HGND GND L L H ON Stops Stops Stops Stops Operation
HHiZ HiZ HHHON Operation Operation Operation Operation Operation
GND
VCC
86 kΩ
C
TL3
to
C
TL5
223 kΩ
5
14
200 kΩ
ESD
protection
element
• CTL3 to CTL5 terminal equivalent circuit
MB39A108
17
3. Protection Function
(1) Timer-latch short-circuit protection circuit (SCP, SCP Comp.)
The short-circuit detection comparator (SCP) detects the output voltage level of each channel, and if any channel
output voltage becomes the short-circuit detection voltage or less, the timer circuits are actuated to start charging
the external capacitor Cscp connected to the CSCP terminal (pin 15) .
When the capacitor (Cscp) voltage reache s about 0.7 V, the circuit is tur ned off the output transistor and sets
the dead time to 100%.
In addition, the shor t-circuit detection from external input is capable by using −INS ter minal (pin 10) on short-
circuit detection comparator (SCP Comp.) .
To release the actuated protection circuit, either turn the power supply off and on again or set the CTL terminal
(pin 6) to the “L” le v el to lo wer the VREF terminal (pin 11) voltage to 1.27 V (Min) or less (Refer to “■ SETTING
TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT”) .
(2) Under voltage lockout protection circuit block (UVLO)
The transient state or a momentary decrease in the power supply v oltage, which occurs when the po wer supply
is turned on, may cause the IC to malfunction, resulting in breakdown or degradation of the system. To prevent
such malfunctions, under v oltage loc k out protection circuit detects a decrease in internal reference v oltage with
respect to the power supply voltage, turned off the output transistor , and set the dead time to 100 % while holding
the CSCP terminal (pin 15) at "L" level.
The circuit restores the output transistor to normal when the power supply voltage reaches the threshold voltage
of the under-voltage lockout protection circuit.
■PROTECTION CIRCUIT OPERATING FUNCTION TABLE
This table refers to output condition when protection circuit is operating.
Operation circuit OUT1-1 OUT1-2 OUT2 OUT3 OUT4 OUT5
Short-circuit protection circuit H LHHLL
Under voltage lockout protection
circuit HLHHLL
MB39A108
18
■SETTING THE OUTPUT VOLTAGE
■SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY
The triangular wave oscillation frequency can be set by the timing resistor (RT) connected to the RT terminal
(pin 12) and the timing capacitor (CT) connected to the CT terminal (pin 13).
Triangular wave oscillation frequency : fosc
fosc (kHz) :=659600
CT (pF) × RT (kΩ)
Error
Amp
−INE1
CS1
Vo
R
1
R
21.00 V
Vo =1.00 V
R2 (R1 + R
2)
−
+
+
37
38
CH1
Error
Amp
−INEX
CSX
Vo
R
1
R
21.23 V
Vo =1.23 V
R2 (R1 + R
2)
−
+
+
X : Each channel No.
CH2 to CH5
MB39A108
19
■SETTING THE SOFT-START TIME
To prevent rush currents when the IC is tur ned on, you can set a soft-star t by connecting soft-star t capacitors
(CS1 to CS5) to the CS1 terminal (pin 38) to CS5 terminal (pin 27) respectively.
As shown in the figure below, changing CTLX from “H” to “L” in the CH1 and CH2 circuits causes the exter n al
soft-start capacitors (CS1 and CS2) connected to CS1 and CS2 terminals to start charging with a current approx-
imately 10 µA.
As shown in the figure on the next page, changing CTLX from “L” to “H” in the CH3 to CH5 circuits causes the
external soft-start capacitors connected to CS3 to CS5 terminals to start charging with a current of approximately
1 µA.
The error amplifier output (FB1 to FB5) is determined by comparison between the lo wer v oltage of the two non-
inv erted input terminal voltage (1.23 V (CH : 1.0 V), CS terminal voltages) and the inverted input terminal voltage
( − INE1 to − INE5). The FB terminal voltage is decided for the soft-start period (CS terminal voltage < 1.23 V
(CH1 : 1.0 V)) by the comparison between − INE terminal voltage and CS terminal voltage. The DC/DC converter
output voltage rises in proportion to the CS terminal voltage as the soft-start capacitor externally connected to
the CS terminal is charged. The soft-start time is obtained from the following formula :
Soft-start time : ts(time to output 100%)
CH1 : ts (s) := 0.100 × CSX (µF)
CH2 : ts (s) := 0.123 × CSX (µF)
CH3 to CH5 : ts (s) := 1.23 × CSX (µF)
CTLX FBX
Vo VREF
10 µA
R
2
R
1
CSX
CSX
−INEX
1.0 V/
1.23 V
Error Am
p
−
+
+
X : Each channel No.
L priority
• Soft-start circuit (CH1, CH2)
MB39A108
20
• Soft-start circuit (CH3 to CH5)
CTLX CHCTL
FBX
Vo VREF
1 µA
R
2
R
1
CSX
C
SX
−INEX
1.23 V
Error Am
p
−
+
+
X : Each channel No.
L priority
MB39A108
21
■PROCESSING WHEN NOT USING CS TERMINAL
When soft-star t function is not used, leave the CS1 ter minal (pin 38), CS2 ter minal (pin 1), CS3 ter minal (pin
19), CS4 terminal (pin 20), and CS5 terminal (pin 27) open.
27CS5
38CS1
20CS419 CS3
1 CS2
“Open”
“Open”
“Open”
“Open”
“Open”
• When not setting soft-start time
MB39A108
22
■SETTING TIME CONST ANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT
Each channel uses the short-circuit detection comparator (SCP Comp .) to alw a ys compare the error amplifier’s
output level to the reference voltage.
While DC/DC conv erter load conditions are stable on all channels , the short-circuit detection comparator output
remains at "L" level, and the CSCP terminal (pin 15) is held at "L" level.
If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage
to drop, the output of the short-circuit detection comparator on that channel goes to "H" level. This causes the
external short-circuit protection capacitor Cscp connected to the CSCP terminal to be charged at 1 µA.
Short-circuit detection time : tcscp
tcscp (s) := 0.70 × Cscp (µF)
When the capacitor Cscp is charged to the threshold voltage (VTH := 0.7V), the latch is set to and the exter nal
FET is tur ned off (dead time is set to 100%). At this time, the latch input is closed and CSCP terminal (pin 15)
is held at "L" level.
In addition, the short-circuit detection from external input is capable by using −INS terminal (pin 10) on the short-
circuit detection comparator (SCP Comp.) . The short-circuit detection operation starts when −INS terminal
voltage is less than threshold voltage (VTH := 1 V) .
When the power supply is turn off and on again or VREF terminal (pin 11) voltage is less than 1.27 V (Min) by
setting CTL terminal (pin 6) to “L” level, the latch is released.
1.1 V
1 µA
UVLO
CSCP
S
R
Latch
CTL
SCP
Comp.
15 VREF
Vo
R1
R2
Error
Amp
1.23 V (CH1 : 1.0 V)
−INEX
FBX
−
+
−
+
+
CSCP
X : Each channel No.
To each channe
l
drive
• Timer-latch short-circuit protection circuit
MB39A108
23
■PROCESSING WHEN NOT USING CSCP TERMINAL
When not using the timer-latch short-circuit protection circuit, connect the CSCP terminal (pin 15) to GND with
the shortest distance.
14 GND
15 CSCP
• When not using CSCP terminal
MB39A108
24
■SETTING THE DEAD TIME
When the device is set for step-up or inverted output based on the step-up, step-up/down Zeta conversion, step-
up/down Sepic conversion, or flyback conversion, the FB ter minal voltage may reach and exceed the tr iangular
wave voltage due to load fluctuation. If this is the case, the output transistor is fixed to a full-ON state (ON duty =
100 %). To prevent this, set the maximum duty of the output transistor.
When the DTC ter minal is opened, the maximum duty is 90% (Typ) because of this IC built-in resistance which
sets the DTC terminal voltage.
When the DTC ter minal is not used, connect it directly to the VREF ter minal (pin 11) as shown below (when no
dead time is set).
Set the DTC terminal v oltage by resistance divider from VREF terminal voltage when y ou change the maximum
duty by external resistance (Refer to “• When dead time is set (Setting by external resistance)” ).
When the DTC terminal voltage is higher than the triangular wave voltage, the output transistor is turned on.
The maximum duty calculation formula assuming that triangular wave amplitude : = 0.5 V and triangular wave
lower voltage : = 0.4 V is given below.
It is possible to set DTC terminal vo ltage (dead time) by disregarding built-in resistance (include the tolerance)
by adjusting external resistance to 1/10 or less of built-in resistance. Set to become 1mA or less in total of each
channel the load current of VREF terminal.
* : DUTY obtained by the above-mentioned formula is a calculated value. For setting, refer to “ON Duty vs. DTC
terminal voltage” in ■ TYPICAL CHARACTERISTICS.
•When dead time is set
(Setting by built-in resistance := 90%)
X : Each channel No.
•When no dead time is set
X : Each channel No.
DUTY (ON) Max := Vdt − 0.4 V × 100 (%)*
0.5 V
Vdt = Rb × VREF (condition : Ra < R1 , Rb < R2 )
Ra + Rb 10 10
DTCX
“Open”
DTCX
VREF
11
MB39A108
25
Example setting : For an aim Max duty (ON) of 80% (Vdt = 0.8 V) with Ra = 13.7 kΩ and Rb = 9.1 kΩ
• Calculation using external resistors Ra and Rb only
• Calculation considering internal resistor (tolerance ± 20%) also
* : Based on [1] and [2] above, selecting external resistances of 1/10th or less of the built-in resistance enables
the built-in resistance to be ignored.
As f or the duty difference, please e xpect ± 5% (at fOSC = 1 MHz) . It is because of being with the diff erence of a
triangular wave amplitude.
Vdt =Rb × VREF := 0.80 V
Ra + Rb
DUTY (ON) Max :=Vdt − 0.4 V × 100 (%) := 80%* ⋅⋅⋅ [1]
0.5 V
Vdt = (Rb and R2 combined resistance) × VREF := 0.80 V ± 0.13%
(Ra and R1 combined resistance) + (Rb and R2 combined resistance)
DUTY (ON) Max :=Vdt − 0.4 V × 100 (%) := 80% ± 0.2%* ⋅⋅⋅ [2]
0.5 V
DTCX
Ra
Rb
V
dt
R1 : 131.9 kΩ
R2 : 97.5 kΩ
GND
VREF
11
14
•When dead time is set
(Setting by external resistance)
To PWM Comp.
X : Each channel No.
MB39A108
26
■OPERATION EXPLANATION WHEN CTL TURNING ON AND OFF
When CTL is turned on, internal reference voltage VR and VREF generate. When VREF exceeds each threshold
v oltage (VTH1,VTH2) of UVLO1 and UVLO2 (under v oltage lockout protection circuit), UVLO1 and UVLO2 are
released, and the operation of output drive circuit of each channel becomes possible.
When CTL is off, VR and VREF fall. When VREF decreases and UVLO1 and UVLO2 fall below each reset
v oltage (VRST1,VRST2), UVLO operates and output Drive circuit of each channel is f orcibly done the oper ation
stop, and makes the output off state.
When period to reaching to 2.0 V by VREF voltage after UVLO1 and UVLO2 are released by turning on CTL
(refer to a and b in “• Timing chart”) and VREF decreases from 2.0 V after turning off CTL and the period until
do the operation of UVLO1 and UVLO2(refer to a’ and b’ in “• Timing char t”), the bias voltage and the bias
current in IC do not reach a prescribed value because VREF which is the reference voltage does not reach 2.0
V, and the speed of response for IC has decreased.
Moreover, when it does the turning on and off of the input sudden change, the load sudden change, and CTL3
to CTL5 in this period, IC cannot conform and the output might overshoot.
Therefore, impress the voltage to CTL ter minal by which the VREF terminal voltage never stays in the above-
mentioned period.
UVLO1
Power
ON/OFF
CTL
VR
1.0 V/1.23 V
VREF
bias
CT
L
VREF
UVLO2
6
11
SCP
VC
C
5
ErrorAmp Reference
H: at SCP
H: UVLO release
H: UVLO release
CH1 to CH3
To output Drive circuit
H: Possible to operate
L: Forcibly stop
To CS1 to CS3 charge/
discharge circuit
H: Possible to charge
L: Forcibly discharge
CH4 and CH5
To output Drive circuit
H: Possible to operate
L: Forcibly stop
To CS4 and CS5 charge/
discharge circuit
H: Possible to charge
L: Forcibly discharge
• CTL block equivalent circuit
MB39A108
27
VR = 1.23 V (Typ)
VREF = 2.00 V (Typ)
UVLO1_3 a
b
a'
b'
U
VLO4_5
VRST2 VRST1
VTH2
VTH1
1.1 V ± 0.2 V (Typ)
V
t
Error Amp
Reference
voltage VR
Reference
voltage
VREF
CH4 and CH5
Output drive
circuit control
CH1 to CH3
Output drive
circuit control
CTL terminal
voltage
Valid UVLO4_5
Valid UVLO1_3
Fixed full-off
Fixed full-off
UVLO4_5 release
UVLO1_3 release
Possible operate
Possible operate
Fixed full-off
Fixed full-off
• Timing chart
MB39A108
28
■ABOUT THE LOW VOLTAGE OPERATION
1.7 V or more is necessar y for the VCC terminal and the VCCO terminal for the self-power supply type to use
the step-up circuit as the start voltage.
Ev en if VIN decreases up to 1.5 V afterwards, it is possib le to oper ate if the VCC terminal voltage and the VCCO
terminal voltage rise to 2.5 V or more after start-up.
However, it is necessary not to exceed the maximum duty set value by the duty due to the VIN decrease.
Include other channels, and confirm an enough operation margin when using it.
Error
Amp5
−INE5
CS5
R
1
R
21.23 V
Drive5
<<CH5>>
N-ch
A
Vo5
(5 V
)
A
VCC
VCCO
VIN
PWM
Comp.5
VREF
0.9 V
0.4 V
DTC5
Max duty
90% ± 5%
−
+
+
−
+
+
OUT5
26
27
24
35
29
5
Step up
• Example of self-power supply method circuit
MB39A108
29
■I/O EQUIVALENT CIRCUIT
(Continued)
1.23 V
V
CC
11 VRE
F
GND
124 kΩ
79 kΩ
5
14
+
−
6
GND
53 kΩ
C
TL
278 kΩ
GND
86 kΩ
C
TLX
223 kΩ
VCC
CS
X
GND
V
REF
(
2.0 V)
15 CSC
P
GND
V
REF
(
2.0 V)
2 kΩ
VREF
(2.0 V)
VCC
GND
−INS 10
100 kΩ
(1V
)
0.64 V
12 R
T
GND
V
REF
(
2.0 V)
+
−
GND
V
REF
(
2.0 V)
13
CT
VREF
(2.0 V)
VCC
GND
FB
X
CSX
1.0 V (CH1)
1.23 V
(CH2 to CH5)
−INEX
X : Each channel No.
• Reference voltage block • Channel control block (CH3 to to CH5
)
ESD
protection
element
• Control block
• Soft-start block • Short-circuit detection block • Short-circuit detection comparator block
• Triangular wave oscillator
block (RT) • Triangular wave oscillator
block (CT)
• Error amplifier block (CH1 to CH5)
ESD
protection
element
ESD
protection
element
MB39A108
30
(Continued)
OUT
X
G
NDO
V
CCO 35
28
VCC
GND
DTCX
F
B2 to FB5 C
T
VREF
(2.0 V) 131.9 kΩ
97.5 kΩ
X : Each channel No.
• PMW comparator block • Output block (CH1 to CH5)
MB39A108
31
■APPLICATION EXAMPLE
FB1
−INE2
OUT2
V
IN
VCC
CTL
GND
B
CS2
FB2
DTC2
−INE3
OUT3
C
CS3
FB3
DTC3
−INE4
OUT4
D
CS4
FB4
DTC4
−INE5
E
CS5
FB5
DTC5
GNDO
OUT5
−INS
CSCP
RT CT VREF
E
TVo2-2
5.0 V/50 mA
TVo2-1
15 V/10 mA
TVo2-3
−7.5 V/−5 mA
−INE1 VCCO
OUT1-1
DVo1
1.2 V/500 m
A
A
CS1
A
C
TVo1-2
5.0 V/50 mA
TVo1-1
15 V/10 mA
OUT1-2
DVo2
2.5 V/250 m
A
B
CTL3
CTL4
CTL5
D
SVo1
3.3 V/500 m
A
2
1
3
4
32
18
19
17
31
21
20
22
30
26
27
25 28
29
5
6
14
10
15
111312
37
38
36
35
34
16
23
24
33
8
9
7
Q1
Q2
Q3
Q5
Q7
Q9
D1
D2
D4
D5
D7
D8
D9
L1
10 µH
L2
15 µH
C1
1 µFC2
4.7 µF
C3
1 µFC4
4.7 µF
C10
2.2
µF
C9
2.2
µF
C8
1 µF
C13
10 µF
C11
1 µF
C14
1 µF
C16
2.2
µF
C17
2.2
µF
C18
2.2
µF
C23
0.1 µF
C24
0.1
µF
L4
10 µFC12
4.7
µF
T1
L5
15
µH
T2
R35
510 ΩR36
4.3 kΩ
R37
24 kΩ
R38
2 kΩ
C25
0.1 µF
R39
510 Ω
R40
15 kΩ
R41
15 kΩ
R42
1 kΩ
C27
0.1 µF
R45
680 ΩR46
30 kΩ
R47
10 kΩ
C26
0.047 µF
C28
0.047 µF
C30
0.1 µF
R48
1 kΩ
C29
0.1 µF
R51
300 Ω
R52
30 kΩ
R53
18 kΩ
R54
1 kΩ
C31
0.1 µF
C32
0.1 µF
R57
680 Ω
R58
30 kΩ
R59
10 kΩ
R60
1 kΩ
C33
0.1 µF
C34
0.1 µF
C35
2200 pF
C36
100 pF C37
0.1 µF
R63
6.8 kΩ
<<CH1>>
<<CH2>>
<<CH3>>
<<CH4>>
<<CH5>>
D6
(
2.5 V to 5 V)
Step up/down
Transformer
Step down
Step down
Short-circuit
detection signal
(L: at short-circuit)
Transformer
MB39A108
32
■PARTS LIST
Note : SANYO : SANYO Electric Co., Ltd.
TDK : TDK Corporation
SUMIDA : Sumida Corporation
ssm : SUSUMU CO., LT D.
COMPONENT ITEM SPECIFICATION VENDOR PARTS No.
Q1, Q3
Q2, Q7, Q9
Q5
P-ch FET
N-ch FET
P-ch FET
VDS = − 12 V, ID = − 1.5 A
VDS = 20 V, ID = 1.8 A
VDS = − 20 V, ID = − 2 A
SANYO
SANYO
SANYO
MCH3317
MCH3405
MCH3306
D1, D2, D6
D4, D5, D7 to D9 Diode
Diode VF = 0.4 V (Max), at IF = 1 A
VF = 0.55 V (Max), at IF = 0.5 A SANYO
SANYO SBS004
SB05-05CP
L1, L4
L2, L5 Inductor
Inductor 10 µH
15 µH0.94 A, 56 mΩ
0.76 A, 97 mΩ
TDK
TDK
RLF5018T-
100MR94
RLF5018T-
150MR76
T1, T2 Transformer ⎯⎯SUMIDA CLQ52 5388-T138
C1, C3
C2, C4, C12
C8, C11
C9, C10
C13
C14
C16 to C18
C23 to C25, C27
C26, C28
C29 to C34
C35
C36
C37
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
1 µF
4.7 µF
1 µF
2.2 µF
10 µF
1 µF
2.2 µF
0.1 µF
0.047 µF
0.1 µF
2200 pF
100 pF
0.1 µF
25 V
16 V
25 V
25 V
6.3 V
25 V
25 V
50 V
50 V
50 V
50 V
50 V
50 V
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
C3216JB1E105K
C3216JB1C475K
C3216JB1E105K
C3216JB1E225K
C3216JB0J106K
C3216JB1E105K
C3216JB1E225K
C1608JB1H104K
C1608JB1H473K
C1608JB1H104K
C1608JB1H222K
C1608CH1H101J
C1608JB1H104K
R35, R39
R36
R37
R38
R40, R41
R42, R48, R54
R45, R57
R46, R52, R58
R47, R59
R51
R53
R60
R63
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
510 Ω
4.3 kΩ
24 kΩ
2 kΩ
15 kΩ
1 kΩ
680 Ω
30 kΩ
10 kΩ
300 Ω
18 kΩ
1 kΩ
6.8 kΩ
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
RR0816P-511-D
RR0816P-432-D
RR0816P-243-D
RR0816P-202-D
RR0816P-153-D
RR0816P-102-D
RR0816P-681-D
RR0816P-303-D
RR0816P-103-D
RR0816P-301-D
RR0816P-183-D
RR0816P-102-D
RR0816P-682-D
MB39A108
33
■REFERENCE DATA
(Continued)
1
00
95
90
85
80
75
70
65
60 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7
.0
Ta = + 25 °C
DV
O
1 = 1.2 V, 500 mA
DV
O
2 = 2.5 V, 250 mA
TV
O
1-1 = 15 V , 10 mA
TV
O
1-2 = 5 V, 50 mA
SV
O
1 = 3.3 V, 500 mA
TV
O
2-1 = 15 V, 10 mA
TV
O
2-2 = 5 V, 50 mA
TV
O
2-3 = 7.5 V, −5 mA
f
OSC
= 1 MHz setting
1
00
95
90
85
80
75
70
65
60 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
CH2
CH4
CH1
CH5
CH3
7
.0
Ta = + 25 °C
DV
O
1 = 1.2 V, 500 mA
DV
O
2 = 2.5 V, 250 mA
TV
O
1-1 = 15 V , 10 mA
TV
O
1-2 = 5 V, 50 mA
SV
O
1 = 3.3 V, 500 mA
TV
O
2-1 = 15 V, 10 mA
TV
O
2-2 = 5 V, 50 mA
TV
O
2-3 = −7.5 V, −5 mA
f
OSC
= 1 MHz
IC stops by the short-circuit
detection operation of CH2 in
VIN := 2.6 V or less.
Total efficiency vs. Input voltage
Input voltage VIN (V)
Total efficiency η (%)
Setting
Note : Only concerned CH is ON.
Driving current of external
SW Tr is contained.
Each CH efficiency vs. Input voltage
Input voltage VIN (V)
Each CH Efficiency η (%)
MB39A108
34
(Continued)
1
00
VIN = 3.6 V
CH1
CH4
Ta = +25 °C
95
90
85
80
75
70
65
60 0 50 100 150 200 250 300 350 400 450 50
0
1
00
VIN = 3.6 V
CH2 Ta = +25 °C
95
90
85
80
75
70
65
60 0 25 50 75 100 125 150 175 200 225 25
0
DIO1 (CH1) ≤ 50 mA : discontinuance
mode
SIO1 (CH4) ≤ 80 mA : discontinuance
mode
CH1 and CH4 efficiency vs. Load current
Load current IO (mA)
CH1 and CH4 efficiency η (%)
CH2 efficiency vs. Load current
Load current IO (mA)
CH2 efficiency η (%)
DIO2 (CH2) ≤ 30 mA : discontinuance
mode
Note : Only concerned CH is ON.
Driving current of external
SW Tr is contained.
Note : Only concerned CH is ON.
Driving current of external
SW Tr is contained.
MB39A108
35
(Continued)
1
00
VIN = 3.6 V
Ta = +25 °C
95
90
85
80
75
70
65
60 010203040506
0
CH5
CH3
TIO1-2 (CH3), TIO2-2 (CH5) ≤ 10 mA : discontinuance mode
CH3 and CH5 efficiency vs. Load current
Load current IO (mA)
CH3 and CH5 efficiency η (%)
Notes :
•Only feedback controlling output is get by
using transformer channel.
TVO1-1 (15 V) : IO = 10 mA fixed
TVO2-1 (15 V) : IO = 10 mA fixed
TVO2-3 ( − 7.5 V) : IO = − 5 mA fixed
•Only concerned CH is ON.
Driving current of external SW Tr is contained.
MB39A108
36
(Continued)
O
UT1-1 [V]
5
0 1.00.90.80.70.60.50.40.30.20.1
0OUT1-2 [V]
t [µs]
5
Ta = +25 °C
VIN = 3.6 V
DVo1 = 1.2
V
lo1 = 500 m
A
0
VD [V]
4
2
0
O
UT2 [V]
5
0 1.00.90.80.70.60.50.40.30.20.1
0
t [µs]
Ta = +25 °C
VIN
= 3.6 V
DVo2 = 2.5
V
lo2 = 250 m
A
VD [V]
4
2
0
Ta = +25 °C
V
IN = 3.6 V
TVo1-1 = 15 V
Tlo1-1 = 10 m
A
TVo1-2 = 5 V
TVo3 = 50 mA
O
UT3 [V]
5
0 1.00.90.80.70.60.50.40.30.20.1
0
t [µs]
VD [V]
5
0
−5
−10
Switching waveform (CH1)
Switching waveform (CH2)
Switching waveform (CH3)
MB39A108
37
(Continued)
Ta = +25 °C
VIN = 3.6 V
SVo1 = 3.3 V
Slo1 = 500 m
A
O
UT4 [V]
5
0 1.00.90.80.70.60.50.40.30.20.1
0
t [µs]
VD [V]
10
5
0
Ta = +25 °C
VIN = 3.6 V
TVo2-1 = 15 V
Tlo2-1 = 10 mA
TVo2-2 = 5 V
Tlo2-2 = 50 mA
TVo2-3 = −7.5
V
Tlo2-3 = −5 mA
O
UT5 [V]
5
0 1.00.90.80.70.60.50.40.30.20.1
0
t [µs]
VD [V]
10
5
0
Switching waveform (CH4)
Switching waveform (CH5)
MB39A108
38
■USAGE PRECAUTIONS
• Printed circuit board ground lines should be set up with consideration for common impedance.
• Take appropriate static electricity measures.
• Containers for semiconductor materials should hav e anti-static protection or be made of conductive material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
• Do not apply negative voltages.
• The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause
malfunction.
■ORDERING INFORMATION
■EV BOARD ORDERING INFORMATION
■RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION
The LSI products of Fujitsu with “E1” are compliant with RoHS Directive , and has observed the standard of
lead, cadmium, mercury, Hexav alent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl
ethers (PBDE) .
The product that conforms to this standard is added “E1” at the end of the part number.
Part number Package Remarks
MB39A108PFT-❏❏❏E1 38-pin plastic TSSOP
(FPT-38P-M03) Lead Free version
MB39A108PV2-❏❏❏E1 40-pin plastic BCC
(LCC-40P-M07) Lead Free version
EV board part No. EV board version No. Remarks
MB39A108EVB-01 Board Rev. 1.0 TSSOP-38P
MB39A108
39
■MARKING FORMAT (LEAD FREE VERSION)
MB39A108
XXXX E1
XXX
INDEX
3
XXXX XXX
E1
INDEX
9A108
Lead Free version
Lead Free version
TSSOP-38P
(FPT-38P-M03)
BCC-40
(LCC-40P-M07)
MB39A108
40
■LABELING SAMPLE (LEAD FREE VERSION)
2006/03/01
ASSEMBLED IN JAPAN
G
QC PASS
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
1,000
PCS
0605 - Z01A
1000
1/1
1561190005
MB123456P - 789 - GE1
MB123456P - 789 - GE1
MB123456P - 789 - GE1
Pb
Lead Free version
lead-free mark
JEITA logo JEDEC logo
MB39A108
41
■MB39A108PFT-❏❏❏E1 (TSSOP-38P)
RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL
[Temperature Profile for FJ Standard IR Reflow]
(1) IR (infrared reflow)
(2) Manual soldering (partial heating method)
Conditions : Temperature 400 °C Max
Times : 5 s max/pin
Item Condition
Mounting Method IR (infrared reflow) , Manual soldering (partial heating method)
Mounting times 2 times
Storage period
Before opening Please use it within two years after
Manufacture.
From opening to the 2nd
reflow Less than 8 days
When the storage period after
opening was exceeded Please processes within 8 days
after baking (125 °C, 24H)
Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
260 °C
(e)
(d')
(d)
255 °C
170 °C
190 °C
RT (b)
(a)
(c)
to
Note : Temperature : the top of the package body
(a) Temperature Increase gradient : Average 1 °C/s to 4 °C/s
(b) Preliminary heating : Temperature 170 °C to 190 °C, 60 s to 180 s
(c) Temperature Increase gradient : Average 1 °C/s to 4 °C/s
(d) Actual heating : Temperature 260 °C Max; 255 °C or more, 10 s or less
(d’) : Temperature 230 °C or more, 40 s or less
or
Temperature 225 °C or more, 60 s or less
or
Temperature 220 °C or more, 80 s or less
(e) Cooling : Natural cooling or forced cooling
H rank : 260 °C Max
MB39A108
42
■MB39A108PV2-❏❏❏E1 (BCC-40)
RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL
[Temperature Profile for FJ Standard IR Reflow]
(1) IR (infrared reflow)
(2) Manual soldering (partial heating method)
Conditions : Temperature 400 °C Max
Times : 5 s max/pin
Item Condition
Mounting Method IR (infrared reflow) , Manual soldering (partial heating method)
Mounting times 2 times
Storage period Before opening Please use it within two years after
Manufacture.
From opening to the reflow
Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
260 °C
(e)
(d')
(d)
255 °C
170 °C
190 °C
RT (b)
(a)
(c)
to
Note : Temperature : the top of the package body
(a) Temperature Increase gradient : Average 1 °C/s to 4 °C/s
(b) Preliminary heating : Temperature 170 °C to 190 °C, 60 s to 180 s
(c) Temperature Increase gradient : Average 1 °C/s to 4 °C/s
(d) Actual heating : Temperature 260 °C Max; 255 °C or more, 10 s or less
(d’) : Temperature 230 °C or more, 40 s or less
or
Temperature 225 °C or more, 60 s or less
or
Temperature 220 °C or more, 80 s or less
(e) Cooling : Natural cooling or forced cooling
H rank : 260 °C Max
MB39A108
43
■PACKAGE DIMENSION
(Continued)
38-pin plastic TSSOP Lead pitch 0.50 mm
Package width
×
package length
4.40 × 9.70 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.10 mm MAX
38-pin plastic TSSOP
(FPT-38P-M03)
(FPT-38P-M03)
C
2002 FUJITSU LIMITED F38003Sc-1-1
0.127±0.05
(.005±.002)
9.70±0.10(.382±.004)
4.40±0.10 6.40±0.10
(.252±.004)(.173±.004)
0.10(.004)
0.50(.020)
0.10±0.10
(.004±.004)
(.024±.004)
0.60±0.10
0.25(.010)
INDEX
1.10(.043)
0.90±0.05
(.035±.002)
9.00(.354)
0~8˚
MAX
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB39A108
44
(Continued)
40-pin plastic BCC Lead pitch 0.50 mm
Package width ×
package length 6.00 mm ×6.00 mm
Sealing method Plastic mold
Mounting height 0.80 mm MAX
Weight 0.05 g
40-pin plastic BCC
(LCC-40P-M07)
(LCC-40P-M07)
C
2004 FUJITSU LIMITED C40057S-c-1-1
1
11
31
21
0.50±0.10
(.020±.004)
0.50(.020)
TYP
4.00(.157)
REF
5.25(.207)
REF
"B"
"C"
"A"
5.25(.207)REF
0.50±0.10
(.020±.004)
0.50(.020)
TYP
5.10(.201)TYP
5.20(.205)TYP
0.80(.031)MAX
0.075±0.025
(.003±.001)
11
21
31
1
6.00±0.10(.236±.004)
(Stand off)
6.00±0.10
(.236±.004)
0.05(.002)
Details of "B" part
0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
(Mount height)
INDEX AREA
Details of "A" part
(.028±.002)
0.70±0.06
(.012±.002)
0.30±0.06
C0.20(.008)
Details of "C" part
(.022±.002)
0.55±0.06
(.022±.002)
0.55±0.06
0.14(.006)
MIN
0.60±0.06
(.024±.002)
4.00(.157)REF
5.20(.205)
5.10(.201)
TYP
TYP
0.14(.006)
MIN
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB39A108
F0608
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
Edited Business Promotion Dept.