SN54HC02, SN74HC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS076B – DECEMBER 1982 – REVISED MAY 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These devices contain four independent 2-input
NOR gates. They perform the Boolean function
Y = A + B or Y = A • B in positive logic.
The SN54HC02 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC02 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS OUTPUT
A B Y
H X L
XHL
L L H
logic symbol†
2
1A 3
1B 1Y
1
5
2A 6
2B 2Y
4
8
3A 9
3B 3Y
10
11
4A 12
4B 4Y
13
≥1
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
logic diagram (positive logic)
A
BY
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1Y
1A
1B
2Y
2A
2B
GND
VCC
4Y
4B
4A
3Y
3B
3A
SN54HC02 ...J OR W PACKAGE
SN74HC02 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4B
NC
4A
NC
3Y
1B
NC
2Y
NC
2A
1A
1Y
NC
3A
3B V
4Y
2B
GND
NC
SN54HC02 . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54HC02, SN74HC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS076B – DECEMBER 1982 – REVISED MAY 1997
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54HC02 SN74HC02
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VIL Low-level input voltage VCC = 4.5 V 0 1.35 0 1.35 V
VCC = 6 V 0 1.8 0 1.8
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V 0 1000 0 1000
ttInput transition (rise and fall) time VCC = 4.5 V 0 500 0 500 ns
VCC = 6 V 0 400 0 400
TAOperating free-air temperature –55 125 –40 85 °C
SN54HC02, SN74HC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS076B – DECEMBER 1982 – REVISED MAY 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HC02 SN74HC02
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 6 V 5.9 5.999 5.9 5.9 V
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
IOL = 20 µA4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 6 V 0.001 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6 V 2 40 20 µA
Ci2 V to 6 V 3 10 10 10 pF
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO
VCC
TA = 25°C SN54HC02 SN74HC02
UNIT
PARAMETER
(INPUT) (OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 45 90 135 115
tpd A or B Y4.5 V 9 18 27 23 ns
6 V 8 15 23 20
2 V 38 75 110 95
ttY4.5 V 8 15 22 19 ns
6 V 6 13 19 16
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per gate No load 22 pF
SN54HC02, SN74HC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS076B – DECEMBER 1982 – REVISED MAY 1997
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
50%50% 10%10% 90% 90% VCC
0 V
trtf
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily . All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
