CY62137CV18 MoBL2™
Document #: 38-05017 Rev. *C Page 4 of 11
tCDR[5] Chip Deselect to Data
Retention Time 0ns
tR[6] Operation Recovery Time tRC ns
Data Retention Characteristics (Over the Op erat ing Ran ge) (conti nue d)
Parameter Description Conditions Min. Typ.[4] Max. Unit
Data Retention Waveform[7]
Switching Characteristics Over the Operating Range[8]
Parameter Description 55 ns 70 ns UnitMin. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Va lid 25 35 ns
tLZOE OE LOW to Low-Z[9] 5 5 ns
tHZOE OE HIGH to High-Z[9, 10 ] 20 25 ns
tLZCE CE LOW to Low-Z[9] 510 ns
tHZCE CE HIGH to High-Z[9, 10] 20 25 ns
tPU CE LOW to Power-up 0 0 ns
tPD CE HIGH to Power-down 55 70 ns
tDBE BLE/BHE LOW to Data Valid 55 70 ns
tLZBE BLE/BHE LOW to Low-Z[9] 5 5 ns
tHZBE BLE/BHE HIGH to High-Z[9, 10] 20 25 ns
Write Cycle[11]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 40 60 ns
tAW Address Set-up to Write End 40 60 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-up to Write Start 0 0 ns
tPWE WE Pulse Widt h 40 50 ns
tBW BLE/BHE LOW to Write End 40 60 ns
tSD Data Set-up to Write End 25 30 ns
tHD Data Hold from Write End 0 0 ns
Notes:
6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the
specified IOL/IOH and 30 pF load capaci tance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZCE, tHZBE and tHZWE transiti ons a re meas ured when the ou tput s ent er a h igh imped ance st ate.
11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
VCC(min.)
VCC(min.)
tCDR
VDR >1.0 V
DATA RETENTION MODE
tR
CE or
VCC
BHE.BLE