128K x 16 Static RAM
CY62137CV18 MoBL2™
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05017 Rev. *C Revised August 28, 2002
Features
•High speed
—55 ns and 70 ns availability
•Low voltage range:
—1.65V−1.95V
•Pin-compatible with CY62137BV18
•Ultra-low active power
—Typical Active Current: 0.5 mA @ f = 1 MHz
—Typical Active Current: 1.5 mA @ f = fmax (70 ns
speed)
•Low standby power
•Easy memory expans ion with C E and OE features
•Automatic power -do wn wh en dese lec t ed
•CMOS for optimum speed/power
Functional Description
The CY62137CV18 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
togg lin g. Th e dev ic e c an al so be pu t into st andby mode wh en
deselected (CE HIGH or both BLE and BHE are HIGH) . The
input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when: deselected (CE HIGH), outputs
are disab led (OE HIGH), both Byte High Enable an d Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW, and WE LO W).
Writing to the device is accomplished by taking Chip Enable
(CE) and Writ e Enab le (WE ) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 thro ugh A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW , the n data from me mory will app ear on I/O8 to I/O15. See
the Truth Table at the back of this data sheet for a complete
description of read and write modes.
The CY62137CV18 is available in a 48-ball FBGA package.
Logic Block Diagram
128K x 16
RAM Array I/O0–I/O7
COLUMN DECODER
A11
A12
A13
A14
A15
2048 X 1024
SENSE AM PS
DATA IN DRIVERS
OE
I/O8–I/O15
CE
WE
BLE
BHE
A16
ROW DECODER
A7
A6
A3
A0
A2
A1
A5
A4
A8
Power - Down
Circuit BHE
BLE
CE
A9
A10
CY62137CV18 MoBL2™
Document #: 38-05017 Rev. *C Page 2 of 11
Maximum Ratings
(Abov e wh ic h th e us eful life ma y be imp aire d. For user gui de-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.2V to +2.4V
DC Voltage Applied to Outputs
in High-Z State[3]...................................–0.2V to VCC + 0.2V
DC Input Voltage[3] ...............................–0.2V to VCC + 0.2V
Output Current into Outpu t s (LO W)..................... ..... ...20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Pin Configuration[1, 2 ]
WE
Vccq
A11
A10
NC
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
Vssq
A7
I/O0
BHE
NC
DNU
A2
A1
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
FBGA
A16
Top Vi e w
Operating Range
Device Range Ambient
Temperature VCC
CY62137CV18 Industrial −40°C to +85°C 1.65V to 1.95V
Product Portfolio
Product VCC Range Speed
Power Dissipation (Industrial)
Operating (ICC)Standby (ISB2)f = 1 MHz f = fmax
VCC(min.) VCC(typ.)[4] VCC(max.) Typ.[4] Max. Typ.[4] Max. Typ.[4] Max.
CY62137CV18 1.65V 1.80V 1.95V 55 ns 0.5 mA 2 mA 2 mA 7 mA 1 µA8 µA
70 ns 0.5 mA 2 m A 1.5 mA 6 mA
Electri cal Characteristics Over the Operating Range
Parameter Description Test Conditions CY62137CV18-55 CY62137CV18-70 UnitMin. Typ.[4] Max. Min. Typ.[4] Max.
VOH Output HIGH Voltage IOH = −0.1 mA VCC = 1.65V 1.4 1.4 V
VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.65V 0.2 0.2 V
VIH Input HIGH Voltage 1.4 VCC +
0.2V 1.4 VCC +
0.2V V
VIL Input LOW Voltage –0.2 0.4 –0.2 0.4 V
IIX Input Leakage Current GND < VI < VCC –1+1–1+1µA
Notes:
1. NC pins are not connected to the die.
2. E3 (DNU) can be left as NC or VSS to ensure proper application.
3. VIL(min) = −2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
CY62137CV18 MoBL2™
Document #: 38-05017 Rev. *C Page 3 of 11
IOZ Output Leakage
Current GND < VO < VCC, Output Disabled –1+1–1+1µA
ICC VCC Operating Supply
Curre nt f = fMAX = 1/tRC VCC = 1.95V
IOUT = 0 mA
CMOS levels
27 1.56mA
f = 1 MHz 0.5 2 0.5 2 mA
ISB1 Automatic CE
Power-down Current—
CMOS Inputs
CE > VCC− 0.2V, VIN > VCC− 0.2V, VIN
< 0.2V f = fMAX (Address and Data
Only), f = 0 (OE, WE, BHE, and BLE)
18 18µA
ISB2 Automatic CE
Power-down Current—
CMOS Inputs
CE > VCC− 0.2V VIN > VCC − 0.2V or
VIN < 0.2V, f = 0, VCC = 1.95V
Electri cal Characteristics Over the Operating Range (continued)
Parameter Description Test Conditions CY62137CV18-55 CY62137CV18-70 UnitMin. Typ.[4] Max. Min. Typ.[4] Max.
Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Capa citance TA = 25°C, f = 1 MHz,
VCC= VCC(typ) 6pF
COUT Output Capacitance 8pF
Thermal Resistance
Parameter Description Test Conditions BGA Unit
ΘJA Thermal Resistance
(Junction to Ambient)[5] Still Air , soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board 55 °C/W
ΘJC Thermal Resistance
(Junction to Cas e)[5] 16 °C/W
AC Test Loads and Waveforms
VCC Typ
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
OUTPUT V
Equivalent to: THÉ VENINEQUIVALENT
ALL INPUT PULSES
RTH
R1
Rise Time:
1 V/ns Fall Time:
1 V/ns
Parameters 1.8V UNIT
R1 13500 Ohms
R2 10800 Ohms
RTH 6000 Ohms
VTH 0.80 Volts
Data Retention Characteristics (Over the Op erat ing Range)
Parameter Description Conditions Min. Typ.[4] Max. Unit
VDR VCC for Data Retention 1.0 1.95 V
ICCDR Da t a Retention Current VCC = 1.0V, CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V 0.5 5µA
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
CY62137CV18 MoBL2™
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tCDR[5] Chip Deselect to Data
Retention Time 0ns
tR[6] Operation Recovery Time tRC ns
Data Retention Characteristics (Over the Op erat ing Ran ge) (conti nue d)
Parameter Description Conditions Min. Typ.[4] Max. Unit
Data Retention Waveform[7]
Switching Characteristics Over the Operating Range[8]
Parameter Description 55 ns 70 ns UnitMin. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Va lid 25 35 ns
tLZOE OE LOW to Low-Z[9] 5 5 ns
tHZOE OE HIGH to High-Z[9, 10 ] 20 25 ns
tLZCE CE LOW to Low-Z[9] 510 ns
tHZCE CE HIGH to High-Z[9, 10] 20 25 ns
tPU CE LOW to Power-up 0 0 ns
tPD CE HIGH to Power-down 55 70 ns
tDBE BLE/BHE LOW to Data Valid 55 70 ns
tLZBE BLE/BHE LOW to Low-Z[9] 5 5 ns
tHZBE BLE/BHE HIGH to High-Z[9, 10] 20 25 ns
Write Cycle[11]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 40 60 ns
tAW Address Set-up to Write End 40 60 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-up to Write Start 0 0 ns
tPWE WE Pulse Widt h 40 50 ns
tBW BLE/BHE LOW to Write End 40 60 ns
tSD Data Set-up to Write End 25 30 ns
tHD Data Hold from Write End 0 0 ns
Notes:
6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the
specified IOL/IOH and 30 pF load capaci tance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZCE, tHZBE and tHZWE transiti ons a re meas ured when the ou tput s ent er a h igh imped ance st ate.
11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
VCC(min.)
VCC(min.)
tCDR
VDR >1.0 V
DATA RETENTION MODE
tR
CE or
VCC
BHE.BLE
CY62137CV18 MoBL2™
Document #: 38-05017 Rev. *C Page 5 of 11
tHZWE WE LOW to High-Z[9, 10] 20 25 ns
tLZWE WE H IGH to Low-Z[9] 510 ns
Switching Characteristics Over the Operating Range[8] (continued)
Parameter Description 55 ns 70 ns UnitMin. Max. Min. Max.
Switching Waveforms
Notes:
12. Device is continuously selected. OE, CE = VIL, BHE and/or BL E = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE, BHE, BLE, transition LOW.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
Read Cycle No. 1(Address Transition Controlled)
[12, 13]
Read Cycle No. 2 (OE Controlled)[13, 14]
50%
50%
DATA VALID
tRC
tACE
tLZBE
tLZCE
tPU
DATA OUT HIGH IMPEDANC E
IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
tHZBE
BHE/BLE tLZOE
ADDRESS
tDOE
tDBE
CY62137CV18 MoBL2™
Document #: 38-05017 Rev. *C Page 6 of 11
Notes:
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simult aneousl y with WE HIGH , th e outpu t remains in a high-i mpedance stat e.
17. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATAIN VALID
NOTE
Write Cycle N o. 1 ( WE Controlled)[11, 15, 16]
17
BHE/BLE tBW
tSCE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 17
Write Cycle No. 2 (CE Controlled)
BHE/BLE tBW
[11 , 15 , 1 6]
tSA
CY62137CV18 MoBL2™
Document #: 38-05017 Rev. *C Page 7 of 11
Switching Waveforms
DATAIN VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATAI/O NOTE 17
Write Cycle No. 3 (WE Controlled, OE LOW)
tBW
BHE/BLE
[16]
DATA I/O
ADDRESS
tHD
tSD
tSA
tHA
tAW
tWC
CE
WE
DATAIN VALID
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[16]
NOTE 17
tBW
BHE/BLE
tSCE
tPWE
CY62137CV18 MoBL2™
Document #: 38-05017 Rev. *C Page 8 of 11
Typical DC and AC Charac ter istics ( Typ ical v alues are inclu ded for re ferenc e only and are n ot guara nteed o r tested .
Typical values are measured at VCC = VCC(typ) Typ, TA = 25°C.)
3.5
3.0
1.5
1.0
0.5
1.80
0
2.0
ISB (µA)
2.4
2.0
1.2
0.8
0.4
1.65 1.80 1.95
0.0
1.6
ICC (mA)
40
35
25
20
15
1.65 1.8 1.95
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
10
30
TAA (ns)
Operating Current Standby Current vs. Supply Voltage
SUPP LY VO LTAG E (V)
SUPP LY VO LTAG E (V)
MoBL2
MoBL2
MoBL2
vs. Supply Voltage
1.95
1.65
(f = fmax, 55 ns)
(f = fmax, 70 ns)
(f = 1 MHz)
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High-Z Deselect/Power-down Standby (ISB)
X X X H H High-Z Deselect/Power-down Standby (ISB)
L H L L L Data Out (I/OO–I/O15)Read Acti ve (ICC)
L H L H L Data Out (I/OO–I/O7);
I/O8–I/O15 in High-Z Read Active (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z Read Active (ICC)
L H H L L High-Z Output Disa bled Active (ICC)
L H H H L High-Z Output Di sa ble d Active (ICC)
L H H L H High-Z Output Disable d Active (ICC)
L L X L L Data In (I/OO–I/O15)Write Active (ICC)
L L X H L Data In (I/OO–I/O7);
I/O8–I/O15 in High-Z Write Active (ICC)
L L X L H Data In (I/O8–I/O15);
I/O0 –I/O7 in High-Z Write Active (ICC)
CY62137CV18 MoBL2™
Document #: 38-05017 Rev. *C Page 9 of 11
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
70 CY62137CV18LL-70BAI BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) Industrial
CY62137CV18LL-70BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8mm x 1 mm)
55 CY62137CV18LL-55BAI BA48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62137CV18LL-55BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8mm x 1 mm)
Package Diagram
48-ball (7.00 mm x 7.00 mm x 1.20 mm) Fine Pitch BGA BA48A
51-85096-A
CY62137CV18 MoBL2™
Document #: 38-05017 Rev. *C Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
Package Diagram (co nti nue d)
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*A
CY62137CV18 MoBL2™
Document #: 38-05017 Rev. *C Page 11 of 11
Document Title: CY62137CV18 MoBL2™ 128K x 16 Static RAM
Document Number: 38-05017
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 106265 5/7/01 HRT/MGN New Data Sheet
*A 108941 08/24/01 MGN From Preliminary to Final
*B 110572 11/02/01 MGN Format standardization.
Improved T ypical Icc @ f = 1 MHz fo r 55 ns and 70 ns and Max Icc @ f = fMAX
for 70 ns.
Improved Typical and Max ICCDR.
*C 115866 09/04/02 DPM Added BV pack age
.
