ICS8304 LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8304 is a low skew, 1-to-4 Fanout ICS Buffer and a member of the HiPerClockSTM famHiPerClockSTM ily of High Performance Clock Solutions from IDT. The ICS8304 is characterized at full 3.3V for input (VDD), and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and par t-to-par t skew characteristics make the ICS8304 ideal for those clock distribution applications demanding well defined performance and repeatability. * Four LVCMOS / LVTTL outputs * LVCMOS / LVTTL clock input * CLK can accept the following input levels: LVCMOS, LVTTL * Maximum output frequency: 200MHz * Additive phase jitter, RMS: 0.173ps (typical) @ 3.3V * Output skew: 45ps (maximum) @ 3.3V * Part-to-part skew: 500ps (maximum) * Small 8 lead SOIC package saves board space * 3.3V input, outputs may be either 3.3V or 2.5V supply modes * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) compliant packages BLOCK DIAGRAM PIN ASSIGNMENT Q0 VDDO VDD CLK GND Q1 CLK Pullup Q2 8 7 6 5 Q3 Q2 Q1 Q0 ICS8304 8-Lead SOIC 3.9mm x 4.9mm, x 1.375mm package body M Package Top View Q3 IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 1 2 3 4 1 ICS8304AM REV. G JUNE 11, 2007 ICS8304 LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 VDDO Power Description Output supply pin. 2 VDD Power Positive supply pin. 3 CLK Input Pulldown LVCMOS / LVTTL clock input. 4 GN D Power 5 Q0 Output Single clock output. LVCMOS / LVTTL interface levels. 6 Q1 Output Single clock output. LVCMOS / LVTTL interface levels. 7 Q2 Output Single clock output. LVCMOS / LVTTL interface levels. 8 Q3 Output Single clock output. LVCMOS / LVTTL interface levels. Power supply ground. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN RPULLDOWN Input Capacitance Power Dissipation Capacitance (per output) Input Pulldown Resistor ROUT Output Impedance CPD IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER Test Conditions Minimum Typical Maximum 4 VDD, VDDO = 3.465V pF 15 51 5 2 7 Units pF k 12 ICS8304AM REV. G JUNE 11, 2007 ICS8304 LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 112.7C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 VDDO Output Power Supply Voltage 3.465 V IDD Power Supply Current 15 mA IDDO Output Supply Current 8 mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C Symbol Parameter Minimum Typical Maximum Units VDD Positive Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 15 mA IDDO Output Supply Current 8 mA TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 1.3 V IIH Input High Current VDD = VIN = 3.465V 150 A IIL Input Low Current VDD = 3.465V, VIN = 0V -5 A Refer to NOTE 1 2.6 V IOH = -16mA 2.9 V IOH = -100uA 3 V VOH VOL Output High Voltage Output Low Voltage Test Conditions Minimum Typical Maximum Units Refer to NOTE 1 0.5 V IOL = 16mA 0.25 V IOL = 100uA 0.15 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Section, "3.3V Output Load Test Circuit". IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 3 ICS8304AM REV. G JUNE 11, 2007 ICS8304 LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions Minimum 2 Typical VDD + 0.3 V VIL Input Low Voltage -0.3 1.3 V IIH Input High Current VDD = VIN = 3.465V IIL Input Low Current VDD = 3.465V, VIN = 0V VOH Output High Voltage; NOTE 1 150 -5 A A 2.1 V Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Section, "3.3V/2.5V Output Load Test Circuit". 0.5 V TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter fMAX tpLH Test Conditions Minimum 166MHz 2. 0 166MHz < f 189.5MHz 125MHz, Integration Range: 12kHz - 20MHz = 133MHz 2.0 Maximum Output Frequency Propagation Delay, Low-to-High; NOTE 1 tsk(o) Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR Output Rise Time 30% to 70% tF Output Fall Time 30% to 70% t jit Typical Maximum Units 200 MHz 3. 3 ns 3.4 ns 0.173 ps 45 ps 500 ps 250 500 ps 250 500 ps 60 % Maximum Units 189.5 MHz ns odc Output Duty Cycle f 189.5MHz 40 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum fMAX Maximum Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR Output Rise Time 30% to 70% 250 tF Output Fall Time 30% to 70% odc Output Duty Cycle For NOTES, please see above Table 4A. f 189.5MHz IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 4 Typical 166MHz 2.3 3. 7 166MHz < f 189.5MHz 2.15 3.55 ns 60 ps 500 ps 500 ps 250 500 ps 40 60 % = 133MHz ICS8304AM REV. G JUNE 11, 2007 ICS8304 LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz SSB PHASE NOISE dBc/HZ Additive Phase Jitter @ 125MHz (12kHz to 20MHz) = 0.173ps typical OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 5 ICS8304AM REV. G JUNE 11, 2007 ICS8304 LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2.05V5% 1.65V5% 1.25V5% SCOPE VDD, VDDO SCOPE VDD VDDO Qx LVCMOS Qx GND LVCMOS GND -1.65V5% -1.25V5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT PART 1 V DD Qx Qx 2 PART 2 V DD 2 V DD DD Qy V Qy 2 tsk(o) OUTPUT SKEW 2 tsk(pp) PART-TO-PART SKEW V 70% DDO 70% 2 Q0:Q3 Clock Outputs t PW 30% 30% tR t tF odc = PERIOD t PW x 100% t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VDD 2 CLK VDDO 2 Q0:Q3 t PD PROPAGATION DELAY IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 6 ICS8304AM REV. G JUNE 11, 2007 ICS8304 LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVCMOS OUTPUT: All unused LVCMOS output can be left floating. There should be no trace attached. RELIABILITY INFORMATION TABLE 5. JAVS. AIR FLOW TABLE JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W 200 128.5C/W 103.3C/W 500 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8304 is: 416 IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 7 ICS8304AM REV. G JUNE 11, 2007 ICS8304 LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC TABLE 6. PACKAGE DIMENSIONS - SUFFIX M SYMBOL Millimeters MINIMUN N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 e H 4.00 1.27 BASIC 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Reference Document: JEDEC Publication 95, MS-012 IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 8 ICS8304AM REV. G JUNE 11, 2007 ICS8304 LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8304AM 8304AM 8 lead SOIC Tube 0C to 70C ICS8304AMT 8304AM 8 lead SOIC 2500 Tape and Reel 0C to 70C ICS8304AMLN 8304AMLN 8 lead SOIC, Lead Free/Annealed ICS8304AMLNT 8304AMLN 8 lead SOIC, Lead Free/Annealed ICS8304AMLF 8304AMLF ICS8304AMLFT 8304AMLF Tube 0C to 70C 2500 Tape and Reel 0C to 70C 8 lead SOIC, Lead Free Tube 0C to 70C 8 lead SOIC, Lead Free 2500 Tape and Reel 0C to 70C While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 9 ICS8304AM REV. G JUNE 11, 2007 ICS8304 LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER REVISION HISTORY SHEET Rev B C C D Table T4A Page 3 Description of Change * Revised tpLH (Propagation Delay) row from 2.3 Min. to 2 Min. * Deleted tpHL row. * Revised tsk(o) (Output Skew) row from 35 Max. to 80 Max. * Revised tsk(pp) (Par t-to-Par t Skew) row from 200 Max. to 500 Max. * General note changed from "...measured at 166MHz..." to " ...measured at 150MHz..." T4B 4 T4 A 3 * Revised tpLH (Propagation Delay) row from 2.6 Min. to 2.3 Min. * Deleted tpHL row. * Revised tsk(o) (Output Skew) row from 35 Max. to 85 Max. * Revised tsk(pp) (Par t-to-Par t Skew) row from 200 Max. to 500 Max. * General note changed from "...measured at 166MHz..." to " ...measured at 150MHz..." * In AC table, revised tsk(o) row from 80ps Max. to 45ps Max. Added f = 133MHz in Test Conditions column. * In odc row, deleted test conditions. * In notes, changed 150MHz to fMAX. T4B 4 T7 10 T3B 3 T1 T2 1 2 2 E T3A & T3C T7 3&4 8 1 T4A 4 F T4B 4 F T7 G T4A 8 1 4 5 7 * In AC table, revised tsk(o) row from 80ps Max. to 60ps Max. Added f = 133MHz in Test Conditions column. * In odc row, deleted test conditions * In notes, changed 150MHz to fMAX. In the Ordering Information table, Marking column, revised marking to read 8304AM from ICS8304AM. LVCMOS/LVTTL DC Characteristics Table, added IOH and IOL Test Conditions to VOH and VOL rows. * Pin Assignment - adjusted dimensions. * Pin Descriptions - changed VDD description to Core supply pin. * Pin Characteristics - changed CIN max 4pF to typical 4pF. Deleted RPULLUP row. Added 5 min. and 12 max. to ROUT. * Power Supply tables - changed VDD parameter from Power to Core. * Ordering Information table - added "Lead Free/Annealed" marking. Updated format throughout the data sheet. Featues section, changed Maximum output frequency bullet from 166MHz to 200MHz. 3.3V AC Table - changed 166MHz max. to 200MHz max. Added another line for Propagation Delay. Changed test conditions in Output Duty Cycle from 166MHz to 189.5MHz. 3.3V AC Table - changed 166MHz max. to 189.5MHz max. Added another line for Propagation Delay. Changed test conditions in Output Duty Cycle from 166MHz to 189.5MH * Ordering Information table - added "Lead Free" marking. Features Section - added Additive Phase Jitter bullet. 3.3V AC Characteristics Table - added Additive Phase Jitter row. Added Additive Phase Jitter plot. Added Recommendations for Unused Output Pins. IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 10 Date 12/4/01 12/11/01 3/11/02 4/4/02 4/13/04 6/1/04 9/13/04 6/11/07 ICS8304AM REV. G JUNE 11, 2007 ICS8304 LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA