LOW SKEW, 1-TO-4 LVCMOS/LVTTL
FANOUT BUFFER
ICS8304
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 1 ICS8304AM REV. G JUNE 11, 2007
GENERAL DESCRIPTION
The ICS8304 is a low skew, 1-to-4 Fanout
Buffer and a member of the HiPerClockS™ fa m -
ily of High Performance Clock Solutions from
IDT. The ICS8304 is characterized at full 3.3V
for input (VDD), and mixed 3.3V and 2.5V for out-
put operating supply modes (VDDO). Guaranteed output and
part-to-part skew characteristics make the ICS8304 ideal
for those clock distribution applications demanding well
defined performance and repeatability.
FEATURES
•Four LVCMOS / LVTTL outputs
•LVCMOS / LVTTL clock input
•CLK can accept the following input levels: LVCMOS, LVTTL
•Maximum output frequency: 200MHz
•Additive phase jitter, RMS: 0.173ps (typical) @ 3.3V
•Output skew: 45ps (maximum) @ 3.3V
•Part-to-part skew: 500ps (maximum)
•Small 8 lead SOIC package saves board space
•3.3V input, outputs may be either 3.3V or 2.5V supply modes
•0°C to 70°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
compliant packages
BLOCK DIAGRAM PIN ASSIGNMENT
ICS8304
8-Lead SOIC
3.9mm x 4.9mm, x 1.375mm package body
M Package
Top View
VDDO
VDD
CLK
GND
1
2
3
4
HiPerClockS™
ICS
Q3
Q2
Q1
Q0
8
7
6
5
Q0
Q1
Q2
Q3
CLK Pullup
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 2 ICS8304AM REV. G JUNE 11, 2007
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
C
DP
ecnaticapaCnoitapissiDrewoP
)tuptuorep( V
DD
V,
ODD
V564.3=51Fp
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
R
TUO
ecnadepmItuptuO5721Ω
ρεβμυΝεμαΝεπψΤνοιτπιρχσεΔ
1V
ODD
rewoP.nipylppustuptuO
2V
DD
rewoP.nipylppusevitisoP
3KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL
4DNGrewoP.dnuorgylppusrewoP
50QtuptuO .slevelecafr
etniLTTVL/SOMCVL.tuptuokcolcelgniS
61QtuptuO .slevelecafretniLTTVL/SOMCVL.tuptuokcolcelgniS
72QtuptuO .slevel
ecafretniLTTVL/SOMCVL.tuptuokcolcelgniS
83QtuptuO .slevelecafretniLTTVL/SOMCVL.tuptuokcolcelgniS
:ETON nwod
lluP .seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
Number Name Type Description
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 3 ICS8304AM REV. G JUNE 11, 2007
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSrewoP531.33.3564.3V
V
ODD
egatloVylppuSrewoPtuptuO531.33.3564.3V
I
DD
tnerruCylppuSrewoP 51Am
I
ODD
tnerruCylppuStuptuO 8Am
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI2V
DD
3.0+V
V
LI
egatloVwoLtupnI3.0-3.1V
I
HI
tnerruChgiHtupnIV
DD
V=
NI
V564.3=051Aµ
I
LI
tnerruCwoLtupnIV
DD
V,V564.3=
NI
V0=5-Aµ
V
HO
egatloVhgiHtuptuO
1ETONotrefeR6.2V
I
HO
Am61-=9.2V
I
HO
Au001-=3 V
V
LO
egatloVwoLtuptuO
1ETONotrefeR5.0V
I
LO
Am61=52.0V
I
LO
Au001=51.0V
05htiwdetanimretstuptuO:1ETON ΩVot
ODD
."tiucriCtseTdaoLtuptuOV3.3",noitceStnemerusaeMretemaraPeeS.2/
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, V
O-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSevitisoP 531.33.3564.3V
V
ODD
egatloVylppuStuptuO 573.25.2526.2V
I
DD
tnerruCylppuSrewoP 51Am
I
ODD
tnerruCylppuStuptuO 8Am
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 4 ICS8304AM REV. G JUNE 11, 2007
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI2V
DD
3.0+V
V
LI
egatloVwoLtupnI3.0-3.1V
I
HI
tnerruChgiHtupnIV
DD
V=
NI
V564.3=051Aµ
I
LI
tnerruCwoLtupnIV
DD
V,V564.3=
NI
V0=5-Aµ
V
HO
1ETON;egatloVhgiHtuptuO1.2V
V
LO
1ETON;egatloVwoLtuptuO 5.0V
05htiwdetanimretstuptuO:1ETON ΩVot
ODD
,noitceStnemerusaeMretemaraPeeS.2/
."tiucriCtseTdaoLtuptuOV5.2/V3.3"
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuOmumixaM 002zHM
pt
HL
;hgiH-ot-woL,yaleDnoitagaporP
1ETON
IJzHM6610.23.3sn
f<zHM661 ≤zHM5.9810.24.3sn
ttij ;SMR,rettiJesahPevitiddAreff
uB
noitceSrettiJesahPevitiddAotrefer
:egnaRnoitargetnI,zHM521
zHM02–zHk21 371.0sp
t)o(ks4,2ETON;wekStuptuOzHM
331=ƒ54sp
t)pp(ks4,3ETON;wekStraP-ot-traP 005sp
t
R
emiTesiRtuptuO%07ot%03052005sp
t
F
emiTllaFtuptuO%07ot%03052005sp
cdoelcyCytuDtuptuOf≤zHM5.9810406%
ftaderusaemsretemarapllA
XAM
.esiwrehtodetonsselnu
VmorfderusaeM:1ETON
DD
Vottupniehtfo2/
ODD
.tuptuoehtfo2/
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
Vtade
rusaeM
ODD
.2/
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusaemerastup
tuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
Vta
ODD
.2/
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuOmumixaM 5.981zHM
pt
HL
1ETON;hgiH-ot-woL,yaleDnoitagaporP IJzHM6613.27.3sn
f<zHM661 ≤zHM5.98151.255.3sn
t)o(ks4,2ETON;wekStuptuOzHM331=ƒ0
6sp
t)pp(ks4,3ETON;wekStraP-ot-traP 005sp
t
R
emiTesiRtuptuO%07ot%03052005sp
t
F
emiTllaFtuptuO%07ot%03052005sp
cdoelcyCytuDtuptuOf≤zHM5.9810406%
.A4elbaTevobaeesesaelp,SETONroF
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 5 ICS8304AM REV. G JUNE 11, 2007
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
Additive Phase Jitter @ 125MHz
(12kHz to 20MHz) = 0.173ps typical
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise . This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 6 ICS8304AM REV. G JUNE 11, 2007
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
LVCMOS
GND
1.65V±5%
SCOPE
Qx
LVCMOSGND
2.05V±5%
-1.25V±5%
OUTPUT SKEW
OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Clock
Outputs
30%
70% 70%
30%
tRtF
tsk(o)
V
DD
2
V
DD
2
Qx
Qy
tsk(pp)
V
DD
2
V
DD
2
Qx
Qy
PART 1
PART 2
Q0:Q3
t
PD
V
DD
2
V
DDO
2
PROPAGATION DELAY
tPERIOD
tPW
tPERIOD
odc =
V
DDO
2
x 100%
tPW
Q0:Q3
CLK
VDD,
VDDO
-1.65V±5%
VDD
VDDO
1.25V±5%
PART-TO-PART SKEW
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 7 ICS8304AM REV. G JUNE 11, 2007
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
TRANSISTOR COUNT
The transistor count for ICS8304 is: 416
TABLE 5. θJAVS. AIR FLOW TABLE
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
RELIABILITY INFORMATION
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. There should
be no trace attached.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 8 ICS8304AM REV. G JUNE 11, 2007
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
TABLE 6. PACKAGE DIMENSIONS - SUFFIX M
Reference Document: JEDEC Publication 95, MS-012
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
LOBMYS sretemilliM
NUMINIMMUMIXAM
N8
A53.157.1
1A01.052.0
B33.015.0
C91.052.0
D08.400.5
E08.300.4
eCISAB72.1
H08.502.6
h52.005.0
L04.07
2.1
α°0°8
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 9 ICS8304AM REV. G JUNE 11, 2007
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
TABLE 7. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT
MA4038SCIMA4038CIOSdael8ebuTC°07otC°0
TMA4038SCIMA403
8CIOSdael8leeRdnaepaT0052C°07otC°0
NLMA4038SCINLMA4038delaennA/eerFdaeL,CIOSdael8ebuTC°07otC°0
TNLMA4038SCINLMA
4038delaennA/eerFdaeL,CIOSdael8leeRdnaepaT0052C°07otC°0
FLMA4038SCIFLMA4038eerFdaeL,CIOSdael8ebuTC°07otC°0
TFL
MA4038SCIFLMA4038eerFdaeL,CIOSdael8leeRdnaepaT0052C°07otC°0
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 10 ICS8304AM REV. G JUNE 11, 2007
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
TEEHSYROTSIHNOISIVER
veRelbaTegaPegnahCfonoitpircseDetaD
BA4T
B4T
3
4
ptdesiveR•
HL
.niM2ot.niM3.2morfwor)yaleDnoitagaporP(
ptdeteleD•
LH
.wor
.xaM08ot.xaM53morfwor)wekStuptuO()o(kstdesiveR•
.xaM005ot.xaM002morfwor)wekStraP-ot-traP()pp(kstde
siveR•
ot"...zHM661taderusaem..."morfdegnahcetonlareneG•
"...zHM051taderusaem..."
ptdesiveR•
HL
.niM3.2ot.niM6.2morfwor)yaleDnoitagaporP(
ptdeteleD•
LH
.wor
.xaM58ot.xaM53morfwor)wekStuptuO()o(kstdesiveR•
.xaM005ot.xaM002morfwor)wekStraP-ot-traP()pp(kstde
siveR•
ot"...zHM661taderusaem..."morfdegnahcetonlareneG•
"...zHM051taderusaem..."
10/4/21
CA4T
B4T
3
4
.xaMsp5
4ot.xaMsp08morfwor)o(kstdesiver,elbatCAnI•
.nmulocsnoitidnoCtseTnizHM331=fdeddA
.snoitidnoctsetdeteled,
worcdonI•
fotzHM051degnahc,setonnI•
.XAM
.xaMsp06ot.xaMsp08morfwor)o(kstdesiver,elbatCAnI•
.nmulocsnoitidnoCtseTnizHM331=fdeddA
snoitidnoctsetde
teled,worcdonI•
fotzHM051degnahc,setonnI•
.XAM
10/11/21
C7T01 daerotgnikramdesiver,nmulocgnikraM,elbatnoitamrofnIgniredrOehtnI
.MA4038SCImorfMA4038 20/11
/3
DB3T3 Idedda,elbaTscitsiretcarahCCDLTTVL/SOMCVL
HO
Idna
LO
snoitidnoCtseT
Vot
HO
Vdna
LO
.swor 20/4/4
E
1T
2T
C3T&A3T
7T
1
2
2
4&3
8
.snoisnemiddetsujda-tnemngissAniP•
Vdegnahc-snoitpircseDniP•
DD
.nipylppuseroCotnoitpircsed
Cdegnahc-scitsiretcarahCniP•
NI
.Fp4lacipytotFp4xam
RdeteleD
PULLUP
.wor
5deddA Ω21dna.nim ΩRot.xam
TUO
.
Vdegnahc-selbatylppuSrewoP•
DD
.eroCotrewoPmorfretemarap
.gnikram"delaennA/eerFdaeL"dedda-elbatnoitamrofnIgniredrO•
.teehsatadehttuohg
uorhttamrofdetadpU
40/31/4
F
A4T
B4T
1
4
4
otzHM661morftellubycneuqerftuptuomumixaMdegnahc,noitcesseutaeF
.zHM
002
.xamzHM002ot.xamzHM661degnahc-elbaTCAV3.3
.yaleDnoitagaporProfenilrehtonadeddA
.zHM5.981otzHM661morf
elcyCytuDtuptuOnisnoitidnoctsetdegnahC
.xamzHM5.981ot.xamzHM661degnahc-elbaTCAV3.3
.yaleDnoitagaporProf
enilrehtonadeddA
HM5.981otzHM661morfelcyCytuDtuptuOnisnoitidnoctsetdegnahC
40/1/6
F7T8 .gnikram"eerFdaeL"ded
da-elbatnoitamrofnIgniredrO• 40/31/9
GA4T
1
4
5
7
dedda-noitceSserutaeF rettiJesahPevitiddA .tellub
dedda-elbaT
scitsiretcarahCCAV3.3 rettiJesahPevitiddA .wor
deddA rettiJesahPevitiddA .tolp
deddA .sniPtuptuOdesunUrofsno
itadnemmoceR
70/11/6
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
