[AK1545]
MS1471-E-00 1 2012/10
AK1545
3.5GHz Low Noise Integer-N Frequency Synthesizer
1. Overview
The AK1545 is an Integer-N PLL (Phase Locked Loop) frequency synthesizer, covering a wide range of frequency
from 500MHz to 3.5GHz. Consisting of a highly accurate charge pump, a reference divider, a programmable
divider and a dual-modulus prescaler (P/P+1), this product provides high performance, very low Phase Noise. An
ideal PLL can be achieved by combining the AK1545 with the external loop filter and VCO (Voltage Controlled
Oscillator). Access to the registers is controlled via a 3-wire serial interface. The operating supply voltage is from
2.7V to 5.5V, and the charge pump circuit and the serial interface can be driven by individual supply voltage.
2. Features
Operating frequency : 500MHz to 3.5GHz
Programmable charge pump current : 250A and 1mA
Fast lock mode : The charge pump current is switched by this function.
Supply Voltage : 2.7 to 5.5 V (AVDD, DVDD pins)
Separate Charge Pump Power Supply : AVDD to 5.6V (CPVDD pin)
Excellent Phase Noise : -217dBc/Hz
On-chip lock detection feature of PLL : Selectable Phase Frequency Detector (PFD) Output or
Digital filtered lock detect
Package : 16pin TSSOP
Operating temperature : -40°C to 85°C
[AK1545]
MS1471-E-00 2 2012/10
- Table of Contents -
1. Overview __________________________________________________________________________ 1
2. Features ___________________________________________________________________________ 1
3. Block Diagram ______________________________________________________________________ 3
4. Pin Functional Description and Assignments ____________________________________________ 4
5. Absolute Maximum Ratings ___________________________________________________________ 6
6. Recommended Operating Range ______________________________________________________ 6
7. Electrical Characteristics _____________________________________________________________ 7
8. Block Functional Descriptions ________________________________________________________ 11
9. Register Map ______________________________________________________________________ 19
10. Function Description - Registers _____________________________________________________ 21
11. IC Interface Schematic ______________________________________________________________ 29
12. Recommended Connection Schematic of Off-Chip Component ____________________________ 31
13. Power-Up Timing Chart (Recommended Flow) __________________________________________ 33
14. Frequency Setting Timing Chart (Recommended Flow) ___________________________________ 34
15. Typical Evaluation Board Schematic __________________________________________________ 35
16. Typical Performance Characteristics __________________________________________________ 36
17. Outer Dimensions __________________________________________________________________ 37
18. Marking __________________________________________________________________________ 38
In this specification, the following notations are used for specific signal and register names.
[Name] : Pin name
<Name> : Register group name (Address name)
{Name} : Register bit name
[AK1545]
MS1471-E-00 3 2012/10
3. Block Diagram
CP
PHASE
FREQENCY
DETECTOR
REFIN
+
-
PRESCALER
32/33
PROGRAMABLE
COUNTER
13 bit
LOCK DETECT
RFINP
RFINN
CPVDD
VSS
AVDD
LD
CLK
DATA
LE
REGISTER
21 bit
N DIVIDER
FAST
COUNTER
PDN
TEST2
TEST1
R COUNTER
14 bit
SW
CHARGE
PUMP
SWALLOW
COUNTER
5 bit
DVDD
Fig. 1 Block Diagram
[AK1545]
MS1471-E-00 4 2012/10
4. Pin Functional Description and Assignments
Table 1 Pin Functions
No.
Name
I/O
Pin Functions
Power Down
(Note 1)
Remarks
1
SW
DO
Fast lock switch output
2
CP
AO
Charge pump output
“Hi-Z”
3
VSS
G
Ground
4
TEST1
DI
TEST input 1. This pin must be connected to
ground.
Schmidt trigger input
5
RFINN
AI
Complementary input to the RF Prescaler
6
RFINP
AI
Input to the RF Prescaler
7
AVDD
P
Power supply for analog blocks
8
REFIN
AI
Reference signal input
9
TEST2
DI
TEST input 2. This pin must be connected to
ground.
Schmidt trigger input
10
PDN
DI
Power down
Schmidt trigger input
11
CLK
DI
Serial clock input
Schmidt trigger input
12
DATA
DI
Serial data input
Schmidt trigger input
13
LE
DI
Load enable input
Schmidt trigger input
14
LD
DO
Lock detect output
15
DVDD
P
Power supply for digital blocks
16
CPVDD
P
Power supply for charge pump
Note 1) “Power Down” means the state of [PDN] =”Low” after power on.
The following table shows the meaning of abbreviations used in the “I/O” column.
AI: Analog input pin
AO: Analog output pin
AIO: Analog I/O pin
DI: Digital input pin
DO: Digital output pin
P: Power supply pin
G: Ground pin
[AK1545]
MS1471-E-00 5 2012/10
2. Pin Assignments
1
2
3
4
5
6
7
8
9
10
15
14
13
12
11
16
TOP
VIEW
SW
CP
VSS
RFINN
TEST1
DATA
LE
LD
DVDD
CPVDD
RFINP
AVDD
REFIN
CLK
PDN
TEST2
16pin TSSOP
Fig. 2 Pin Assignment
[AK1545]
MS1471-E-00 6 2012/10
5. Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Unit
Remarks
Supply Voltage
VDD1
-0.3
6.5
V
[AVDD], [DVDD] (Note 1)
VDD2
-0.3
6.5
V
[CPVDD] (Note 1)
Ground Level
VSS
0
0
V
[VSS]
Analog Input Voltage
VAIN
VSS-0.3
VDD1+0.3
V
[RFINN], [RFINP], [REFIN] (Notes 1 & 2)
Digital Input Voltage
VDIN
VSS-0.3
VDD1+0.3
V
[CLK], [DATA], [LE], [PDN] (Notes 1 & 2)
Input Current
IIN
-10
10
mA
Storage Temperature
Tstg
-55
125
°C
Note 1) 0V reference for all voltages.
Note 2) Maximum must not be over 6.5V.
Exceeding these maximum ratings may result in damage to the AK1545. Normal operation is not guaranteed at
these extremes.
6. Recommended Operating Range
Table 3 Recommended Operating Range
Parameter
Symbol
Min.
Typ.
Max.
Unit
Remarks
Operating Temperature
Ta
-40
85
C
Supply Voltage
VDD1
2.7
5.5
V
Applied to the [AVDD],[DVDD] pins
VDD2
VDD1
5.6
V
Applied to the [CPVDD] pin
Note 1) VDD1 and VDD2 can be driven individually within the Recommended Operating Range.
Note 2) All specifications are applicable within the Recommended Operating Range (operating temperature /
supply voltage).
[AK1545]
MS1471-E-00 7 2012/10
7. Electrical Characteristics
1. Digital DC Characteristics
Table 4 Digital DC Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Remarks
High level input voltage
Vih
0.8VDD1
V
Note 1)
Low level input voltage
Vil
0.2VDD1
V
Note 1)
High level input current
Iih
Vih = VDD1=5.5V
-1
1
A
Note 1)
Low level input current
Iil
Vil = 0V, VDD1=5.5V
-1
1
A
Note 1)
High level output voltage
Voh
Ioh = -500A
VDD1-0.4
V
Note 2)
Low level output voltage
Vol
Iol = 500A
0.4
V
Note 3)
High level output voltage2
Voh
Ioh = -500A
VDD2-0.4
V
Note 4)
Note 1) Applied to the [ CLK ], [ DATA ], [ LE ] and [ PDN ] pins.
Note 2) Applied to the [ LD ] pins.
Note 3) Applied to the [LD],[SW] pins.
Note 4) Applied to the [ SW] pins.
[AK1545]
MS1471-E-00 8 2012/10
2. Serial Interface Timing
<Write-In Timing>
Fig. 3 Serial Interface Timing Chart
Table 5 Serial Interface Timing
Parameter
Symbol
Min.
Typ.
Max.
Unit
Remarks
Clock L level hold time
Tcl
25
ns
Clock H level hold time
Tch
25
ns
Clock setup time
Tcsu
10
ns
Data setup time
Tsu
10
ns
Data hold time
Thd
10
ns
LE setup time
Tlesu
10
ns
LE pulse width
Tle
20
ns
LE
(Input)
CLK
(Input)
DATA
(Input)
Tsu
Thd
Tcsu
D18
D2
A0
A1
D0
D1
Tch
Tcl
Tlesu
Tle
[AK1545]
MS1471-E-00 9 2012/10
3. Analog Circuit Characteristics
VDD1＝2.7V to 5.5V, VDD2=VDD1 to 5.6V, –40°C ≤ Ta ≤ 85°C, unless otherwise specified.
Parameter
Min.
Typ.
Max.
Unit
Remarks
RF Characteristics
Input Sensitivity
-10
2
dBm
Input Frequency
500
3500
MHz
REFIN Characteristics
Input Sensitivity
0.4
VDD1
Vpp
Input Frequency
5
100
MHz
Maximum Allowable Prescaler Output
Frequency
120
MHz
Phase Detector
Phase Detector Frequency
55
MHz
Charge Pump
Charge Pump High Value
1
mA
Charge Pump Low Value
250
A
Icp TRI-STATE Leak Current
1
nA
0.6≤Vcpo≤VDD2-0.7, Ta=25°C
Mismatch between Source and Sink Currents
(Note 1)
3
%
Vcpo=VDD2/2, Ta=25°C
Icp vs. Vcpo (Note 2)
2
%
0.5≤Vcpo≤VDD2-0.5, Ta=25°C
Noise Characteristic
Normalized Phase Noise Floor
-217
dBc/Hz
Current Consumption
IDD1
10
A
[PDN]=“0” or {PD1}=1
IDD2 (Note3, Note4)
12
18
mA
[PDN]=”1”, {PD1}=0, IDD for VDD1
IDD3 (Note4)
0.4
0.7
mA
[PDN]=”1”, {PD1}=0, IDD for VDD2
Note 1) Mismatch between Source and Sink Currents : [(|Isink|-|Isource|)/{(|Isink|+|Isource|)/2}] × 100 [%]
Note 2) See “Charge Pump Characteristics - Voltage vs. Current”. Vcpo is the output voltage at [CP].
Icp vs. Vcpo : [{1/2×(|I1|-|I2|)}/{1/2×(|I1|+|I2|)}]×100 [%]
Note 3) When [PDN] = ”1” and {PD1}=0, the total power supply current of the AK1545 is “IDD2+IDD3+ Charge
pump current”.
Note 4) RFIN=3.5GHz,5dBm, REFIN=100MHz,10dBm, {R}=100,{B}=109,{A}=12
[AK1545]
MS1471-E-00 10 2012/10
Isink
Isource
Vcpo
Icp
CPVDD-0.5
CPVDD/2
0.5
I1
I1
I2
I2
Fig. 4 Charge Pump Characteristics - Voltage (Vcpo) vs. Current (Icp)
[AK1545]
MS1471-E-00 11 2012/10
8. Block Functional Descriptions
1. Frequency Setup
The following formula is used to calculate the frequency setting for the AK1545.
Frequency setting (external VCO output frequency) = FPFD x N
Where :
N : Dividing number N = [ (P x B) + A ]
FPFD : Phase detector frequency FPFD = [REFIN] pin input frequency / R counter dividing number
P : 32
B : B (Programmable) counter value (See <Address1>:{B[12:0]})
A : A (Swallow) counter value (See <Address1>:{A[4:0]})
Calculation example
The output frequency of external reference frequency oscillator is 10MHz, and FPFD is 1MHz and VCO
frequency is 3000MHz.
AK1545 setting :
R (Reference counter) =10000000/1000000 = 10 (<Address0>:{R[13:0]}= “10”)
P=32
B=93 (<Address1>:{B[12:0]}=”93”)
A=24 (<Address1>:{A[4:0]}=”24”)
Frequency setting = 1M × [ (32×93) + 24] = 3000MHz
Lower limit for setting consecutive dividing numbers
In the AK1545, it is not possible to set consecutive dividing numbers below the lower limit.
(The lower limit is determined by a dividing number set for the prescaler.)
The following table shows an example where consecutive dividing numbers below the lower limit cannot be set.
The consecutive dividing numbers can be set when B ≥ P-1.
[AK1545]
MS1471-E-00 12 2012/10
P=32 (Dual modulus prescaler 32/33)
P
B[12:0]
A[5:0]
N [ (P×B) + A ]
Remarks
32
30
30
990
991 cannot be set as an N divider.
32
31
0
992
This is the lower limit.
992 or over can consecutively be set as an N divider.
32
31
1
993
・
・
・
・
32
4097
15
131119
・
・
・
・
32
8191
30
262142
32
8191
31
262143
[AK1545]
MS1471-E-00 13 2012/10
2．Charge Pump, Loop Filter and Fast Lock Up Mode
The current setting of charge pump and loop filter can switch with the built-in timer for Fast Lock.
C2
Phase Detector
up
down
Timer
VCO
Loop Filter
C1
C3
R2
R3
CP
SW
R2’
Fig. 5 Loop Filter Schematic
Fast Lock Mode 1
The output level of [SW] pin is programmed to a low state, and the charge pump current is switched to the
high value (1 mA). [SW] is used to switch a resistor in the loop filter and to ensure stability while in the fast
lock up mode by altering the loop bandwidth.
When the {CPGAIN} bit in the N register is set to “1”, the AK1545 enters the fast lock up mode. When the
{CPGAIN} bit in the N register is set to “0”, the AK1545 exits the fast lock up mode.
Fast Lock Mode 2
The output level of [SW] pin is programmed to a low state, and the charge pump current is switched to the
high value (1 mA). [SW] is used to switch a resistor in the loop filter and to ensure stability while in the fast
lock up mode by altering the loop bandwidth.
When the {CPGAIN} bit in the N register is set to “1”, the AK1545 enters the fast lock up mode. The AK1545
exits the fast lock up mode after the expiration of the timer. The timer configuration is set by the value in
{TIMER [3:0]}. After the timeout, the {CPGAIN} bit in the N register is automatically reset to 0, and the device
reverts to normal mode instead of the fast lock up mode.
[AK1545]
MS1471-E-00 14 2012/10
Fast Lock Up
High Value
VSS
Normal
Normal
Low Value
Hi-Z
Low Value
Hi-Z
Operation mode
Charge pump current
[SW] pin control
Fast Lock Up time
specified by the timer
Fig. 6 Fast Lock Up Mode Timing Chart
Table 6 Fast Lock Mode Function
Function
{FASTEN}={D7}
{FASTMODE}={D9}
{CPGAIN}
[SW]-pin state
Fast Lock Mode
disable
0
X
0
{D9} state
1
Fast Lock Mode 1
1
0
0
Hi-Z
1
VSS
Fast Lock Mode 2
1
1
(*1) Controlled by the value in
{TIMER [3:0]}.
(*1) When the timer is counting, {CPGAIN} =”1” and [SW] pin is low state. After the timeout, its function reverts to
normal mode ({CPGAIN} =”0” and [SW] pin is Hi-Z state) instead of the fast lock up mode.
[SW]-pin Functions
SW pin is a General Purpose Output (GPO) pin which can be controlled by FASTEN register.
(1) {FASTEN} =”0”
The value of D9 register comes out from the SW pin.
AK1545
SW
■FASTMODE＝[D9]＝0 : SW＝“LOW” (CPVSS)
■FASTMODE＝[D9]＝1 : SW＝“HIGH” (CPVDD)
(2) {FASTEN} =”1”
Works as shown in the “Fast Lock UP Mode Timing Chart” above.
[AK1545]
MS1471-E-00 15 2012/10
3．Lock Detect
Lock detect output can be selected by {LD[2:0]} in <Address2>. When {LD} is set to “101Bin", the phase detector
outputs an un-manipulated phase detection(comparison) result. (This is called “analog lock detect”.) When {LD} is
set to “001Bin”, the lock detect signal is output according to the on-chip logic. (This is called “digital lock detect”.)
The lock detect can be done as following:
The [LD] pin is in unlocked state (which outputs “Low”) when a frequency setup (N register or R register settings)
is made.
Case of Lock to Unlock is as following.
R=1: The [LD] pin outputs “High” when a phase error smaller than a half cycle of [REFIN] (1/2T) is detected
for the counter value N times consecutively.
R>1: The [LD] pin outputs “High” when a phase error smaller than a cycle of [REFIN] (T) is detected for the
counter value N times consecutively.
Case of Unlock to Lock is as following.
R=1: The [LD] pin outputs “Low” when a phase error larger than a half cycle of [REFIN] (1/2T) is detected for
the counter value N times consecutively.
R>1: The [LD] pin outputs “Low” when a phase error larger than a cycle of [REFIN] (T) is detected for the counter
value N times consecutively.
The counter value N can be set by {LDP} in <Address0>. The N is different between “unlocked to locked” and
“locked to unlocked”.
Table 7 Lock Detect Precision
{LDP}
unlocked to locked
locked to unlocked
0
N=15
N=3
1
N=31
N=7
[AK1545]
MS1471-E-00 16 2012/10
The lock detect signal is shown below:
1/2T
Reference clock
This is ignored
because it cannot
be sampled.
PFD frequency signal
Divided clock of RF input signal
PFD output signal (Phase Error)
Valid
ignored
LD Output
The [LD] pin outputs HIGH when
a phase error smaller than 1/2T is
detected for N times consecutively.
Valid
Case of “R = 1”
T
Reference clock
This is ignored
because it cannot
be sampled.
Valid
PFD frequency signal
Divided clock of RF input signal
PFD output signal (Phase Error)
ignored
ignored
LD Output
The [LD] pin outputs HIGH when
a phase error smaller than T is
detected for N times consecutively.
Valid
Case of “R > 1”
Fig. 7 Digital Lock Detect Operations
[AK1545]
MS1471-E-00 17 2012/10
Phase Error < T
Flag = Flag+1
Lock ([LD]=HIGH)
Unlock ([LD]=LOW)
Yes
No
Flag > N
Flag=0
Yes
No
Fig. 8 Unlocked → Locked
Phase Error > T
Yes
Flag=0
Flag = Flag+1
Flag > N
No
Yes
Unlock ([LD]=LOW)
No
Lock ([LD]=HIGH)
PDN=0 or {PD1}=1
Fig. 9 Locked → Unlocked
[AK1545]
MS1471-E-00 18 2012/10
4．Reference counter
The reference input can be set with a dividing number in the range of 1 to 16383 using {R [13:0]}, which is an
14-bit address of {D[13:0]} in <Address0>. 0 cannot be set as a dividing number.
5．Prescaler
The dual modulus prescaler (P/P + 1) and the swallow counter are used to provide a large dividing ratio. AK1545
has a Dual modulus prescaler 32/33.
6．Power-down and Power-save mode
It is possible to operate in the power-down or power-save mode if necessary by using the external control pin.
Power On
Follow the power-up sequence.
Normal Operation
Table 8 Power-down and Power-save mode
[PDN]
<Address2>
Function
{PD2}
{PD1}
“Low”
X
X
Power Down
“High”
X
0
Normal Operation
“High”
0
1
Asynchronous Power Down
“High”
1
1
Synchronous Power Down
X : Don’t care
[AK1545]
MS1471-E-00 19 2012/10
9. Register Map
Name
Data
Address
R Counter
D18 - D0
0
0
N Counter (A and B)
0
1
Function
1
0
Initialization
1
1
Name
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Addr
ess
R Count
LDP
0
0
0
0
R
[13]
R
[12]
R
[11]
R
[10]
R
[9]
R
[8]
R
[7]
R
[6]
R
[5]
R
[4]
R
[3]
R
[2]
R
[1]
R
[0]
0x0
N Count
CPGA
IN
B
[12]
B
[11]
B
[10]
B
[9]
B
[8]
B
[7]
B
[6]
B
[5]
B
[4]
B
[3]
B
[2]
B
[1]
B
[0]
A
[4]
A
[3]
A
[2]
A
[1]
A
[0]
0x1
Func.
0
PD2
0
0
0
TIMER
[3]
TIMER
[2]
TIMER
[1]
TIMER
[0]
FAST
MODE
0
FAST
EN
CP
HiZ
CP
POLA
LD
[2]
LD
[1]
LD
[0]
PD1
CNTR
RST
0x2
Initial.
0
PD2
0
0
0
TIMER
[3]
TIMER
[2]
TIMER
[1]
TIMER
[0]
FAST
MODE
0
FAST
EN
CP
HiZ
CP
POLA
LD
[2]
LD
[1]
LD
[0]
PD1
CNTR
RST
0x3
[AK1545]
MS1471-E-00 20 2012/10
Notes for writing into registers
After powers on AK1545, [PDN] must be “0” or {PD1} must be “1”.
After powers on AK1545, the initial registers value are not defined. It is required to write the data in all addresses
in order to commit it.
[Examples of writing into registers]
(Ex. 1) Power-On
- Bring [PDN] to ”0 (Low)”
- Apply VDD
- Program Address0, Address1 and Address2
- Bring [PDN] to ”1 (High)”
(Ex. 2) Changing frequency settings : Initialization
- Program Address3
- Program Address1
(Ex. 3) Changing frequency settings : Counter reset
- Program Address2. As part of this, load “1” to both {PD1} and {CNTR_RST}.
- Program Address1
- Program Address2. As part of this, load “0” to both {PD1} and {CNTR_RST}.
(Ex. 4) Changing frequency settings : PDN pin method
- Bring [PDN] to ”0 (Low)”
- Program Address1
- Bring [PDN] to ”1 (High)”
[AK1545]
MS1471-E-00 21 2012/10
10. Function Description - Registers
< Address0 : R Counter >
D18
D[17:14]
D[13:0]
Address
LDP
0
R[13:0]
00
D[17:14] : These bits are set to the following for normal operation
D17
D16
D15
D14
0
0
0
0
LDP : Lock Detect Precision
The counter value for digital lock detect can be set.
D18
Function
Remarks
0
15 times Count
unlocked to locked
3 times Count
locked to unlocked
1
31 times Count
unlocked to locked
7 times Count
locked to unlocked
[AK1545]
MS1471-E-00 22 2012/10
R[13:0] : Reference clock division number
The following settings can be selected for the reference clock division.
The allowed range is 1 (1/1 division) to 16383 (1/16383 division). 0 cannot be set.
The maximum frequency for FPFD is 55MHz.
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
Remarks
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Prohibited
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1/1 division
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1/2 division
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1/3 division
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1/4 division
DATA
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1/16381
division
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1/16382
division
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1/16383
division
[AK1545]
MS1471-E-00 23 2012/10
< Address1 : N Counter >
D18
D[17:5]
D[4:0]
Address
CPGAIN
B[12:0]
A[4:0]
01
CPGAIN : Sets the charge pump current
D18
Function
Remarks
0
250A
1
1mA
B[12:0] : B (Programmable) counter value
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
Function
Remarks
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Prohibited
0
0
0
0
0
0
0
0
0
0
0
0
1
1 Dec
Prohibited
0
0
0
0
0
0
0
0
0
0
0
1
0
2 Dec
Prohibited
0
0
0
0
0
0
0
0
0
0
0
1
1
3 Dec
DATA
1
1
1
1
1
1
1
1
1
1
1
0
1
8189 Dec
1
1
1
1
1
1
1
1
1
1
1
1
0
8190 Dec
1
1
1
1
1
1
1
1
1
1
1
1
1
8191 Dec
A[4:0] : A (Swallow) counter value
D4
D3
D2
D1
D0
Function
Remarks
0
0
0
0
0
0
0
0
0
0
1
1 Dec
0
0
0
1
0
2 Dec
0
0
0
1
1
3 Dec
DATA
1
1
1
0
1
29 Dec
1
1
1
1
0
30 Dec
1
1
1
1
1
31 Dec
[AK1545]
MS1471-E-00 24 2012/10
* Requirements for A[4:0] and B[12:0]
The data at A[4:0] and B[12:0] must meet the following requirements:
A[4:0] ≥ 0, B[12:0] ≥ 3, B[12:0] ≥ A[4:0]
See “Frequency Setup” in section “Block Functional Descriptions” for details of the relationship
between a frequency division number N and the data at A[4:0] and B[12:0].
[AK1545]
MS1471-E-00 25 2012/10
< Address2 : Function >
D18
D17
D[16:14]
D[13:10]
D9
D8
D7
0
PD2
0
TIMER[3:0]
FASTMODE
0
FASTEN
D6
D5
D[4:2]
D1
D0
Address
CPHIZ
CPPOLA
LD[2:0]
PD1
CNTR_RST
02
PD2, PD1 : Power Down Select
[PDN]
<Address2>
Function
{PD2}
{PD1}
“Low”
X
X
Power Down
“High”
X
0
Normal Operation
“High”
0
1
Asynchronous Power Down
“High”
1
1
Synchronous Power Down
X : Don’t care
{PD2}=1 and {PD1}=1 : All circuits powers down at the timing when the Phase detector frequency
signal reverses.
{PD2}=0 and {PD1}=1 : All circuits goes into Power Down at the rise up of LE signal that latches 1 into
{PD1}.
TIMER[3:0] : Sets the Fast Lock Timer
This is enabled when { FASTMODE } =”1”, {FASTEN} = “1” and {CPGAIN}=”1”.
The charge pump current is set into high value (1mA) designate during switchover time which is set by
{TIMER[3:0]}.
The following formula shows the relationship between the switchover time and the counter value.
Switchover time = 1 / FPFD x Counter Value
Counter Value = 3 + Timer[3:0] x 4
[AK1545]
MS1471-E-00 26 2012/10
The following table shows the relationship between counter value and {TIMER[3:0]}.
D13
D12
D11
D10
Function
Remarks
0
0
0
0
3 Counts
0
0
0
1
7 Counts
0
0
1
0
11 Counts
0
0
1
1
15 Counts
0
1
0
0
19 Counts
0
1
0
1
23 Counts
0
1
1
0
27 Counts
0
1
1
1
31 Counts
1
0
0
0
35 Counts
1
0
0
1
39 Counts
1
0
1
0
43 Counts
1
0
1
1
47 Counts
1
1
0
0
51 Counts
1
1
0
1
55 Counts
1
1
1
0
59 Counts
1
1
1
1
63 Counts
FASTMODE and FASTEN : Enables or disables the Fast Lock mode
D7
D9
Function
Remarks
0
X
Fast Lock Mode disable
SW pin functions as a General Purpose Output
(GPO) which reflects a D9 register settings.
1
0
Fast Lock Mode 1
1
1
Fast Lock Mode 2
Timer is available
CPHIZ : TRI-STATE output setting for charge pump
D6
Function
Remarks
0
Charge pumps are activated.
Use this setting for normal operation.
1
TRI-STATE
Note 1)
Note 1) The charge pump output is turned OFF and put in the high-impedance (Hi-Z)
state.
[AK1545]
MS1471-E-00 27 2012/10
CPPOLA : Selects positive or negative output polarity for CP
D5
Function
Remarks
0
Negative
1
Positive
LD ： Selects output from [LD] pin
D4
D3
D2
Function
Remarks
0
0
0
Low
0
0
1
Digital lock detect
0
1
0
N divider output
0
1
1
High
1
0
0
R divider output
1
0
1
Analog lock detect
Open Drain
1
1
0
Low
1
1
1
Low
CNTR_RST : Counter Reset
D0
Function
Remarks
0
Normal operation
1
R and N counters are reset.
High
High
Charge pump output voltage
Negative
Positive
Low
Low
VCO frequency
[AK1545]
MS1471-E-00 28 2012/10
< Address3 : Initialization >
This function is same as <Address2>. When this register is programmed, the N-counter, R-counter,
FAST-counter become load-state condition and the charge pump output is three - state. Next, Writing the
address1<N-counter>, these are starting to operation.
[AK1545]
MS1471-E-00 29 2012/10
11. IC Interface Schematic
No.
Pin name
I/O
R0()
Cur(A)
Function
10
PDN
I
300
Digital input pin
R0
11
CLK
I
300
12
DATA
I
300
13
LE
I
300
4
TEST1
I
300
9
TEST2
I
300
14
LD
O
Digital output pin
1
SW
O
8
REFIN
I
300
Analog input pin
R0
[AK1545]
MS1471-E-00 30 2012/10
No.
Pin name
I/O
R0()
Cur(A)
Function
2
CP
O
Analog output pin
5
RFINN
I
21k
60
Analog input pin (RF input pin)
R0
6
RFINP
I
21k
60
[AK1545]
MS1471-E-00 31 2012/10
12. Recommended Connection Schematic of Off-Chip Component
1. Power Supply Pins
PVDD
CPVDD
LSI
AVDD
100pF
10F
0.01F
0.01F
0.01F
100pF
10F
100pF
10F
2. TEST1, TEST2
TEST1,2
LSI
3. REFIN
REFIN
LSI
100pF±10%
[AK1545]
MS1471-E-00 32 2012/10
4. RFINP、RFINN
LSI
RFINP
VCO Output
RFINN
100pF±10%
100pF±10%
51Ω
[AK1545]
MS1471-E-00 33 2012/10
13. Power-Up Timing Chart (Recommended Flow)
Note1) After VDD1 and VDD2 is powered up, the initial setting of registers is undefined.
It is required to write in Address0, 1 and 2.
Fig. 10 Power Up Sequence (Recommended)
Note2) When VDD1, VDD2 and PDN are synchronously powered up, internal sequence circuit is not
initialized. So the circuit starts working on undefined status. Therefore, register {PD1} must be
set to “1” before register setting.
Fig. 11 Power Up Sequence (VDD1/VDD2/PDN synchronous power-up)
PDN
Register Write-in
VDD1, VDD2
Internal register values are set
CP
Output
op
Hi-z
PDN
VDD1, VDD2
CP
Output
Hi-z
Register Write-in
Internal register values are set
Internal sequence circuit is initialized
Undefined
Address
0~2
Address 2
{PD1}=1
Address 0,1
Address 2
{PD1}=0
[AK1545]
MS1471-E-00 34 2012/10
14. Frequency Setting Timing Chart (Recommended Flow)
Fig. 12 Frequency settings (controlled by {PD1})
Fig. 23 Frequency settings (controlled by INITIAL register)
注) The function of Address3 is the same as Address2. Before writing in Address3, be sure to set
{PD1}=0. Access to Address3 resets CP to Hi-Z, then set Address0 and 1. Access to
Address1 restarts CP to operating.
PDN
VDD1, VDD2
CP
Output 2
Hi-z
Address 2
{PD1}=1
Power down
Address 0
setting
Address 1
setting
Address 2
Power up
{PD1}=0
Output 1
PDN
VDD1, VDD2
CP
Hi-z
Address 3
{PD1}=0
Address 0
setting
Address 1
setting
Register Write-in
Register Write-in
Output 1
Output 2
[AK1545]
MS1471-E-00 35 2012/10
15. Typical Evaluation Board Schematic
C2
AK1545
Loop Filter
C1
C3
R2
R3
CP
RFOUT
51
100pF
RFINN
VCO
RFINP
100pF
REFIN
100pF
100pF
18
18
18
SW
R2’
Fig. 34 Typical Evaluation Board Schematic
[AK1545]
MS1471-E-00 36 2012/10
16. Typical Performance Characteristics
- 1kHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
OUTPUT POWER -dB
VDD1 = 3V, VDD2 = 5V
Icp = 1mA
PFD FREQENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 0.19 SECONDS
AVERAGES = 26
REFERENCE
LEVEL = -5.27dBm
2800MHz +1kHz +2kHz- 2kHz - 1kHz
-86.6dBc/Hz
- 1kHz
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
OUTPUT POWER -dB
VDD1 = 3V, VDD2 = 5V
Icp = 1mA
PFD FREQENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 3kHz
VIDEO BANDWIDTH = 3kHz
SWEEP = 2.2 SECONDS
AVERAGES = 4
REFERENCE
LEVEL = -6.29dBm
2800MHz +1MHz +2MHz- 2MHz - 1MHz
-84.3dBc
Fig. 15 AK1545 Phase Noise (2800 MHz, 1 MHz,
100 kHz)
Fig. 17 AK1545Reference Spurs (2800 MHz, 1 MHz,
100 kHz)
VDD=3V(電池)
CPVDD=5V(5052B)
Icp=1mA
REF IN=100MHz
PDF=25kHz
LF帯域=3kHz
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
PHASE NOISE - dBc/Hz
1MHz
100Hz FREQUENCY OFFSET FROM 2.8GHz CARRIER
1.25°rms
RMS NOISE = 1.253°
10dB/DIVISION RL= -40 dBc/Hz
Fig. 16 AK1545 Integrated Phase Noise (2800 MHz,
1 MHz, 100 kHz)
[AK1545]
MS1471-E-00 37 2012/10
17. Outer Dimensions
Fig. 18 Outer Dimensions
[AK1545]
MS1471-E-00 38 2012/10
18. Marking
a. Style ： TSSOP
b. Number of pins ： 16
c. A1 pin marking ： ●
d. Product number ： 1545
e. Date code ： YWWLE (5 digits)
Y ： Lower 1 digit of calendar year
(Year 2012-> 2, 2013-> 3 ...)
WW ： Week
L ： Lot identification, given to each product lot which is made in a week
(A, B, C…)
→ LOT ID is given in alphabetical order
E ：Fixed
1545(d)
YWWLE(e)
(c)
[AK1545]
MS1471-E-00 39 2012/10
IMPORTANT NOTICE
These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi
Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor
products. You are fully responsible for the incorporation of these external circuits, application circuits,
software and other related information in the design of your equipments. AKM assumes no responsibility for
any losses incurred by you or third parties arising from the use of these information herein. AKM assumes
no liability for infringement of any patent, intellectual property, or other rights in the application or use of
such information contained herein.
Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life
support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use,
except for the use approved with the express written consent by Representative Director of AKM. As used
here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage
to person or property.
It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold
AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
2014/10
Related Parts
Part#
Discription
Comments
Mixer
AK1220
100MHz~900MHz High Linearity Down Conversion Mixer
IIP3:+22dBm
AK1222
100MHz~900MHz Low Power Down Conversion Mixer
IDD:2.9mA
AK1224
100MHz~900MHz Low Noise, High Liniarity Down Conversion Mixer
NF:8.5dB, IIP3:+18dBm
AK1228
10MHz~2GHz Up/Down Conversion Mixer
3V Supply, NF:8.5dB
AK1221
0.7GHz~3.5GHz High Linearity Down Conversion Mixer
IIP3:+25dBm
AK1223
3GHz~8.5GHz High Linearity Down Conversion Mixer
IIP3:+13dB, NF:15dB
PLL Synthesizer
AK1541
20MHz~600MHz Low Power Fractional-N Synthesizer
IDD:4.6mA
AK1542A
20MHz~600MHz Low Power Integer-N Synthesizer
IDD:2.2mA
AK1543
400MHz~1.3GHz Low Power Fractional-N Synthesizer
IDD:5.1mA
AK1544
400MHz~1.3GHz Low Power Integer-N Synthesizer
IDD:2.8mA
AK1590
60MHz~1GHz Fractional-N Synthesizer
IDD:2.5mA
AK1545
0.5GHz~3.5GHz Integer-N Synthesizer
16-TSSOP
AK1546
0.5GHz~3GHz Low Phase Noise Integer-N Synthesizer
Normalized C/N:-226dBc/Hz
AK1547
0.5GHz~4GHz Integer-N Synthesizer
5V Supply
AK1548
1GHz~8GHz Low Phase Noise Integer-N Synthesizer
Normalized C/N:-226dBc/Hz
IFVGA
AK1291
100~300MHz Analog Signal Control IF VGA w/ RSSI
Dynamic Range:30dB
integrated VCO
AK1572
690MHz~4GHz Down Conversion Mixer with Frac.-N PLL and VCO
IIP3:24dBm,
-111dBc/Hz@100kHz
AK1575
690MHz~4GHz Up Conversion Mixer with Frac.-N PLL and VCO
IIP3:24dBm,
-111dBc/Hz@100kHz
IF Reciever (2nd Mixer + IF BPF + FM Detector)
AK2364
Built-in programmable AGC+BPF, FM detector IC
IFBPF:10kHz ~ 4.5kHz
AK2365A
Built-in programmable AGC+BPF, IFIC
IFBPF:7.5kHz ~ 2kHz
Analog BB for PMR/LMR
AK2345C
CTCSS Filter, Encoder, Decoder
24-VSOP
AK2360/
AK2360A
Inverted frequency(3.376kHz/3.020kHz) scrambler
8-SON
AK2363
MSK Modem/DTMF Receiver
24-QFN
AK2346B
0.3-2.55/3.0kHz Analog audio filter,
Emphasis, Compandor, scrambler, MSK Modem
24-VSOP
AK2346A
24-QFN
AK2347B
0.3-2.55/3.0kHz Analog audio filter
Emphasis, Compandor, scrambler, CTCSS filter
24-VSOP
AK2347A
24-QFN
Function IC
AK2330
8-bit 8ch Electronic Volume
VREF can be selected for each
channel
AK2331
8-bit 4ch Electronic Volume
VREF can be selected for each
channel
Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without
notice. When you consider any use or application of AKM product stipulated in this document, please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
