Charge Pump Regulator
for Color TFT Panel
Data Sheet
ADM8832
Rev. B Document Feedback
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FEATURES
3 output voltages (+5.1 V, +15.3 V, −10.2 V) from one 3 V
input supply
Power efficiency optimized for use with TFT in mobile
phones
Low quiescent current
Low shutdown current (<1 µA)
Fast transient response
Shutdown function
Power saving during blanking period
Option to use external LDO
APPLICATIONS
Handheld instruments
TFT LCD panels
Cellular phones
FUNCTIONAL BLOCK DIAGRAM
LDO
VOLTAGE
REGULATOR
VOLTAGE
DOUBLER
DISCHARGE
C1+
C1–
VOUT
LDO IN
+5VOUT
+5VIN
C2+
C2–
C3+
C3–
+15VOUT
C4+
C4–
–10VOUT
C1
2.2µF
C6
2.2µF
C2
1µF
C7
2.2µF
+5.1V
C3
1µF
+15.3V
C8
1µF
C4
1µF
–10.2V
C9
1µF
VOLTAGE
TRIPLER
DOUBLE
TRIPLE
VOLTAGE
INVERTER
CLKIN
SCAN/
BLANK
LDO_ON/
OFF
GND
V
CC
TIMING
GENERATOR
CONTROL
LOGIC
SHUTDOWN
CONTROL
OSCILLATOR
ADM8832
C5
2.2µF
03759-A-001
SHDN
Figure 1.
GENERAL DESCRIPTION
The ADM8832 is a charge pump regulator used for color thin
film transistor (TFT) liquid crystal displays (LCD). Using charge
pump technology, the device can be used to generate three
output voltages (+5.1 V ±2%, +15.3 V, −10.2 V) from a single
3 V input supply. These outputs are then used to provide
supplies for the LCD controller (+5.1 V) and the gate drives for
the transistors in the panel (+15.3 V and −10.2 V). Only a few
external capacitors are needed for the charge pumps. An
efficient low dropout voltage regulator also ensures that the
power efficiency is high and provides a low ripple 5.1 V output.
This LDO can be shut down and an external LDO used to
regulate the 5 V doubler output and drive the input to the
charge pump section, which generates the +15.3 V and −10.2 V
outputs if so required by the user.
The ADM8832 has an internal 100 kHz oscillator for use in
scanning mode, but the part must be clocked by an external
clock source in blanking (low current) mode. The internal
oscillator is used to clock the charge pumps during scanning
mode where the current is highest. During blanking periods,
the ADM8832 switches to an external, lower frequency clock.
This allows the user to vary the frequency and maximize power
efficiency during blanking periods. The tolerances on the output
voltages are seamlessly maintained when switching from scan-
ning mode to blanking mode or vice versa.
The ADM8832 power saving features include low power
shutdown and reduced quiescent current consumption during
the blanking periods. The 5.1 V output consumes the most
power, so power efficiency is also maximized on this output
with an oscillator enabling scheme (Green Idle™). This
effectively senses the load current that is flowing and turns on
the charge pump only when charge needs to be delivered to the
5 V pump doubler output.
The ADM8832 is fabricated using CMOS technology for minimal
power consumption. The part is packaged in a 20-lead LFCSP
(lead frame chip scale package).
OBSOLETE
ADM8832 Data Sheet
Rev. B | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings ............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ..............................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 10
Scanning and Blanking .............................................................. 10
Power Sequencing ...................................................................... 10
Transient Response .................................................................... 10
External Clock ............................................................................ 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
8/2017—Rev. A to Rev. B
Changed CP-20 to CP-20-6 .......................................... Throughout
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
4/2004—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
7/2003—Revision 0: Initial Version
OBSOLETE
Data Sheet ADM8832
Rev. B | Page 3 of 12
SPECIFICATIONS
VCC = 2.6 V to 3.6 V, TA = −40°C to +85°C, unless otherwise noted; C1, C5, C6, C7 = 2.2 µF, C2, C3, C4, C8, C9 = 1 µF, CLKIN = 1 kHz in
blanking mode.
Table 1.
Parameter Min Typ Max Unit Test Conditions
INPUT VOLTAGE, VCC 2.6 3.6 V
SUPPLY CURRENT, ICC 150 400 µA Unloaded, Scanning Period
70 140 µA Unloaded, Blanking Period
1 µA Shutdown Mode, TA = 25°C
+5.1 V OUTPUT
Output Voltage 5.0 5.1 5.2 V IL = 10 µA to 8 mA
Output Current 4 5 mA Scanning Period
5 8 mA Scanning Period, VCC > 2.7 V
50 200 µA Blanking Period
Power Efficiency 80 % VCC = 3 V, IL = 5 mA (Scanning)
70
%
V
CC
= 3 V, I
L
= 200 µA (Blanking)
Output Ripple 10 mV p-p 8 mA Load
Transient Response 5 µs IL Stepped from 10 µA to 8 mA
+15.3 V OUTPUT
Output Voltage 14.4 15.3 15.6 V IL = 1 µA to 100 µA
Output Current 50 100 µA Scanning Period
1 10 µA Blanking Period
Output Ripple 50 mV p-p IL = 100 µA
−10.2 V OUTPUT
Output Voltage −10.4 −10.2 −9.6 V IL = –1 µA to −100 µA
Output Current −100 −50 µA Scanning Period
−10
−1
µA
Blanking Period
Output Ripple 50 mV p-p IL = –100 µA
POWER EFFICIENCY 90 % Relative to 5.1 V Output, IL = 100 µA (Scanning)
(+15.3 V and −10.2 V Outputs)
80
%
Relative to 5.1 V Output, I
L
= 10 µA (Blanking)
CHARGE PUMP FREQUENCY 60 100 140 kHz Scanning Period
CONTROL PINS
SHDN
Input Voltage, VSHDN 0.3 VCC V SHDN Low = Shutdown Mode
0.7 VCC V SHDN High = Normal Mode
Digital Input Current
±1
µA
Digital Input Capacitance1 10 pF
SCAN/BLANK
Input Voltage 0.3 VCC V Low = BLANK Period
0.7 VCC V High = SCAN Period
Digital Input Current
±1
µA
Digital Input Capacitance1 10 pF
LDO_ON/OFF
Input Voltage 0.3 VCC V Low = External LDO
0.7 VCC V High = Internal LDO
Digital Input Current ±1 µA
Digital Input Capacitance1 10 pF
OBSOLETE
ADM8832 Data Sheet
Rev. B | Page 4 of 12
Parameter Min Typ Max Unit Test Conditions
CLKIN
Minimum Frequency 0.9 1 kHz Duty Cycle = 50%, Rise/Fall Times = 20 ns
Input Voltage
VIL 0.3 VCC V
V
IH
0.7 V
CC
V
Digital Input Current ±1 µA
Digital Input Capacitance1 10 pF
1 Guaranteed by design. Not 100% production tested.
TIMING SPECIFICATIONS
VCC = 2.6 V to 3.6 V, TA = –40°C to +85°C, unless otherwise noted; C1, C5, C6, C7 = 2.2 µF, C2, C3, C4, C8, C9 = 1 µF, CLKIN = 1 kHz in
blanking mode.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER-UP SEQUENCE
+5 V Rise Time, tR5V 300 µs 10% to 90%, Figure 17
+15 V Rise Time, tR15V 8 ms 10% to 90%, Figure 17
−10 V Fall Time, t
F10V
12
ms
90% to 10%, Figure 17
Delay between −10 V Fall and +15 V, tDELAY 3 ms Figure 17
POWER-DOWN SEQUENCE
+5 V Fall Time, tF5V 75 ms 90% to 10%, Figure 17
+15 V Fall Time, tF15V 40 ms 90% to 10%, Figure 17
−10 V Rise Time, tR10V 40 ms 10% to 90%, Figure 17
OBSOLETE
Data Sheet ADM8832
Rev. B | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Ratings
Supply Voltage −0.3 V to +4.0 V
Input Voltage to Digital Inputs −0.3 V to +4.0 V
Output Short Circuit Duration to GND 10 sec
Output Voltage
+5.1 V Output −0.3 V to +6 V
−10.2 V Output −12 V to +0.3 V
+15.3 V Output
−0.3 V to +17 V
Operating Temperature Range −40°C to +85°C
Power Dissipation
(Derate 33 mW/°C above 25°C)
3.55 W
Storage Temperature Range −65°C to +150°C
ESD Class I
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL CHARACTERISTICS
20-Lead LFCSP:
θJA = 31°C/W
ESD CAUTION
OBSOLETE
ADM8832 Data Sheet
Rev. B | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
03759-A-002
C4–
C2+
C2–
C3+
C3–
+15VOUT
CLKIN
SCAN/BLANK
SHDN
LDO_ON/OFF
+5VIN
+5VOUT
LDO_IN
VOUT
V
CC
C1+
C1–
GND
–10VOUT
C4+
14
13
12
1
3
4
15
11
2
5
7
6
8
9
10
19
20
18
17
16
ADM8832
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Function
1
V
CC
Positive Supply Voltage Input. Connect this pin to 3 V supply with a 2.2 µF decoupling capacitor.
2 VOUT Voltage Doubler Output. This is derived by doubling the 3 V supply. A 2.2 µF capacitor to ground is required on
this pin.
3 LDO_IN Voltage Regulator Input. The user has the option to bypass this circuit using the LDO_ON/OFF pin.
4 +5VOUT +5.1 V Output Pin. This is derived by doubling and regulating the +3 V supply. A 2.2 µF capacitor to ground is
required on this pin to stabilize the regulator.
5 +5VIN +5.1 V Input Pin. This is the input to the voltage tripler and doubler inverter charge pump circuits.
6 LDO_ON/OFF Control Logic Input. 3 V CMOS logic. A logic high selects the internal LDO for regulation of the 5 V voltage
doubler output. A logic low isolates the internal LDO from the rest of the charge pump circuits. This allows the
use of an external LDO to regulate the 5 V voltage doubler output. The output of this LDO is then fed back into
the voltage tripler and doubler/inverter circuits of the ADM8832.
7 SHDN Digital Input. 3 V CMOS logic. Active low shutdown control. This pin shuts down the timing generator and
enables the discharge circuit to dissipate the charge on the voltage outputs, thus driving them to 0 V.
8 SCAN/BLANK Drive Mode Input. 3 V CMOS logic. A logic high places the part in scan (high current) mode, and the charge
pump is driven by the internal oscillator. A logic low places the part in blanking (low current) mode, and the
charge pump is driven by the (slower) external oscillator. This is a power saving feature on the ADM8832.
9 CLKIN External CLOCK Input. During a blanking period, the oscillator circuit selects this pin to drive the charge pump
circuit. This is at a lower frequency than the internal oscillator, resulting in lower quiescent current
consumption, thus saving power.
10 +15VOUT +15.3 V Output Pin. This is derived by tripling the +5.1 V regulated output. A 1 µF capacitor is required on
this pin.
11, 12 C3−, C3+ External capacitor C3 is connected between these pins. A 1 µF capacitor is recommended.
13, 14 C2−, C2+ External capacitor C2 is connected between these pins. A 1 µF capacitor is recommended.
15, 16 C4−, C4+ External capacitor C4 is connected between these pins. A 1 µF capacitor is recommended.
17 −10VOUT −10.2 V Output Pin. This is derived by doubling and inverting the +5.1 V regulated output. A 1 µF capacitor is
required on this pin.
18 GND Device Ground Pin.
19, 20 C1−, C1+ External capacitor C1 is connected between these pins. A 2.2 µF capacitor is recommended.
OBSOLETE
Data Sheet ADM8832
Rev. B | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
03759-A-003
OUTPUT CURRENT (µA)
19010 5030 9070 150130110 170
LDO POWER EFFICIENCY (%)
90
60
70
50
40
30
20
10
Figure 3. LDO Efficiency in Blanking Mode with VCC = 3 V
03759-A-004
BLANKING FREQUENCY (Hz)
10000100 1000
LDO OUTPUT VOLTAGE (V)
5.0752
5.0744
5.0746
5.0748
5.0750
5.0742
5.0740
5.0738
5.0736
5.0734
Figure 4. LDO Output Voltage (Unloaded) vs.
Blanking Mode Frequency
03759-A-005
I
LOAD
(mA)
801234567
LDO O/P (V)
5.104
5.102
5.100
5.098
5.096
5.094
5.092
5.090
Figure 5. LDO O/P Voltage vs.
Load Current in Scanning Mode, VCC = 3.3 V
03759-A-006
OUTPUT CURRENT (mA)
80 1 2 3 4 5 6 7
LDO POWER EFFICIENCY (%)
85
84
83
82
81
80
79
78
Figure 6. LDO Efficiency in Scanning Mode with VCC = 3 V
03759-A-007
OUTPUT CURRENT (µA)
102 4 6 8
+15V/–10V EFFICIENCY (%)
100
90
80
70
60
Figure 7. +15 V/−10 V Efficiency vs.
Output Current in Blanking Mode, VCC = 3 V
03759-A-008
OUTPUT CURRENT (µA)
1000 20 40 60 80
+15/–10V EFFICIENCY (%)
100
90
80
70
60
50
40
Figure 8. +15 V/−10 V Efficiency vs.
Output Current in Scanning Mode, VCC = 3 V
OBSOLETE
ADM8832 Data Sheet
Rev. B | Page 8 of 12
03759-A-009
V
CC
(V)
3.62.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
5.0V O/P (V)
5.30
5.25
5.20
5.15
5.10
5.05
4.90
5.00
4.95
DEVICE 1 @ –40°C
DEVICE 1 @ +25°C
DEVICE 1 @ +85°C
Figure 9. LDO Variation over Supply and Temperature
03759-A-010
V
CC
(V)
3.62.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
SUPPLY CURRENT (µA)
300
250
200
150
100
50
0
ICC (BLANK)
ICC (SCAN)
Figure 10. Supply Current vs. Voltage
03759-A-011
CH1 20.0mV
CH3 50.0mV
CH2 100mV M20.0µs CH1 –2.8mV
3
T
T
T
1
2
TEK STOP: 2.50MS/s
T
[ ]
23 ACQS
5V OUTPUT RIPPLE
VOUT
VCC RIPPLE
Figure 11. Output Ripple on LDO (5 V Output)
03759-A-012
T
T
CH1 20.0mV CH2 2.00V M5.00µs CH2 1.20V
1
2
TEK STOP: SINGLE SEQ
T
[ ]
10.0MS/s
LOAD ENABLE
5V OUTPUT
Figure 12. 5 V Output Transient Response for Max load Current
03759-A-013
T
T
CH1 20.0mV CH2 2.00V M5.00µs CH2 1.20V
1
2
TEK STOP: SINGLE SEQ
T
[ ]
10.0MS/s
LOAD DISABLE
5V OUTPUT
Figure 13. 5 V Output Transient Response, Load Disconnected
03759-A-014
T
T
T
CH1 5.00V
CH3 5.00V
CH2 5.00V M10.0ms CH2 1.3V
2
1
TEK STOP: SINGLE SEQ
T
[ ]
5.00KS/s
+15V OUTPUT
–10V OUTPUT
5VOUT
Figure 14. +15 V and −10 V Outputs at Power-Up
OBSOLETE
Data Sheet ADM8832
Rev. B | Page 9 of 12
03759-A-015
T
T
T
CH1 5.00V
CH3 5.00V
CH2 5.00V M10.0ms CH1 0V
1
2
TEK STOP: 500S/s
T
[ ]
5 ACQS
+15V OUTPUT
–10V OUTPUT
5VOUT
Figure 15. +15 V and −10 V Outputs at Power-Down (Unloaded)
03759-A-016
TEMPERATURE (°C)
90–40 –20 0 20 40 60
DISSIPATED POWER (mW)
20.1
20.0
19.9
19.8
19.7
19.6
19.5
19.4
Figure 16. Power Dissipation over Temperature, VCC = 3.6 V, Scanning Mode
with All O/Ps at Maximum Load
OBSOLETE
ADM8832 Data Sheet
Rev. B | Page 10 of 12
THEORY OF OPERATION
SCANNING AND BLANKING
A TFT LCD panel is made up of a bank of capacitors, each
representing a pixel in the display. These capacitors store
different levels of charge, depending on the amount of
luminescence required for a given pixel. When a picture is
displayed on the panel, a scan of all the pixel capacitors is
performed, placing different levels of charge on each in order to
create the image. The process of updating the display like this is
called scanning. Once scanned, an image is held by pixel
capacitance, and the controller and source line drivers can be
put into a low power mode. This low power mode is referred to
as the blanking mode on the ADM8832. Over a finite period of
time, this pixel charge will leak and the capacitors will need to
be refreshed in order to maintain the image.
The ADM8832 uses scanning and blanking modes, as follows.
When the TFT LCD panel is in scanning mode, a logic high on
the SCAN/BLANK input places the device in high current
power mode, providing extra power (extra current) to the LCD
controller and the source line drivers. If the panel continues to
be updated (as when a moving picture is being displayed), the
ADM8832 can be continually operated in scanning mode. If the
same image is kept on the panel, a logic low is applied to the
SCAN/BLANK input, and the ADM8832 enters blanking (low
current) mode. Depending on how often the image is updated,
the ADM8832 can be operated with a variable SCAN/ BLANK
duty cycle. This helps to maximize power efficiency and,
therefore, extends the battery life.
POWER SEQUENCING
The gate drive supplies must be sequenced such that the −10 V
supply is up before the +15 V supply for the TFT panel to power
on correctly. The ADM8832 controls this sequence. When the
device is turned on (a logic high on SHDN), the ADM8832
allows the −10 V output to ramp immediately, but holds off the
+15 V output. It continues to do this until the negative output
reaches −3 V. At this point, the positive output is enabled and
allowed to ramp up to +15 V. This sequence is shown in Figure 17.
VCC
LOAD
S
CAN/BLAN
K
EXTERNAL
CLOCK
SHDN
+5V
+15V
–10V 90%
10%
10%
90%
03759-A-018
t
F15V
t
F5V
t
R5V
t
R15V
t
R15V
t
F10V
t
R10V
–3V
Figure 17. Power Sequence
TRANSIENT RESPONSE
The ADM8832 features extremely fast transient response,
making it very suitable for fast image updates on TFT LCD
panels. This means that even under changing load conditions
there is still very effective regulation of the 5 V output. Figure 12
and Figure 13 show how the 5.1 V output responds when a
maximum load is dynamically connected and disconnected.
Note that the output settles within 5 μs to less than 1% of the
output level.
EXTERNAL CLOCK
The ADM8832 has an internal 100 kHz oscillator, but an
external clock source can also be used to clock the part. This
clock source must be applied to the CLKIN pin. Power is saved
during blanking periods by disabling the internal oscillator and
by switching to the lower frequency external clock source. To
achieve optimum performance of the charge pump circuitry, it
is important that the duty cycle of the external clock source is
50% and that the rise and fall times are less than 20 ns.
90%
10%
t
R
: RISE TIME
t
F
: FALL TIME
t
H
t
T
@ 100% = DUTY CYCLE
03759-A-017
t
R
t
F
t
H
t
T
Figure 18. Duty Cycle of External Clock
SOLDER MASK
BOARD METALLIZATION
03759-A-019
0.500
0.750 0.100
0.280 0.400
0.900
0.050
1.950
2.100
0.2500.2000.875
Figure 19. Suggested LFCSP 4 mm × 4mm 20 Lead Land Pattern
OBSOLETE
Data Sheet ADM8832
Rev. B | Page 11 of 12
OUTLINE DIMENSIONS
0.80
0.75
0.70
2.30
2.10 SQ
2.00
0.50
BSC
0.65
0.60
0.55
0.30
0.25
0.18
BOTTOM VIEW
TOP VIEW
EXPOSED
PAD
4.10
4.00 SQ
3.90
0.05 MAX
0.02 NOM
0.203 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
1
20
6
10
11
15
16
5
PKG-003763
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-1
PIN 1
INDIC AT OR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
02-13-2017-B
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
SEATING
PLANE
Figure 20. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADM8832ACPZ −40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP] CP-20-6
ADM8832ACPZ-REEL −40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP] CP-20-6
ADM8832ACPZ-REEL7
−40°C to +85°C
20-Lead Frame Chip Scale Package [LFCSP]
CP-20-6
ADM8832-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
OBSOLETE
