PM25LD010-SCE - Integrated Silicon Solutions

Pm25LD512/010/ 020

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DRAFT Date: August, 2010, Rev:0.4

FEATURES

• Single Power Supply Operation

- Low voltage range: 2.3 V – 3.6 V

• Memory Organization

- Pm25LD512: 64K x 8 (512 Kbit)

- Pm25LD010: 128K x 8 (1 Mbit)

- Pm25LD020: 256K x 8 (2 Mbit)

• Cost Effective Sector/Block Architecture

- 512Kb : Uniform 4KByte sectors / Two uniform

32KByte blocks

- 1Mb : Uniform 4KByte sectors / Four uniform

32KByte blocks

- 2Mb : Uniform 4KByte sectors / Four uniform

64KByte blocks

• Low standby current 1uA (Typ)

• Serial Peripheral Interface (SPI) Compatible

- Supports single- or dual-output

- Supports SPI Modes 0 and 3

- Maximum 33 MHz clock rate for normal read

- Maximum 100 MHz clock rate for fast read

• Page Program (up to 256 Bytes) Operation

- Typical 2 ms per page program

• Sector, Block or Chip Erase Operation

- Maximum 10 ms sector, block or chip erase

• Low Power Consumption

- Typical 10 mA active read current

- Typical 15 mA program/erase current

• Hardware Write Protection

- Protect and unprotect the device from write

operation by Write Protect (WP#) Pin

• Software Write Protection

- The Block Protect (BP2, BP1, BP0) bits allow

partial or entire memory to be configured as read-

only

• High Product Endurance

- Guaranteed 200,000 program/erase cycles per

single sector

- Minimum 20 years data retention

• Industrial Standard Pin-out and Package

- 8-pin 150mil SOIC

- 8-pin 208mil SOIC for Pm25LD040

- 8-pin 300mil PDIP for Pm25LD040

- 8-contact WSON

- 8-pin TSSOP

- Lead-free (Pb-free), halogen-free package

GENERAL DESCRIPTION

The Pm25LD512/010/020 are 512Kbit/ 1Mbit / 2Mbit Serial Peripheral Interface (SPI) Flash memories, providing

single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100

MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide operating

voltage ranging from 2.3 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be

programmed in standard EPROM programmers.

The Pm25LD512/010/020 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output

(SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all

recognized command codes and operations. The dual-output fast read operation provides and effective serial

data rate of 200MHz.

The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in

one program operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte

blocks.(Pm25LD020 is uniform 4 KByte sectors or uniform 64 KByte).

The Pm25LD512/010/020 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are

offered in 8-pin SOIC 150mil, 8-contact WSON and 8-pin TSSOP. The devices operate at wide temperatures

between -40°C to +105°C.

512Kbit/

1

Mbit /

2

Mbit Single

Operating Voltage Serial

Flash Memory With 100 MHz Dual-Output SPI Bus

Interface

Pm25LD512/010/ 020

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PRODUCT ORDERING INFORMATION

Pm25LDxxx - S C E

Environmental Attribute

E = Lead-free (Pb-free) and Halogen- free

package

Temperature Range

C = Commercial Grade (-40°C to +105°C)

Package Type

S = 8-pin SOIC 150mil (8S)

B = 8-pin SOIC 208mil (8B)

P = 8-pin PDIP 300 mil (8P)

K = 8-contact WSON (8K)

pFlash Device Number

Pm25LD512/010/020

Part Number Operating Frequency (MHz)

Package Temperature Range

Pm25LD512-SCE

Pm25LD010-SCE

Pm25LD020-SCE

100 8S

150mil SOIC

Pm25LD512-KCE

Pm25LD010-KCE

Pm25LD020-KCE

100

8K WSON

(Back Side

Metal)

Pm25LD040-PCE 100

8P 300mil PDIP

Pm25LD040-BCE 100

8B 208mil SOIC

Pm25LD512-DCE

Pm25LD010-DCE

Pm25LD020-DCE

100

8-pin TSSOP

Commercial Grade

(-40

o

C to +105

o

C)

Pm25LD512/010/ 020

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CONNECTION DIAGRAMS

5

6

7

81

2

3

4

Vcc

HOLD#

SCK

SIO

SO

GND

WP#

CE#

5

6

7

81

2

3

4

Vcc

HOLD#

SCK

SIO

SO

GND

WP#

CE#

PIN DESCRIPTIONS

SYMBOL

TYPE DESCRIPTION

CE# INPUT

Chip Enable: CE# low activates the devices internal circuitries for

device operation. CE# high deselects the devices and switches into

standby mode to reduce the power consumption. When a device is not

selected, data will not be accepted via the serial input pin (SlO), and the

serial output pin (SO) will remain in a high impedance state.

SCK INPUT Serial Data Clock

SIO INPUT/OUTPUT

Serial Data Input/Output

SO OUTPUT Serial Data Output

GND Ground

Vcc Device Power Supply

WP# INPUT Write Protect: A hardware program/erase protection for all or part of a

memory array. When the WP# pin is low, memory array write-protection depends

on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is

high, the devices are not write-protected.

HOLD# INPUT Hold: Pause serial communication by the master device without resetting

the serial sequence.

CE#

SO

WP#

GND

Vcc

HOLD#

SCK

SIO

SCK

HOLD#

Vcc

SO

WP#

GND

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

8

-

Pin SOIC

8

-

Contact WSON

8

-

Pin TSSOP

8

-

PDIP

Pm25LD512/010/ 020

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BLOCK DIAGRAM

SIO

Pm25LD512/010/ 020

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SPI MODES DESCRIPTION

Multiple Pm25LD512/010/020 devices can be

connected on the SPI serial bus and controlled by a

SPI Master, i.e. microcontroller, as shown in Figure 1.

The devices support either of two SPI modes:

Mode 0 (0, 0)

Mode 3 (1, 1)

The difference between these two modes is the clock

polarity when the SPI master is in Stand-by mode: the

serial clock remains at “0” (SCK = 0) for Mode 0 and

the clock remains at “1” (SCK = 1) for Mode 3. Please

refer to Figure 2. For both modes, the input data is

latched on the rising edge of Serial Clock (SCK), and

the output data is available from the falling edge of

SCK.

Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

Figure 2. SPI Modes Supported

MSb

SCK

SO

SIO

Input mode

Mode 0 (0,

0)

Mode 3 (1,

1)

SPI Master

(i.e. Microcontroller)

CS3 CS2 CS1

SPI Memory

Device

SPI Memory

Devic

e

SPI Memory

Device

SPI Interface with

(0,0) or (1,1)

SD

I

O

SDI

SCK

SO

SI

O

SI

O

S

IO

CE#

WP#

HOLD#

Note: 1.

The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as

Pm25LD512/010/ 020

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SYSTEM CONFIGURATION

The Pm25LD512/010/020 devices are designed to interface directly with the synchronous Serial Peripheral

Interface (SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system

controllers. The devices have two superset features that can be enabled through specific software instructions

and the Configuration Register:

Block No. Block Size

(Kbytes) Sector No. Sector Size

(Kbytes) Address Range

Sector 0

(1)

4000000h - 000FFFh

Sector 1 4001000h - 001FFFh

: : :

Sector 7 4007000h - 007FFFh

Sector 8 4008000h - 008FFFh

Sector 9 4009000h - 009FFFh

: : 000000h - 006FFFh

Sector 15 400F000h - 00FFFFh

Block 2 32 ""010000h - 017FFFh

Block 3 32 ""018000h - 01FFFFh

Memory Density

1 Mbit

512 Kbit

32

Block 0

Block 1

Table 1-1. Block/Sector Addresses of Pm25LD512/010/020

Memory Density Block No.

Block

Size

(KBytes)

Sector No.

Sector

Size

(KBytes)

Address Range

Sector 0 4 000000h - 000FFFh

Sector 1 4 001000h - 001FFFh

: : :

Block 0 64

Sector 15 4 00F000h - 00FFFFh

Sector 16 4 010000h - 010FFFh

Sector 17 4 011000h - 011FFFh

: : :

Block 1 64

Sector 31 4 01F000h - 01FFFFh

: : : : :

2 Mbit

Block 3 64 : 4 030000h – 03FFFFh

Pm25LD512/010/ 020

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REGISTERS (CONTINUED)

STATUS REGISTER

Refer to Tables 5 and 6 for Status Register Format and

Status Register Bit Definitions.

The BP0, BP1, BP2, and SRWD are volatile memory

cells that can be written by a Write Status Register

(WRSR) instruction. The default value of the BP2, BP1,

BP0 were set to “0” and SRWD bits was set to “0” at

factory. Once a “0” or “1”is written, it will not be

changed by device power-up or power-down, and can

only be altered by the next WRSR instruction. The

Status Register can be read by the Read Status

Register (RDSR). Refer to Table 10 for Instruction Set.

The function of Status Register bits are described as

follows:

WIP bit: The Write In Progress (WIP) bit is read-only,

and can be used to detect the progress or completion

of a program or erase operation. When the WIP bit is

“0”, the device is ready for a write status register,

program or erase operation. When the WIP bit is “1”,

the device is busy.

WEL bit: The Write Enable Latch (WEL) bit indicates

the status of the internal write enable latch. When the

WEL is “0”, the write enable latch is disabled, and all

write operations, including write status register, page

program, sector erase, block and chip erase operations

are inhibited. When the WEL bit is “1”, write operations

are allowed. The WEL bit is set by a Write Enable

(WREN) instruction. Each write register, program and

erase instruction must be preceded by a WREN

instruction. The WEL bit can be reset by a Write

Disable (WRDI) instruction. It will automatically be the

reset after the completion of a write instruction.

BP2, BP1, BP0 bits: The Block Protection (BP2, BP1,

BP0) bits are used to define the portion of the memory

area to be protected. Refer to Tables 7, 8 and 9 for the

Block Write Protection bit settings. When a defined

combination of BP2, BP1 and BP0 bits are set, the

corresponding memory area is protected. Any program

or erase operation to that area will be inhibited. Note:

a Chip Erase (CHIP_ER) instruction is executed

successfully only if all the Block Protection Bits are set

as “0”s.

SRWD bit: The Status Register Write Disable (SRWD)

bit operates in conjunction with the Write Protection

(WP#) signal to provide a Hardware Protection Mode.

When the SRWD is set to “0”, the Status Register is

not write-protected. When the SRWD is set to “1” and

the WP# is pulled low (V

IL

), the volatile bits of Status

Register (SRWD, BP2, BP1, BP0) become read-only,

and a WRSR instruction will be ignored. If the SRWD is

set to “1” and WP# is pulled high (V

IH

), the Status

Register can be changed by a WRSR instruction.

Table 5. Status Register Format

Bit 7 Bit 6 Bit 5

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SRWD1

Reserved BP2 BP1 BP0 WEL WIP

Default (flash bit)

0 0 0 0 0 0 0

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REGISTERS (CONTINUED)

Table 6. Status Register Bit Definition

Bit Name

Definition Read-

/Write

Non-Volatile

bit

Bit 0 WIP

Write In Progress Bit:

"0" indicates the device is ready

"1" indicates a write cycle is in progress and the device is busy

R No

Bit 1 WEL

Write Enable Latch:

"0" indicates the device is not write enabled

"1" indicates the device is write enabled (default)

R/W No

Bit 2 BP0

Bit 3 BP1

Bit 4 BP2

Block Protection Bit: (See Table 7 and Table 8 for details)

"0" indicates the specific blocks are not write-protected (default)

"1" indicates the specific blocks are write-protected

R/W Yes

Bits 5 - 6

N/A Reserved: Always "0"s N/A

Bit 7 SRWD

Status Register Write Disable: (See Table 9 for details)

"0" indicates the Status Register is not write-protected (default)

"1" indicates the Status Register is write-protected

R/W Yes

Table 8. Block Write Protect Bits for Pm25LD512/010/020

BP1 BP0 Pm25LD512A Pm25LD010A Pm25LD020

0 0 None None None

0 1 None

Upper quarter (Block 3)

018000h - 01FFFFh

Upper quarter (Block 3)

030000h - 03FFFFh

1 0 None

Upper half (Block 2 & 3)

010000h - 01FFFFh

Upper half (Block 2 & 3)

020000h - 03FFFFh

1 1

All Blocks

000000h - 00FFFFh

All Blocks

000000h - 01FFFFh

All Blocks

000000h - 03FFFFh

Status Register Bits Protected Memory Area

Pm25LD512/010/ 020

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REGISTERS (CONTINUED)

PROTECTION MODE

The Pm25LD512/010/020 have two types of write-

protection mechanisms: hardware and software.

These are used to prevent irrelevant operation in a

possibly noisy environment and protect the data

integrity.

HARDWARE WRITE-PROTECTION

The devices provide two hardware write-protection

features:

a. When inputting a program, erase or write status

register instruction, the number of clock pulse is

checked to determine whether it is a multiple of eight

before the executing. Any incomplete instruction

command sequence will be ignored.

b. The Write Protection (WP#) pin provides a

hardware write protection method for BP2, BP1, BP0

and SRWD in the Status Register. Refer to the

STATUS REGISTER description.

c. Write inhibit is 1.8V, all write sequence will be

ignored when Vcc drop to 1.8V and lower

SOFTWARE WRITE PROTECTION

The Pm25LD512/010/020 also provides two software

write protection features:

a. Before the execution of any program, erase or write

status register instruction, the Write Enable Latch

(WEL) bit must be enabled by executing a Write

Enable (WREN) instruction. If the WEL bit is not

enabled first, the program, erase or write register

instruction will be ignored.

b. The Block Protection (BP2, BP1, BP0) bits allow part

or the whole memory area to be write-protected.

Table 9. Hardware Write Protection on Status

Register

SRWD

WP# Status Register

0 Low Writable

1 Low Protected

0 High Writable

1 High Writable

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DEVICE OPERATION

The Pm25LD512/010/020 utilize an 8-bit instruction

register. Refer to Table 10 Instruction Set for details of

the Instructions and Instruction Codes. All instructions,

addresses, and data are shifted in with the most

significant bit (MSB) first on Serial Data Input (SI). The

input data on SI is latched on the rising edge of Serial

Clock (SCK) after Chip Enable (CE#) is driven low (V

IL

).

Every instruction sequence starts with a one-byte

instruction code and is followed by address bytes, data

bytes, or both address bytes and data bytes,

depending on the type of instruction. CE# must be

driven high (V

IH

) after the last bit of the instruction

sequence has been shifted in.

The timing for each instruction is illustrated in the

following operational descriptions.

Table 10. Instruction Set

Instruction Name Hex

Code

Operation Command

Cycle

Maximum

Frequency

RDID ABh

Read Manufacturer and Product ID 4 Bytes 100 MHz

JEDEC ID READ 9Fh Read Manufacturer and Product ID by JEDEC ID

Command

1 Byte

100 MHz

RDMDID 90h Read Manufacturer and Device ID 4 Bytes 100 MHz

WREN 06h Write Enable 1 Byte

100 MHz

WRDI 04h Write Disable 1 Byte

100 MHz

RDSR 05h Read Status Register 1 Byte

100 MHz

WRSR 01h Write Status Register 2 Bytes

100 MHz

READ 03h Read Data Bytes from Memory at Normal Read Mode

4 Bytes

33 MHz

FAST_READ 0Bh

Read Data Bytes from Memory at Fast Read Mode 5 Bytes

100 MHz

FRDO 3Bh

Fast Read Dual Output 5 Bytes

100 MHz

PAGE_ PROG 02h Page Program Data Bytes Into Memory 4 Bytes +

256B

50 MHz

SECTOR_ER D7h/

20h

Sector Erase 4 Bytes

100 MHz

BLOCK_ER D8h

Block Erase 4 Bytes

100 MHz

CHIP_ER C7h/

60h

Chip Erase 1 Byte

100 MHz

HOLD OPERATION

HOLD# is used in conjunction with CE# to select

the Pm25LD512/010/020. When the devices are

selected and a serial sequence is underway,

HOLD# can be used to pause the serial

communication with the master device without

resetting the serial sequence. To pause, HOLD# is

brought low while the SCK signal is low. To resume

serial communication, HOLD# is brought high while

the SCK signal is low (SCK may still toggle during

HOLD). Inputs to SlO will be ignored while SO is in

the high impedance state.

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DEVICE OPERATION (CONTINUED)

RDID COMMAND (READ PRODUCT

IDENTIFICATION) OPERATION

The Read Product Identification (RDID) instruction is

for reading out the old style of 8-bit Electronic

Signature, whose values are shown as table of ID

Definitions. This is not same as RDID or JEDEC ID

instruction. It’s not recommended to use for new

design. For new design, please use RDID or JEDEC ID

instruction.

The RDES instruction code is followed by three dummy

bytes, each bit being latched-in on SI during the rising

edge of SCK. Then the Device ID is shifted out on SO

with the MSB first, each bit been shifted out during the

falling edge of SCK. The RDES instruction is ended by

CE# goes high. The Device ID outputs repeatedly if

continuously send the additional clock cycles on SCK

while CE# is at low.

Table 11. Product Identification

Product Identification Data

First Byte 9Dh

Manufacturer ID Second Byte 7Fh

Device ID: Device ID 1 Device ID 2

Pm25LD512 05h 20h

Pm25LD010 10h 21h

Pm25LD020 11h 22h

Figure 3. Read Product Identification Sequence

0 1 8 31 38 39 46 47 54

HIGH IMPEDANCE

Device ID1 Device ID1 Device ID1

SCK

CE#

SI

SO

INSTRUCTION

97

1010 1011b

3 Dummy Bytes

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DEVICE OPERATION (CONTINUED)

JEDEC ID READ COMMAND (READ PRODUCT IDENTIFICATION BY JEDEC ID)

OPERATION

The JEDEC ID READ instruction allows the user to

read the manufacturer and product ID of devices. Refer

to Table 11 Product Identification for pFlash

Manufacturer ID and Device ID. After the JEDEC ID

READ command is input, the second Manufacturer ID

(7Fh) is shifted out on SO with the MSB first, followed

by the first Manufacturer ID (9Dh) and the Device ID

(22h, in the case of the Pm25LD020), each bit shifted

out during the falling edge of SCK. If CE# stays low

after the last bit of the Device ID is shifted out, the

Manufacturer ID and Device ID will loop until CE# is

pulled high.

Figure 4. Read Product Identification by JEDEC ID READ Sequence

SCK

CE#

SI

INSTRUCTION

1001 1111b

0815 23 24 317 16

HIGH IMPEDANCE

SO Device ID2Manufacture ID1Manufacture ID2

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DEVICE OPERATION (CONTINUED)

RDMDID COMMAND (READ DEVICE MANUFACTURER AND DEVICE ID)

OPERATION

The RDMDID instruction allows the user to read the

manufacturer and product ID of devices. Refer to Table

11 Product Identification for pFlash Manufacturer ID

and Device ID. The RDMDID command is input,

followed by a 24-bit address pointing to an ID table.

The table contains the first Manufacturer ID (9Dh) and

the Device ID (22h, in the case of the Pm25LD020),

and is shifted out on SO with the MSB first, each bit

shifted out during the falling edge of SCK. If CE# stays

low after the last bit of the Device ID is shifted out, the

Manufacturer ID and Device ID will loop until CE# is

pulled high.

Figure 5. Read Product Identification by RDMDID READ Sequence

Pm25LD512/010/ 020

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Note :

(1) ADDRESS A0 = 0, will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh)

ADDRESS A0 = 1, will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh)

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DEVICE OPERATION (CONTINUED)

WRITE ENABLE OPERATION

The Write Enable (WREN) instruction is used to set the

Write Enable Latch (WEL) bit. The WEL bit of the

Pm25LD512/010/020 is reset to the write –protected

state after power-up. The WEL bit must be write

enabled before any write operation, including sector,

block erase, chip erase, page program and write status

register operations. The WEL bit will be reset to the

write-protect state automatically upon completion of a

write operation. The WREN instruction is required

before any above operation is executed.

Figure 6. Write Enable Sequence

WRDI COMMAND (WRITE DISABLE) OPERATION

The Write Disable (WRDI) instruction resets the WEL

bit and disables all write instructions. The WRDI

instruction is not required after the execution of a write

instruction, since the WEL bit is automatically reset.

Figure 7. Write Disable Sequence

SI

O

SIO

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DEVICE OPERATION (CONTINUED)

RDSR COMMAND (READ STATUS REGISTER) OPERATION

The Read Status Register (RDSR) instruction provides

access to the Status Register. During the execution of

a program, erase or write status register operation, all

other instructions will be ignored except the RDSR

instruction, which can be used to check the progress or

completion of an operation by reading the WIP bit of

Status Register.

Figure 8. Read Status Register Sequence

WRSR COMMAND (WRITE STATUS REGISTER) OPERATION

The Write Status Register (WRSR) instruction allows

the user to enable or disable the block protection and

status register write protection features by writing “0”s

or “1” s into the volatile BP2, BP1, BP0 and SRWD

bits.

Figure 9. Write Status Register Sequence

DEVICE OPERATION (CONTINUED)

SIO

Pm25LD512/010/ 020

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READ COMMAND (READ DATA) OPERATION

The Read Data (READ) instruction is used to read

memory data of a Pm25LD512/010/020 under normal

mode running up to 33 MHz.

The READ instruction code is transmitted via the SlO

line, followed by three address bytes (A23 - A0) of the

first memory location to be read. A total of 24 address

bits are shifted in, but only A

MS

(most significant

address) - A0 are decoded. The remaining bits (A23 –

A

MS

)

are ignored. The first byte addressed can be at

any memory location. Upon completion, any data on

the Sl will be ignored. Refer to Table 12 for the related

Address Key.

The first byte data (D7 - D0) addressed is then shifted

out on the SO line, MSb first. A single byte of data, or

up to the whole memory array, can be read out in one

READ instruction. The address is automatically

incremented after each byte of data is shifted out. The

read operation can be terminated at any time by driving

CE# high (V

IH

) after the data comes out. When the

highest address of the devices is reached, the address

counter will roll over to the 000000h address, allowing

the entire memory to be read in one continuous READ

instruction.

Table 12. Address Key

Address Pm25LD020 Pm25LD010 Pm25LD512

A

N (

A

MS

– A

0)

A17 - A0 A16 - A0 A15 - A0

Don't Care Bits A23 – A18 A23 – A17 A23 – A16

Figure 12. Read Data Sequence

SIO

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DEVICE OPERATION (CONTINUED)

FAST_READ COMMAND (FAST READ DATA) OPERATION

The FAST_READ instruction is used to read memory

data at up to a 100 MHz clock.

The FAST_READ instruction code is followed by three

address bytes (A23 - A0) and a dummy byte (8 clocks),

transmitted via the SI line, with each bit latched-in

during the rising edge of SCK. Then the first data byte

addressed is shifted out on the SO line, with each bit

shifted out at a maximum frequency f

CT

, during the

falling edge of SCK.

The first byte addressed can be at any memory

location. The address is automatically incremented

after each byte of data is shifted out. When the highest

address is reached, the address counter will roll over to

the 000000h address, allowing the entire memory to be

read with a single FAST_READ instruction. The

FAST_READ instruction is terminated by driving CE#

high (V

IH

).

Figure 13. Fast Read Data Sequence

SIO

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DEVICE OPERATION (CONTINUED)

FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATION

The FRDO instruction is used to read memory data on

two output pins each at up to a 100 MHz clock.

The FRDO instruction code is followed by three

address bytes (A23 - A0) and a dummy byte (8 clocks),

transmitted via the SI line, with each bit latched-in

during the rising edge of SCK. Then the first data byte

addressed is shifted out on the SO and SIO lines, with

each pair of bits shifted out at a maximum frequency

f

CT

, during the falling edge of SCK. The first bit (MSb)

is output on SO, while simultaneously the second bit is

output on SIO.

The first byte addressed can be at any memory

location. The address is automatically incremented

after each byte of data is shifted out. When the highest

address is reached, the address counter will roll over to

the 000000h address, allowing the entire memory to be

read with a single FRDO instruction. FRDO instruction

is terminated by driving CE# high (V

IH

).

Figure 14. Fast Read Dual-Output Sequence

012 3 4 5 6 7 8910 11 28 29 30 31

...

INSTRUCTION = 0011 1011b ...

23 22 21 3210

3 - BYTE ADDRESS

CE#

SCK

SIO

SO HIGH IMPEDANCE

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

CE#

SCK

SIO

SO HIGH IMPEDANCE

DATA OUT 1 DATA OUT 2

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DRAFT Date: August, 2010, Rev:0.4

DEVICE OPERATION (CONTINUED)

PAGE_PROG COMMAND (PAGE PROGRAM) OPERATION

The Page Program (PAGE_PROG) instruction allows

up to 256 bytes data to be programmed into memory in

a single operation. The destination of the memory to be

programmed must be outside the protected memory

area set by the Block Protection (BP2, BP1, BP0) bits.

A PAGE_PROG instruction which attempts to program

into a page that is write-protected will be ignored.

Before the execution of PAGE_PROG instruction, the

Write Enable Latch (WEL) must be enabled through a

Write Enable (WREN) instruction.

The PAGE_PROG instruction code, three address

bytes and program data (1 to 256 bytes) are input via

the SlO line. Program operation will start immediately

after the CE# is brought high, otherwise the

PAGE_PROG instruction will not be executed. The

internal control logic automatically handles the

programming voltages and timing. During a program

operation, all instructions will be ignored except the

RDSR instruction. The progress or completion of the

program operation can be determined by reading the

WIP bit in Status Register via a RDSR instruction. If

the WIP bit is “1”, the program operation is still in

progress. If WIP bit is “0”, the program operation has

completed.

If more than 256 bytes data are sent to a device, the

address counter rolls over within the same page, the

previously latched data are discarded, and the last 256

bytes data are kept to be programmed into the page.

The starting byte can be anywhere within the page.

When the end of the page is reached, the address will

wrap around to the beginning of the same page. If the

data to be programmed are less than a full page, the

data of all other bytes on the same page will remain

unchanged.

Note: A program operation can alter “1”s into “0”s, but

an erase operation is required to change “0”s back to

“1”s. A byte cannot be reprogrammed without first

erasing the whole sector or block.

Figure 15. Page Program Sequence

SIO

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DRAFT Date: August, 2010, Rev:0.4

DEVICE OPERATION (CONTINUED)

ERASE OPERATION

The memory array of the Pm25LD512/010 is organized

into uniform 4 KByte sectors or 32 KByte uniform

blocks (a block consists of eight adjacent sectors).

Pm25LD020 is organized into uniform 4 KByte sectors

or 64 KByte uniform blocks (a block consists of sixteen

adjacent sectors)

Before a byte can be reprogrammed, the sector or

block that contains the byte must be erased (erasing

sets bits to “1”). In order to erase the devices, there are

three erase instructions available: Sector Erase

(SECTOR_ER), Block Erase (BLOCK_ER) and Chip

Erase (CHIP_ER). A sector erase operation allows any

individual sector to be erased without affecting the data

in other sectors. A block erase operation erases any

individual block. A chip erase operation erases the

whole memory array of a device. A sector erase, block

erase or chip erase operation can be executed prior to

any programming operation.

SECTOR_ER COMMAND (SECTOR ERASE)

OPERATION

A SECTOR_ER instruction erases a 4 KByte sector

Before the execution of a SECTOR_ER instruction, the

Write Enable Latch (WEL) must be set via a Write

Enable (WREN) instruction. The WEL bit is reset

automatically after the completion of sector an erase

operation.

A SECTOR_ER instruction is entered, after CE# is

pulled low to select the device and stays low during the

entire instruction sequence The SECTOR_ER

instruction code, and three address bytes are input via

SI. Erase operation will start immediately after CE# is

pulled high. The internal control logic automatically

handles the erase voltage and timing. Refer to Figure

14 for Sector Erase Sequence.

During an erase operation, all instruction will be

ignored except the Read Status Register (RDSR)

instruction. The progress or completion of the erase

operation can be determined by reading the WIP bit in

the Status Register using a RDSR instruction. If the

WIP bit is “1”, the erase operation is still in progress. If

the WIP bit is “0”, the erase operation has been

completed.

BLOCK_ER COMMAND (BLOCK ERASE)

OPERATION

A Block Erase (BLOCK_ER) instruction erases a 64

KByte block of the Pm25LD512/010/020. Before the

execution of a BLOCK_ER instruction, the Write

Enable Latch (WEL) must be set via a Write Enable

(WREN) instruction. The WEL is reset automatically

after the completion of a block erase operation.

The BLOCK_ER instruction code and three address

bytes are input via SI. Erase operation will start

immediately after the CE# is pulled high, otherwise the

BLOCK_ER instruction will not be executed. The

internal control logic automatically handles the erase

voltage and timing. Refer to Figure 15 for Block Erase

Sequence.

CHIP_ER COMMAND (CHIP ERASE) OPERATION

A Chip Erase (CHIP_ER) instruction erases the entire

memory array of a Pm25LD512/010/020. Before the

execution of CHIP_ER instruction, the Write Enable

Latch (WEL) must be set via a Write Enable (WREN)

instruction. The WEL is reset automatically after

completion of a chip erase operation.

The CHIP_ER instruction code is input via the SI.

Erase operation will start immediately after CE# is

pulled high, otherwise the CHIP_ER instruction will not

be executed. The internal control logic automatically

handles the erase voltage and timing. Refer to Figure

16 for Chip Erase Sequence.

Pm25LD512/010/ 020

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DRAFT Date: August, 2010, Rev:0.4

DEVICE OPERATION (CONTINUED)

Figure 16. Sector Erase Sequence

Figure 17. Block Erase Sequence

Figure 18. Chip Erase Sequence

SIO

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DRAFT Date: August, 2010, Rev:0.4

ABSOLUTE MAXIMUM RATINGS

(1)

Temperature Under Bias -65

o

C to +125

o

C

Storage Temperature -65

o

C to +125

o

C

Standard Package

240

o

C 3 Seconds

Surface Mount Lead Soldering Temperature

Lead-free Package

260

o

C 3 Seconds

Input Voltage with Respect to Ground on All Pins (2) -0.5 V to VCC + 0.5 V

All Output Voltage with Respect to Ground -0.5 V to VCC + 0.5 V

VCC (2) -0.5 V to +6.0 V

Notes:

1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only. The functional operation of the device conditions that exceed those

indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating

condition for extended periods may affect device reliability.

2. Maximum DC voltage on input or I/O pins is V

CC

+ 0.5 V. During voltage transitions, input or I/O pins may

overshoot V

CC

by

+ 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is

-0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to

exceed 20 ns.

DC AND AC OPERATING RANGE

Part Number Pm25LD512/010/020

Operating Temperature (Commercial Grade) -40

o

C to105

o

C

Vcc Power Supply 2.3 V – 3.6 V

DC CHARACTERISTICS

Applicable over recommended operating range from:

T

AC

= -40°C to +105°C, V

CC

= 2.3 V to 3.6 V (unless otherwise noted).

Symbol

Parameter Condition Min Typ Max Units

I

CC1

Vcc Active Read Current V

CC

= 3.6V at 33 MHz, SO = Open 10 15 mA

I

CC2

Vcc Program/Erase Current V

CC

= 3.6V at 33 MHz, SO = Open 15 30 mA

I

SB1

Vcc Standby Current CMOS

V

CC

= 3.6V, CE# = V

CC

10 µA

I

SB2

Vcc Standby Current TTL V

CC

= 3.6V, CE# = V

IH

to V

CC

3 mA

I

LI

Input Leakage Current V

IN

= 0V to V

CC

1 µA

I

LO

Output Leakage Current V

IN

= 0V to V

CC

, T

AC

= 0

o

C to 85

o

C 1 µA

V

IL

Input Low Voltage -0.5 0.8 V

V

IH

Input HIgh Voltage 0.7V

CC

V

CC

+ 0.3 V

V

OL

Output Low Voltage I

OL

= 2.1 mA 0.45 V

V

OH

Output High Voltage 2.3V < V

CC

< 3.6V

I

OH

= -100 µA

V

CC

- 0.2

V

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DRAFT Date: August, 2010, Rev:0.4

AC CHARACTERISTICS

Applicable over recommended operating range from T

A

= -40°C to +105°C, V

CC

= 2.3 V to 3.6 V

C

L

= 1 TTL Gate and 10 pF (unless otherwise noted).

Symbol

Parameter Min Typ Max Units

f

CT

Clock Frequency for fast read mode 0 100 MHz

f

C

Clock Frequency for read mode 0 33 MHz

t

RI

Input Rise Time 8 ns

t

FI

Input Fall Time 8 ns

t

CKH

SCK High Time 4 ns

t

CKL

SCK Low Time 4 ns

t

CEH

CE# High Time 25 ns

t

CS

CE# Setup Time 10 ns

t

CH

CE# Hold Time 5 ns

t

DS

Data In Setup Time 2 ns

t

DH

Data in Hold Time 2 ns

t

HS

Hold Setup Time 15 ns

t

HD

Hold Time 15 ns

t

V

Output Valid 8 ns

t

OH

Output Hold Time Normal Mode 0 ns

t

LZ

Hold to Output Low Z 200 ns

t

HZ

Hold to Output High Z 200 ns

t

DIS

Output Disable Time 100 ns

t

EC

Secter/Block/Chip Erase Time 10 ms

t

PP

Page Program Time 2 5 ms

t

VCS

V

CC

Set-up Time 50 µs

t

w

Write Status Register time (flash bit) 10 ms

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DRAFT Date: August, 2010, Rev:0.4

AC CHARACTERISTICS (CONTINUED)

SERIAL INPUT/OUTPUT TIMING

(1)

Note: 1. For SPI Mode 0 (0,0)

SIO

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DRAFT Date: August, 2010, Rev:0.4

AC CHARACTERISTICS (CONTINUED)

HOLD TIMING

PIN CAPACITANCE (f = 1 MHz, T = 25°C )

Typ Max Units Conditions

C

IN

4 6 pF V

IN

= 0 V

C

OUT

8 12 pF V

OUT

= 0 V

Note: These parameters are characterized but not 100% tested.

OUTPUT TEST LOAD INPUT TEST WAVEFORMS

AND MEASUREMENT LEVEL

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POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must not be

selected (CE# must follow the voltage applied on Vcc)

until Vcc reaches the correct value:

- Vcc(min) at Power-up, and then for a further delay of

tVCE

- Vss at Power-down

Usually a simple pull-up resistor on CE# can be used

to insure safe and proper Power-up and Power-down.

To avoid data corruption and inadvertent write

operations during power up, a Power On Reset (POR)

circuit is included. The logic inside the device is held

reset while Vcc is less than the POR threshold value

(Vwi) during power up, the device does not respond to

any instruction until a time delay of tPUW has elapsed

after the moment that Vcc rised above the VWI

threshold. However, the correct operation of the device

is not guaranteed if, by this time, Vcc is still below

Vcc(min). No Write Status Register, Program or Erase

instructions should be sent until the later of:

- tPUW after Vcc passed the VWI threshold

- tVCE after Vcc passed the Vcc(min) level

At Power-up, the device is in the following state:

- The device is in the Standby mode

- The Write Enable Latch (WEL) bit is reset

At Power-down, when Vcc drops from the operating

voltage, to below the Vwi, all write operations are

disabled

and the device does not respond to any write

instruction.

Chip Selection Not Allowed

All Write Commands are Rejected

tVCE Read Access Allowed Device fully accessible

tPUW

Vcc

Vcc(max)

Vcc(min)

Reset State

V (write inhibit)

Time

Symbol Parameter Min. Max. Unit

t

VCE

*1

Vcc(min) to CE# Low 10 us

t

PUW

*1

Power-Up time delay to Write instruction 1 10 ms

V

WI

*1

Write Inhibit Voltage 2.1 V

Note : *1. These parameters are characterized only.

1.8

1.

6

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DRAFT Date: August, 2010, Rev:0.4

PROGRAM/ERASE PERFORMANCE

Parameter Unit

Typ

Max

Remarks

Sector Erase Time ms

10 From writing erase command to erase completion

Block Erase Time ms

10 From writing erase command to erase completion

Chip Erase Time ms

10 From writing erase command to erase completion

Page Programming Time

ms

2 5 From writing program command to program completion

Note: These parameters are characterized and are not 100% tested.

RELIABILITY CHARACTERISTICS

Parameter Min Typ Unit Test Method

Endurance 200,000 Cycles JEDEC Standard A117

Data Retention 20 Years JEDEC Standard A103

ESD – Human Body Model 2,000 Volts JEDEC Standard A114

ESD – Machine Model 200 Volts JEDEC Standard A115

Latch-Up 100 + I

CC1

mA JEDEC Standard 78

Note: These parameters are characterized and are not 100% tested.

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DRAFT Date: August, 2010, Rev:0.4

PACKAGE TYPE INFORMATION

`

8S

8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit (SOIC) Package

(measure in millimeters)

Pm25LD512/010/ 020

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DRAFT Date: August, 2010, Rev:0.4

PACKAGE TYPE INFORMATION (CONTINUED)

8K

8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters)

Pm25LD512/010/ 020

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DRAFT Date: August, 2010, Rev:0.4

PACKAGE TYPE INFORMATION (CONTINUED)

Pm25LD512/010/ 020

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DRAFT Date: August, 2010, Rev:0.4

Pm25LD512/010/ 020

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DRAFT Date: August, 2010, Rev:0.4

REVISION HISTORY

Date Revision No. Description of Changes Page No.

March, 2009 0.0 Preliminary Product Specification All

September, 2009 0.1 1. Modify the program frequency to 50MHz

2. Improve Erase time from 15ms to 10ms.

1,10

October, 2009 0.2 1. Modify the t

HS

, t

HD

to 15ns 24

October, 2009 0.3 1. fix the erase time

November, 2009 0.31 1. change the operation voltage spec

2.3V~2.8V

All

August, 2010 0.4 1. Modify the operation voltage 2.3V~3.6V

2. Modify the write inhibit 1.6V~1.8V

ALL