24LC16B-I/OTG - Microchip Technology, Inc.

24AA00/24LC00/24C00 24AA01/24LC01B

24AA014/24LC014 24C01C

24AA02/24LC02B 24C02C

24AA024/24LC024 24AA025/24LC025

24AA04/24LC04B 24AA08/24LC08B

24AA16/24LC16B 24AA32A/24LC32A

24AA64/24LC64 24AA128/24LC128/24FC128

24AA256/24LC256/24FC256 24AA512/24LC512/24FC512

Features:

• 128-bit through 512 Kbit devices

• Single-supply with operation down to 1.8V for

24AAXX devices

• Low-power CMOS technology:

- 1 mA active current typical

-1μA standby current typical (I-temp)

• 2-wire serial interface bus, I2C™ compatible

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (1.8V) and 400 kHz (≥ 2.5V) compatibility

• 1 MHz for 24FCXX products

• Self-timed write cycle (including auto-erase)

• Page write buffer

• Hardware write-protect available on most devices

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1 million erase/write cycles

• Data retention > 200 years

• 8-lead PDIP, SOIC, TSSOP and MSOP packages

• 5-lead SOT-23 package (most 1-16 Kbit devices)

• 8-lead 2x3mm and 5x6mm DFN packages

available

• Available for extended temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Description:

The Microchip Technology Inc. 24CXX, 24LCXX,

24AAXX and 24FCXX (24XX*) devices are a family of

128-bit through 512 Kbit Electrically Erased PROMs.

The devices are organized in blocks of x8-bit memory

with 2-wire serial interfaces. Low voltage design

permits operation down to 1.8V (for 24AAXX devices),

with standby and active currents of only 1 μA and 1

mA, respectively. Devices 1 Kbit and larger have page

write capability. Parts having functional address lines

allow connection of up to 8 devices on the same bus.

The 24XX family is available in the standard 8-pin

PDIP, surface mount SOIC, TSSOP and MSOP pack-

ages. Most 128-bit through 16 Kbit devices are also

available in the 5-lead SOT-23 package. DFN

packages (2x3mm or 5x6mm) are also available. All

packages are available in a Pb-free (Matte Tin) finish.

Package Types(1)

VSS

VCC

WP(3)

SCL

SDA

PDIP/SOIC

VSS

VCC

WP(3)

SCL

SDA

TSSOP/MSOP(2)

VSS

VCC

SCL

SDA

510

TSSOP

SCL

VSS

SDA

VCC

SOT-23-5

(24XX00)

SOT-23-5

SCL

VSS

SDA

VCC

(all except 24XX00)

VSS

WP(3)

SCL

SDA

1VCC

DFN Note 1: Pins A0, A1, A2 and WP are not used by some

devices (no internal connections). See Table 1-1,

Device Selection Table, for details.

2: Pins A0 and A1 are no-connects for the 24XX128

and 24XX256 MSOP devices.

3: Pin 7 is “not used” for 24XX00, 24XX025 and

24C01C.

I2C™ Serial EEPROM Family Data Sheet

*24XX is used in this document as a generic part number for 24 series devices in this data sheet. 24XX64, for example,

represents all voltages of the 64 Kbit device.

24AAXX/24LCXX/24FCXX

TABLE 1-1: DEVICE SELECTION TABLE

Part Number VCC

Range

Max Clock

Frequency

Page

Size

Write-

Protect

Scheme

Functional

Address

Pins

Temp

Range Packages(5)

128-bit devices

24AA00 1.8-5.5V 400 kHz(1)

— None None

C, I P, SN, ST, OT, MC

24LC00 2.5-5.5V 400 kHz(1) C, I

24C00 4.5-5.5V 400 kHz C, I, E

1 Kb devices

24AA01 1.8-5.5V 400 kHz (2)

8 bytes Entire Array None I P, SN, ST, MS, OT, MC

24LC01B 2.5-5.5V 400 kHz I, E

24AA014 1.8-5.5V 400 kHz(2)

16 bytes Entire Array A0, A1, A2 I P, SN, ST, MS, MC

24LC014 2.5-5.5V 400 kHz I

24C01C 4.5V-5.5V 400 kHz 16 bytes None A0, A1, A2 C, I, E P, SN, ST, MC

2 Kb devices

24AA02 1.8-5.5V 400 kHz (2)

8 bytes Entire Array None I P, SN, ST, MS, OT, MC

24LC02B 2.5-5.5V 400 kHz I, E

24AA024 1.8-5.5V 400 kHz(2)

16 bytes Entire Array A0, A1, A2 I P, SN, ST, MS, MC

24LC024 2.5-5.5V 400 kHz I

24AA025 1.8-5.5V 400 kHz(2)

16 bytes None A0, A1, A2 I P, SN, ST,MS, MC

24LC025 2.5-5.5V 400 kHz I

24C02C 4.5-5.5V 400 kHz 16 bytes Upper Half

of Array

A0, A1, A2 C, I, E P, SN, ST, MC

4 Kb devices

24AA04 1.8-5.5V 400 kHz (2) 16 bytes Entire Array None I P, SN, ST, MS, OT, MC

24LC04B 2.5-5.5V 400 kHz I, E

8 Kb devices

24AA08 1.8-5.5V 400 kHz (2)

16 bytes Entire Array None I P, SN, ST, MS, OT, MC

24LC08B 2.5-5.5V 400 kHz I, E

16 Kb devices

24AA16 1.8-5.5V 400 kHz (2)

16 bytes Entire Array None I P, SN, ST, MS, OT, MC

24LC16B 2.5-5.5V 400 kHz I, E

32 Kb devices

24AA32A 1.8-5.5V 400 kHz (2)

32 bytes Entire Array A0, A1, A2 I P, SN, SM, ST, MS, MC

24LC32A 2.5-5.5V 400 kHz I, E

64 Kb devices

24AA64 1.8-5.5V 400 kHz (2)

32 bytes Entire Array A0, A1, A2 I P, SN, SM, ST, MS, MC

24LC64 2.5-5.5V 400 kHz I, E

Note 1: 100 kHz for VCC <4.5V.

2: 100 kHz for VCC <2.5V.

3: 400 kHz for VCC <2.5V

4: Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package.

5: P = 8-PDIP, SN = 8-SOIC (150 mil JEDEC), ST = 8-TSSOP, OT = 5 or 6-SOT23, MC = 2x3mm DFN,

MS = 8-MSOP, SM = 8-SOIC (200 mil EIAJ), MF = 5x6mm DFN, ST14 = 14-TSSOP.

24AAXX/24LCXX/24FCXX

128 Kb devices

24AA128 1.8-5.5V 400 kHz (2)

64 bytes Entire Array A0, A1,

A2(4)

I P, SN, SM, ST, MS, MF,

ST14

24LC128 2.5-5.5V 400 kHz I, E

24FC128 1.8-5.5V 1 MHz(3) I

256 Kb devices

24AA256 1.8-5.5V 400 kHz (2)

64 bytes Entire Array A0, A1,

A2(4)

I P, SN, SM, ST, MS, MF,

ST14

24LC256 2.5-5.5V 400 kHz I, E

24FC256 1.8-5.5V 1 MHz(3) I

512 Kb devices

24AA512 1.8-5.5V 400 kHz (2)

128

bytes Entire Array A0, A1, A2

I P, SM, MF, ST14

24LC512 2.5-5.5V 400 kHz I, E

24FC512 1.8-5.5V(3) 1 MHz I

TABLE 1-1: DEVICE SELECTION TABLE (CONTINUED)

Part Number VCC

Range

Max Clock

Frequency

Page

Size

Write-

Protect

Scheme

Functional

Address

Pins

Temp

Range Packages(5)

Note 1: 100 kHz for VCC <4.5V.

2: 100 kHz for VCC <2.5V.

3: 400 kHz for VCC <2.5V

4: Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package.

5: P = 8-PDIP, SN = 8-SOIC (150 mil JEDEC), ST = 8-TSSOP, OT = 5 or 6-SOT23, MC = 2x3mm DFN,

MS = 8-MSOP, SM = 8-SOIC (200 mil EIAJ), MF = 5x6mm DFN, ST14 = 14-TSSOP.

24AAXX/24LCXX/24FCXX

2.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

TABLE 2-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions

above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

DC CHARACTERISTICS

Electrical Characteristics:

Commercial (C): VCC = +1.8V to 5.5V TA = 0°C to +70°C

Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C

Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C

Param.

No. Sym. Characteristic Min. Max. Units Conditions

D1 — A0, A1, A2, SCL, SDA and

WP pins:

————

D2 VIH High-level input voltage 0.7 VCC —V—

D3 VIL Low-level input voltage — 0.3 VCC

0.2 VCC

VCC ≥ 2.5V

VCC < 2.5V

D4 VHYS Hysteresis of Schmitt Trigger

inputs (SDA, SCL pins)

0.05 VCC —V(Note 1)

D5 VOL Low-level output voltage — 0.40 V IOL = 3.0 mA @ VCC = 2.5V

D6 ILI Input leakage current — ±1 μAVIN = VSS or VCC

D7 ILO Output leakage current — ±1 μAVOUT = VSS or VCC

D8 CIN,

COUT

Pin capacitance

(all inputs/outputs)

—10pFVCC = 5.0V (Note 1)

TA = 25°C, FCLK = 1 MHz

D9 ICC Read Operating current — 400

μA

24XX128, 256, 512: VCC = 5.5V,

SCL = 400 kHz

All except 24XX128, 256, 512:

VCC = 5.5V, SCL = 400 kHz

ICC Write — 3

VCC = 5.5V, All except 24XX512

VCC = 5.5V, 24XX512

D10 ICCS Standby current — 1 μATA = -40°C to +85°C

SCL = SDA = VCC = 5.5V

A0, A1, A2, WP = VSS or VCC

—5μATA = -40°C to 125°C

SCL = SDA = VCC = 5.5V

A0, A1, A2, WP = VSS or VCC

—50μA 24C01C and 24C02C only

SCL = SDA = VCC = 5.5V

A0, A1, A2, WP = VSS or VCC

Note 1: This parameter is periodically sampled and not 100% tested.

24AAXX/24LCXX/24FCXX

TABLE 2-2: AC CHARACTERISTICS – ALL EXCEPT 24XX00, 24C01C

AND 24C02C

AC CHARACTERISTICS

Electrical Characteristics:

Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C

Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C

Param.

No. Sym. Characteristic Min. Max. Units Conditions

CLK Clock frequency —

—

100

400

1000

kHz 1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FCXXX

2.5V ≤ VCC ≤ 5.5V 24FCXXX

HIGH Clock high time 4000

600

500

—

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FCXXX

2.5V ≤ VCC ≤ 5.5V 24FCXXX

LOW Clock low time 4700

1300

500

—

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FCXXX

2.5V ≤ VCC ≤ 5.5V 24FCXXX

RSDA and SCL rise time

(Note 1)

—

1000

300

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V 24FCXXX

FSDA and SCL fall time

(Note 1)

—

300

100

ns All except 24FCXXX

1.8V ≤ VCC ≤ 5.5V 24FCXXX

HD:STA Start condition hold time 4000

600

250

—

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FCXXX

2.5V ≤ VCC ≤ 5.5V 24FCXXX

SU:STA Start condition setup time 4700

600

250

—

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FCXXX

2.5V ≤ VCC ≤ 5.5V 24FCXXX

HD:DAT Data input hold time 0 — ns (Note 2)

SU:DAT Data input setup time 250

100

—

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V 24FCXXX

10 TSU:STO Stop condition setup time 4000

600

250

—

ns 1.8 V ≤ VCC < 2.5V

2.5 V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FCXXX

2.5 V ≤ VCC ≤ 5.5V 24FCXXX

11 TSU:WP WP setup time 4000

600

—

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V 24FCXXX

12 THD:WP WP hold time 4700

1300

—

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V 24FCXXX

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site:

www.microchip.com.

4: 24FCXXX denotes the 24FC128, 24FC256 and 24FC512 devices.

24AAXX/24LCXX/24FCXX

13 TAA Output valid from clock

(Note 2)

—

3500

900

400

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FCXXX

2.5V ≤ VCC ≤ 5.5V 24FCXXX

14 TBUF Bus free time: Time the bus

must be free before a new

transmission can start

4700

1300

500

—

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FCXXX

2.5V ≤ VCC ≤ 5.5V 24FCXXX

15 TOF Output fall time from VIH

minimum to VIL maximum

CB ≤ 100 pF

10 + 0.1CB250

250

ns All except 24FCXXX (Note 1)

24FCXXX (Note 1)

16 TSP Input filter spike suppression

(SDA and SCL pins)

— 50 ns All except 24FCXXX (Note 1)

17 TWC Write cycle time (byte or

page)

—5ms

18 — Endurance 1,000,000 — cycles 25°C (Note 3)

TABLE 2-2: AC CHARACTERISTICS – ALL EXCEPT 24XX00, 24C01C

AND 24C02C (CONTINUED)

AC CHARACTERISTICS

Electrical Characteristics:

Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C

Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C

Param.

No. Sym. Characteristic Min. Max. Units Conditions

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site:

www.microchip.com.

4: 24FCXXX denotes the 24FC128, 24FC256 and 24FC512 devices.

24AAXX/24LCXX/24FCXX

TABLE 2-3: AC CHARACTERISTICS – 24XX00, 24C01C AND 24C02C

All Parameters apply across all

recommended operating ranges

unless otherwise noted

Commercial (C): TA = 0°C to +70°C, VCC = 1.8V to 5.5V

Industrial (I): TA = -40°C to +85°C, VCC = 1.8V to 5.5V

Automotive (E): TA = -40°C to +125°C, VCC = 4.5V to 5.5V

Parameter Symbol Min Max Units Conditions

Clock frequency FCLK —

—

100

400

kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Clock high time THIGH 4000

4000

600

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Clock low time TLOW 4700

4700

1300

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

SDA and SCL rise time

(Note 1)

TR—

—

1000

300

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

SDA and SCL fall time TF—300ns(Note 1)

Start condition hold time THD:STA 4000

4000

600

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Start condition setup time TSU:STA 4700

4700

600

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Data input hold time THD:DAT 0—ns(Note 2)

Data input setup time TSU:DAT 250

250

100

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Stop condition setup time TSU:STO 4000

4000

600

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Output valid from clock

(Note 2)

TAA —

—

3500

900

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Bus free time: Time the bus must

be free before a new transmis-

sion can start

TBUF 4700

4700

1300

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.8V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Output fall time from VIH

minimum to VIL maximum

TOF 20+0.1

250 ns (Note 1), CB ≤ 100 pF

Input filter spike suppression

(SDA and SCL pins)

TSP —50ns(Note 1)

Write cycle time TWC —4

1.5

ms 24XX00

24C01C, 24C02C

Endurance 1,000,000 — cycles (Note 3)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.

24AAXX/24LCXX/24FCXX

FIGURE 2-1: BUS TIMING DATA

(unprotected)

(protected)

SCL

SDA

OUT

D4 4

11 12

24AAXX/24LCXX/24FCXX

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 A0, A1, A2 Chip Address Inputs

The A0, A1 and A2 pins are not used by the 24XX01

through 24XX16 devices.

The A0, A1 and A2 inputs are used by the 24C01C,

24C02C, 24XX014, 24XX024, 24XX025 and the

24XX32 through 24XX512 for multiple device opera-

tions. The levels on these inputs are compared with the

corresponding bits in the slave address. The chip is

selected if the compare is true.

For the 24XX128 and 24XX256 in the MSOP package

only, pins A0 and A1 are not connected.

Up to eight devices (two for the 24XX128 and

24XX256 MSOP package) may be connected to the

same bus by using different Chip Select bit

combinations.

In most applications, the chip address inputs A0, A1

and A2 are hard-wired to logic ‘0’ or logic ‘1’. For

applications in which these pins are controlled by a

microcontroller or other programmable device, the chip

address pins must be driven to logic ‘0’ or logic ‘1’

before normal device operation can proceed.

3.2 Serial Data (SDA)

This is a bidirectional pin used to transfer addresses

and data into and out of the device. It is an open drain

terminal. Therefore, the SDA bus requires a pull-up

resistor to VCC (typical 10 kΩ for 100kHz, 2kΩ for

400 kHz and 1 MHz).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

3.3 Serial Clock (SCL)

This input is used to synchronize the data transfer to

and from the device.

3.4 Write-Protect (WP)

This pin must be connected to either VSS or VCC. If tied

to VSS, write operations are enabled. If tied to VCC,

write operations are inhibited but read operations are

not affected. See Table 1-1 for the write-protect

scheme of each device.

3.5 Power Supply (VCC)

A VCC threshold detect circuit is employed which

disables the internal erase/write logic if VCC is below

1.5V at nominal conditions. For the 24C00, 24C01C

and 24C02C devices, the erase/write logic is disabled

below 3.8V at nominal conditions.

Name

8-Pin

PDIP and

SOIC

8-Pin

TSSOP and

MSOP

5-Pin SOT-23

24XX00

5-Pin SOT-23

All except

24XX00

14-Pin

TSSOP

8-Pin

5x6 DFN and

2x3 DFN

Function

A0 1 1(1) — — 1 1 User configurable Chip Select(3)

A1 2 2(1) ——22

User configurable Chip Select(3)

A2 3 3 — — 6 3 User configurable Chip Select(3)

VSS 4 4 2 2 7 4 Ground

SDA 5 5 3 3 8 5 Serial Data

SCL 6 6 1 1 9 6 Serial Clock

(NC) — — 4 — 3, 4, 5,

10, 11, 12

— Not Connected

WP 7(2) 7(2) — 5 13 7 Write-Protect Input

VCC 8 8 5 4 14 8 Power Supply

Note 1: Pins 1 and 2 are not connected for the 24XX128 and 24XX256 MSOP packages.

2: Pin 7 is not used for 24XX00, 24XX025 and 24C01C.

3: Pins A0, A1 and A2 are not used by some devices (no internal connections). See Table 1-1 for details.

24AAXX/24LCXX/24FCXX

4.0 FUNCTIONAL DESCRIPTION

Each 24XX device supports a bidirectional, 2-wire bus

and data transmission protocol. A device that sends

data onto the bus is defined as a transmitter, while a

device receiving data is defined as a receiver. The bus

has to be controlled by a master device which gener-

ates the Serial Clock (SCL), controls the bus access

and generates the Start and Stop conditions, while the

24XX works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is activated.

Block Diagram

HV Generator

EEPROM

Array

Page Latches*

YDEC

XDEC

Sense Amp.

R/W Control

emory

ontrol

ogic

I/O

ontrol

ogic

I/O

A0*A1*A2*

SDA

SCL

WP*

* A0, A1, A2, WP and page latches are not used by some

devices.

See Table 1-1, Device Selection Table, for details.

24AAXX/24LCXX/24FCXX

5.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 5-1).

5.1 Bus Not Busy (A)

Both data and clock lines remain high.

5.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

5.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

5.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of data

bytes transferred between Start and Stop conditions is

determined by the master device.

24AAXX/24LCXX/24FCXX

5.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end-of-

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XX) will leave the data line

high to enable the master to generate the Stop

condition (Figure 5-2).

FIGURE 5-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 5-2: ACKNOWLEDGE TIMING

Note: During a write cycle, the 24XX will not

acknowledge commands.

SCL

SDA

(A) (B) (D) (D) (A)(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

SCL 987654321123

Transmitter must release the SDA line at this point,

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line

at this point so the Transmitter can

continue sending data.

Data from transmitter

SDA

Acknowledge

bit

Data from transmitter

24AAXX/24LCXX/24FCXX

5.6 Device Addressing For Devices

Without Functional Address Pins

A control byte is the first byte received following the

Start condition from the master device (Figure 5-3).

The control byte begins with a four-bit control code. For

the 24XX, this is set as ‘1010’ binary for read and write

operations. The next three bits of the control byte are

the block-select bits (B2, B1, B0). They are used by the

master device to select which of the 256-word blocks of

memory are to be accessed. These bits are in effect the

three Most Significant bits of the word address. Note

that B2, B1 and B0 are “don’t care” for the 24XX00, the

24XX01 and 24XX02. B2 and B1 are “don’t care” for

the 24XX04. B2 is “don’t care” for the 24XX08.

The last bit of the control byte defines the operation to

be performed. When set to ‘1’, a read operation is

selected. When set to ‘0’ a write operation is selected.

Following the Start condition, the 24XX monitors the

SDA bus. Upon receiving a ‘1010’ code, the block

select bits and the R/W bit, the slave device outputs an

Acknowledge signal on the SDA line. The address byte

follows the acknowledge.

FIGURE 5-3: CONTROL AND ADDRESS BYTE ASSIGNMENTS FOR

DEVICES WITHOUT ADDRESS PINS

S1010xxxR/W ACK

S1010xxB0 R/W ACK

S1010xB1 B0 R/W ACK

S1010B2 B1 B0 R/W ACK

24XX01

24XX02

24XX04

24XX08

24XX016

x = “don’t care” bit

Acknowledge

Control Code

Start bit

Control Byte

Block Select bits

Address Byte

24XX00

Read/Write bit (read = 1, write = 0)

xxxxA3 . . A0

xA6 . . . . . A0

A7 . . . . . . A0

bit

24AAXX/24LCXX/24FCXX

5.7 Device Addressing For Devices

With Functional Address Pins

A control byte is the first byte received following the

Start condition from the master device (Figure 5-4).

The control byte begins with a 4-bit control code. For

the 24XX, this is set as ‘1010’ binary for read and write

operations. The next three bits of the control byte are

the Chip Select bits (A2, A1, A0). The Chip Select bits

allow the use of up to eight 24XX devices on the same

bus and are used to select which device is accessed.

The Chip Select bits in the control byte must corre-

spond to the logic levels on the corresponding A2, A1

and A0 pins for the device to respond. These bits are,

in effect, the three Most Significant bits of the word

address.

For 24XX128 and 24XX256 in the MSOP package, the

A0 and A1 pins are not connected. During device

addressing, the A0 and A1 Chip Select bits (Figure 5-4)

should be set to ‘0’. Only two 24XX128 or 24XX256

MSOP packages can be connected to the same bus.

The last bit of the control byte defines the operation to

be performed. When set to a ‘1’, a read operation is

selected. When set to a ‘0’, a write operation is

selected.

For higher density devices (24XX32 through

24XX512), the next two bytes received define the

address of the first data byte. Depending on the prod-

uct density, not all bits in the address high byte are

used. A15, A14, A13 and A12 are “don’t care” for

24XX32. A15, A14 and A13 are “don’t care” for

24XX64. A15 and A14 are “don’t care” for 24XX128.

A15 is “don’t care” for 24XX256. All address bits are

used for the 24XX512. The upper address bits are

transferred first, followed by the Less Significant bits.

Following the Start condition, the 24XX monitors the

SDA bus. Upon receiving a ‘1010’ code, appropriate

device select bits and the R/W bit, the slave device out-

puts an Acknowledge signal on the SDA line. The

address byte(s) follow the acknowledge.

FIGURE 5-4: CONTROL AND ADDRESS BYTE ASSIGNMENTS FOR

DEVICES WITH ADDRESS PINS

S1010A2 A1 A0 R/W ACK

24XX64

24XX128

24XX256

24XX512

x = “don’t care” bit

Acknowledge

Control Code

Start bit

Control Byte

Chip Select bits*

Address High Byte

24XX32

Read/Write bit

xxxxA11 A10 A9 A8

xxxA12 A11 A10 A9 A8

xxA13 A12 A11 A10 A9 A8

xA14 A13 A12 A11 A10 A9 A8

A15 A14 A13 A12 A11 A10 A9 A8

bit

S1010A2 A1 A0 R/W ACK

xA6 . . . . . A0

A7 . . . . . . A0

24XX024/025

24C02C

24C01C

Address Byte

A7 . . . . . . A0

Address Low Byte

* Chip Select bits A1 and A0 must be set to ‘0’ for 24XX128/256 devices in the MSOP package.

Control Byte

(Read = 1, Write = 0)

24AAXX/24LCXX/24FCXX

5.7.1 CONTIGUOUS ADDRESSING

ACROSS MULTIPLE DEVICES

Chip Select bits A2, A1 and A0 can be used to expand

the contiguous address space by adding up to eight

24XXs on the same bus. Software can use the three

address bits of the control byte as the three Most

Significant bits of the address byte. For example, in the

24XX32 devices, software can use A0 of the control

byte as address bit A12; A1 as address bit A13; and A2

as address bit A14 (Table 5-1). It is not possible to

sequentially read across device boundaries.

TABLE 5-1: CONTROL BYTE ADDRESS BITS

Maximum

Devices

Maximum

Contiguous

Address Space

Chip Select Bit

1K (24C01C) 8 8 Kb A10 A9 A8

1K (24XX014) 8 8 Kb A10 A9 A8

2K (24C02C) 8 16 Kb A10 A9 A8

2K (24XX024/025 8 16 Kb A10 A9 A8

32K (24XX32) 8 256 Kb A14 A13 A12

64K (24XX64) 8 512 Kb A15 A14 A13

128K (24XX128) 8* 1 Mb A16* A15* A14

256K (24XX256) 8* 2 Mb A17* A16* A15

512K (24XX512) 8 4 Mb A18 A17 A16

* Up to two 24XX128 or 24XX256 devices in the MSOP package can be added for up to 256 kb or 512 kb of address

space, respectively. Bits A0 and A1 must be set to ‘0’.

24AAXX/24LCXX/24FCXX

6.0 WRITE OPERATIONS

6.1 Byte Write

A byte write operation begins with a Start condition

from the master followed by the four-bit control code

(see Figure 6-1 and Figure 6-2). The next 3 bits are

either the Block Address bits (for devices without

address pins) or the Chip Select bits (for devices with

address pins). Then the master transmitter clocks the

R/W bit (which is a logic low) onto the bus. The slave

then generates an Acknowledge bit during the ninth

clock cycle.

The next byte transmitted by the master is the address

byte (for 128-bit to 16 Kbit devices) or the high-order

address byte (for 32-512 Kbit devices). For 32 through

512 Kbit devices, the high-order address byte is

followed by the low-order address byte. In either case,

each address byte is acknowledged by the 24XX and

the address bits are latched into the internal address

counter of the 24XX.

For the 24XX00 devices, only the lower four address

bits are used by the device. The upper four bits are

“don’t cares.”

After receiving the ACK from the 24XX acknowledging

the final address byte, the master device transmits the

data word to be written into the addressed memory

location. The 24XX acknowledges again and the

master generates a Stop condition, which initiates the

internal write cycle.

If an attempt is made to write to an array with the WP

pin held high, the device will acknowledge the

command, but no write cycle will occur, no data will be

written, and the device will immediately accept a new

command. After a byte Write command, the internal

address counter will increment to the next address

location. During a write cycle, the 24XX will not

acknowledge commands.

FIGURE 6-1: BYTE WRITE: 128-BIT TO 16 KBIT DEVICES

FIGURE 6-2: BYTE WRITE: 32 TO 512 KBIT DEVICES

S P

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Address

Byte

Data

Byte

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

High Order

Address Byte

Low Order

Address Byte

Data S

Byte

24AAXX/24LCXX/24FCXX

6.2 Page Write

The write control byte, word address byte(s), and the

first data byte are transmitted to the 24XX in much the

same way as in a byte write (see Figure 6-3 and

Figure 6-4 ). The exception is that instead of generating

a Stop condition, the master transmits up to one page

of bytes(1), which is temporarily stored in the on-chip

page buffer. This data is then written into memory once

the master has transmitted a Stop condition. Upon

receipt of each word, the internal address counter is

incremented by one. If the master should transmit more

than one page of data prior to generating the Stop con-

dition, the address counter will roll over and the previ-

ously received data will be overwritten. As with the byte

write operation, once the Stop condition is received, an

internal write cycle begins. During the write cycle, the

24XX will not acknowledge commands.

Page writes can be any number of bytes within a page

(up to the page size), starting at any address. Only the

data bytes being addressed will be changed within the

page.

If an attempt is made to write to the array with the WP

pin held high, the device will acknowledge the

command, but no write cycle will occur, no data will be

written and the device will immediately accept a new

command.

6.3 Write-Protection

The WP pin allows the user to write-protect the array

when the pin is tied to VCC. See Device Selection

Table 1-1 for the write-protect scheme of each device.

If tied to VSS, the write protection is disabled. The WP

pin is sampled prior to the Stop bit for every Write

command (Figure 2-1). Toggling the WP pin after the

Stop bit will have no effect on the execution of the write

cycle.

FIGURE 6-3: PAGE WRITE: 1 KB TO 16 KBIT DEVICES

FIGURE 6-4: PAGE WRITE: 32 TO 512 KBIT DEVICES

* See Table 1-1 for maximum number of data bytes in a page.

Note 1: See Device Selection Table 1-1 for the

page size of each device.

Note: Page write operations are limited to

writing bytes within a single physical

page, regardless of the number of

bytes actually being written. Physical

page boundaries start at addresses

that are integer multiples of the page

buffer size (or ‘page size’) and end at

addresses that are integer multiples of

[page size – 1]. If a Page Write

command attempts to write across a

physical page boundary, the result is

that the data wraps around to the

beginning of the current page (over-

writing data previously stored there),

instead of being written to the next

page, as might be expected. It is there-

fore necessary for the application soft-

ware to prevent page write operations

that would attempt to cross a page

boundary.

S P

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Address

Byte Initial Final

Second

Data Byte Data Byte Data Byte*

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

High Order

Address Byte

Low Order

Address Byte

Initial S

Final

Data Byte Data Byte*

24AAXX/24LCXX/24FCXX

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge commands

during a write cycle, this can be used to determine

when the cycle is complete (This feature can be used

to maximize bus throughput). Once the Stop condition

for a Write command has been issued from the master,

the device initiates the internally timed write cycle. ACK

polling can be initiated immediately. This involves the

master sending a Start condition, followed by the con-

trol byte for a Write command (R/W = 0). If the device

is still busy with the write cycle, then no ACK will be

returned. If no ACK is returned, the Start bit and control

byte must be re-sent. If the cycle is complete, then the

device will return the ACK and the master can then pro-

ceed with the next Read or Write command. See

Figure 7-1 for flow diagram.

FIGURE 7-1: ACKNOWLEDGE

POLLING FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

Yes

24AAXX/24LCXX/24FCXX

8.0 READ OPERATION

Read operations are initiated in much the same way as

write operations with the exception that the R/W bit of

the control byte is set to ‘1’. There are three basic types

of read operations: current address read, random read

and sequential read.

8.1 Current Address Read

The 24XX contains an address counter that maintains

the address of the last byte accessed, internally incre-

mented by ‘1’. Therefore, if the previous read or write

operation was to address ‘n’ (n is any legal address),

the next current address read operation would access

data from address n + 1.

Upon receipt of the control byte with R/W bit set to ‘1’,

the 24XX issues an acknowledge and transmits the

8-bit data byte. The master will not acknowledge the

transfer, but does generate a Stop condition and the

24XX discontinues transmission (Figure 8-1).

FIGURE 8-1: CURRENT ADDRESS

READ

8.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the byte address must first

be set. This is done by sending the byte address to the

24XX as part of a write operation (R/W bit set to ‘0’).

Once the byte address is sent, the master generates a

Start condition following the acknowledge. This termi-

nates the write operation, but not before the internal

address counter is set. The master then issues the

control byte again, but with the R/W bit set to a ‘1’. The

24XX will then issue an acknowledge and transmit the

8-bit data byte. The master will not acknowledge the

transfer but does generate a Stop condition, which

causes the 24XX to discontinue transmission

(Figure 8-2 and Figure 8-3). After a random Read

command, the internal address counter will increment

to the next address location.

FIGURE 8-2: RANDOM READ: 128-BIT TO 16 KBIT DEVICES

FIGURE 8-3: RANDOM READ: 32 TO 512 KBIT DEVICES

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Data

Byte

S P

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Address

Byte (n)

Control

Byte

Data

Byte

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

High Order

Address Byte

Low Order

Address Byte

Control

Byte

Data

Byte

SSP

24AAXX/24LCXX/24FCXX

8.3 Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24XX transmits the

first data byte, the master issues an acknowledge as

opposed to the Stop condition used in a random read.

This acknowledge directs the 24XX to transmit the next

sequentially addressed data byte (Figure 8-4). Follow-

ing the final byte transmitted to the master, the master

will NOT generate an acknowledge but will generate a

Stop condition. To provide sequential reads, the 24XX

contains an internal address pointer which is incre-

mented by one at the completion of each operation.

This address pointer allows the entire memory contents

to be serially read during one operation. If the last

address byte in the array is acknowledged, the address

pointer will roll over to address 0x00.

FIGURE 8-4: SEQUENTIAL READ

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte Data Byte Data Byte Data Byte Data Byte

Initial Second Third Final

24AAXX/24LCXX/24FCXX

APPENDIX A: REVISION HISTORY

Revision A

Original release of document. Combined Serial

EEPROM 24XXX device data sheets.

24AAXX/24LCXX/24FCXX

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

8-Lead PDIP Package Marking (Pb-free)

Device Line 1

Marking Device Line 1

Marking

24AA00 24AA00 24LC00 24LC00 24C00 24C00

24AA01 24AA01 24LC01B 24LC01B

24AA014 24AA014 24LC014 24LC014

24C01C 24C01C

24AA02 24AA02 24LC02B 24LC02B

24AA024 24AA024 24LC024 24LC024

24AA025 24AA025 24LC025 24LC025

24C02C 24C02C

24AA04 24AA04 24LC04B 24LC04B

24AA08 24AA08 24LC08B 24LC08B

24AA16 24AA16 24LC16B 24LC16B

24AA32A 24AA32A 24LC32A 24LC32A

24AA64 24AA64 24LC64 24LC64

24AA128 24AA128 24LC128 24LC128 24FC128 24FC128

24AA256 24AA256 24LC256 24LC256 24FC256 24FC256

24AA512 24AA512 24LC512 24LC512 24FC512 24FC512

Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

Legend: XX...X Part number or part number code

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn) plated devices

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

XXXXXNNN

XXXXXXXX

YYWW

8-Lead PDIP

I/P 1L7

24LC01B

0528

Example: Sn/Pb

I/P 1L7

24LC01B

0528

Example: Pb-free

24AAXX/24LCXX/24FCXX

Note: T = Temperature range: I = Industrial, E = Extended, (blank) = Commercial

XXXXXNNN

XXXXXXXX

YYWW

8-Lead SOIC

I/SN 0528

24LC01B

1L7

Example: Sn/Pb

SN 0528

24LC01BI

1L7

Example: Pb-free

8-Lead SOIC Package Marking (Pb-free)

Device Line 1

Marking Device Line 1

Marking

24AA00 24AA00T 24LC00 24LC00T 24C00 24C00T

24AA01 24AA01T 24LC01B 24LC01BT

24AA014 24AA014T 24LC014 24LC014T

24C01C 24C01CT

24AA02 24AA02T 24LC02B 24LC02BT

24AA024 24AA024T 24LC024 24LC024T

24AA025 24AA025T 24LC025 24LC025T

24C02C 24C02CT

24AA04 24AA04T 24LC04B 24LC04BT

24AA08 24AA08T 24LC08B 24LC08BT

24AA16 24AA16T 24LC16B 24LC16BT

24AA32A 24AA32AT 24LC32A 24LC32AT

24AA64 24AA64T 24LC64 24LC64T

24AA128 24AA128T 24LC128 24LC128T 24FC128 24FC128T

24AA256 24AA256T 24LC256 24LC256T 24FC256 24FC256T

24AA512 24AA512T 24LC512 24LC512T 24FC512 24FC512T

Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

Legend: XX...X Part number or part number code

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn) plated devices

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

24AAXX/24LCXX/24FCXX

8-Lead 2x3 DFN Example:

244

506

XXX

YWW

8-Lead 2x3mm DFN Package Marking (Pb-free)

Device

Industrial

Line 1

Marking

Device

Industrial

Line 1

Marking

E-Temp

Line 1

Marking

Device

Industrial

Line 1

Marking

E-Temp

Line 1

Marking

24AA00 201 24LC00 204 205 24C00 207 208

24AA01 211 24LC01B 214 215

24AA014 2N1 24LC014 2N4 2N5

24C01C 2N7 2N8

24AA02 221 24LC02B 224 225

24AA024 2P1 24LC024 2P4 2P5

24AA025 2R1 24LC025 2R4 2R5

24C02C 2P7 2P8

24AA04 231 24LC04B 234 235

24AA08 241 24LC08B 244 245

24AA16 251 24LC16B 254 255

24AA32A 261 24LC32A 264 265

24AA64 271 24LC64 274 275

Legend: XX...X Part number or part number code

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn) plated devices

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

24AAXX/24LCXX/24FCXX

Note: Temperature range (T) listed on second line. I = Industrial, E = Extended

8-Lead DFN Example: Pb-free

XXXXXXX

T/XXXXX

YYWW

24AA128

I/MF

0528

1L7

NNN

Example: Sn/Pb

24AA128

I/MF

0528

1L7

8-Lead 5x6mm DFN Package Marking (Pb-free)

Device Line 1

Marking Device Line 1

Marking

24AA128 24AA128 24LC128 24LC128 24FC128 24FC128

24AA256 24AA256 24LC256 24LC256 24FC256 24FC256

24AA512 24AA512 24LC512 24LC512 24FC512 24FC512

Legend: XX...X Part number or part number code

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn) plated devices

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

24AAXX/24LCXX/24FCXX

Example:

5-Lead SOT-23

XXNN 5EL7

5-Lead SOT-23 Package Marking (Pb-free)

Device Comm.

Marking

Indust.

Marking Device Comm.

Marking

Indust.

Marking

E-Temp

Marking Device Comm.

Marking

Indust.

Marking

E-Temp

Marking

24AA00 A0NN B0NN 24LC00 L0NN M0NN N0NN 24C00 C0NN D0NN E0NN

24AA01 A1NN B1NN 24LC01B L1NN M1NN N1NN

24AA02 A2NN B2NN 24LC02B L2NN M2NN N2NN

24AA04 A3NN B3NN 24LC04B L3NN M3NN N3NN

24AA08 A4NN B4NN 24LC08B L4NN M4NN N4NN

24AA16 A5NN B5NN 24LC16B L5NN M5NN N5NN

Legend: XX...X Part number or part number code

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn) plated devices

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

24AAXX/24LCXX/24FCXX

Note: T = Temperature range: I = Industrial, E = Extended, (blank) = Commercial

8-Lead MSOP (150 mil) Example:

XXXXXXT

YWWNNN

4L8BI

2281L7

8-Lead MSOP Package Marking (Pb-free)

Device Line 1

Marking Device Line 1

Marking

24AA01 4A01T 24LC01B 4L1BT

24AA014 4A14T 24LC014 4L14T

24C01C 4C1CT

24AA02 4A02T 24LC02B 4L2BT

24AA024 4A24T 24LC024 4L24T

24AA025 4A25T 24LC025 4L25T

24C02C 4C2CT

24AA04 4A04T 24LC04B 4L4BT

24AA08 4A08T 24LC08B 4L8BT

24AA16 4A16T 24LC16B 4L16T

24AA32A 4A32AT 24LC32A 4L32AT

24AA64 4A64T 24LC64 4L64T

24AA128 4A128T 24LC128 4L128T 24FC128 4F128T

24AA256 4A256T 24LC256 4L256T 24FC256 4F256T

Legend: XX...X Part number or part number code

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn) plated devices

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

24AAXX/24LCXX/24FCXX

Note: T = Temperature range: I = Industrial, E = Extended, (blank) = Commercial

NNN

XXXX

TYWW

8-Lead TSSOP

1L7

4L08

I228

Example:

8-Lead TSSOP Package Marking (Pb-free)

Device Line 1

Marking Device Line 1

Marking

24AA00 4A00 24LC00 4L00 24C00 4C00

24AA01 4A01 24LC01B 4L1B

24AA014 4A14 24LC014 4L14

24C01C 4C1C

24AA02 4A02 24LC02B 4L02

24AA024 4A24 24LC024 4L24

24AA025 4A25 24LC025 4L25

24C02C 4C2C

24AA04 4A04 24LC04B 4L04

24AA08 4A08 24LC08B 4L08

24AA16 4A16 24LC16B 4L16

24AA32A 4AA 24LC32A 4LA

24AA64 4AB 24LC64 4LB

24AA128 4AC 24LC128 4LC 24FC128 4FC

24AA256 4AD 24LC256 4LD 24FC256 4FD

Legend: XX...X Part number or part number code

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn) plated devices

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Note: T = Temperature range: I = Industrial, E = Extended

14-Lead TSSOP Example:

XXXXXXXT

YYWW

NNN

4A256I

0528

1L7

14-Lead TSSOP Package Marking (Pb-free)

Device Line 1

Marking Device Line 1

Marking

24AA128 4A128T 24LC128 4L128T 24FC128 4F128T

24AA256 4A256T 24LC256 4L256T 24FC256 4F256T

24AA512 4A512T 24LC512 4L512T 24FC512 4F512T

Legend: XX...X Part number or part number code

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn) plated devices

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

24AAXX/24LCXX/24FCXX

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α5 10 15 5 10 15

Mold Draft Angle Bottom β5 10 15 5 10 15

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001

Drawing No. C04-018

.010” (0.254mm) per side.

§ Significant Characteristic

24AAXX/24LCXX/24FCXX

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Foot Angle φ048048

1512015120

Mold Draft Angle Bottom

1512015120

Mold Draft Angle Top

0.510.420.33.020.017.013BLead Width

0.250.230.20.010.009.008

Lead Thickness

0.760.620.48.030.025.019LFoot Length

0.510.380.25.020.015.010hChamfer Distance

5.004.904.80.197.193.189DOverall Length

3.993.913.71.157.154.146

Molded Package Width

6.206.025.79.244.237.228EOverall Width

0.250.180.10.010.007.004

Standoff §

1.551.421.32.061.056.052A2Molded Package Thickness

1.751.551.35.069.061.053AOverall Height

1.27.050

Pitch

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

§ Significant Characteristic

24AAXX/24LCXX/24FCXX

8-Lead Plastic Dual Flat No Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated

Exposed Pad Width

Exposed Pad Length

Contact Length

*Controlling Parameter

Contact Width

Drawing No. C04-123

Notes:

Exposed pad dimensions vary with paddle size.

Overall Width

.016

.012

.008

.047

.055

.010

.118 BSC

Number of Pins

Standoff

Contact Thickness

Overall Length

Overall Height

Pitch p

Units

Dimension Limits

.000 .001

.008 REF.

.079 BSC

.031

.020 BSC

MIN

INCHES

NOM

0.40

0.25

3.00 BSC

0.30

.020

.071

.012

.064

0.20

1.20

1.39

0.50

0.30

1.80

1.62

0.02

0.80

2.00 BSC

0.20 REF.

0.50 BSC

MILLIMETERS*

.002

.039

0.00

MINMAX NOM

0.05

1.00

MAX

Package may have one or more exposed tie bars at ends.1.

Pin 1 visual index feature may vary, but must be located within the hatched area.2.

0.90.035

(Note 3)

4. JEDEC equivalent: MO-229

A3 A1

TOP VIEW

EXPOSED

PAD

METAL

BOTTOM VIEW

(NOTE 1)

EXPOSED

TIE BAR

PIN 1

(NOTE 2)

ID INDEX

AREA

Revised 05/24/04

-- --

24AAXX/24LCXX/24FCXX

8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) – Saw Singulated

24AAXX/24LCXX/24FCXX

5-Lead Plastic Small Outline Transistor (OT) (SOT-23)

10501050

Mold Draft Angle Bottom

10501050

Mold Draft Angle Top

0.500.430.35.020.017.014BLead Width

0.200.150.09.008.006.004

Lead Thickness

10501050

Foot Angle

0.550.450.35.022.018.014LFoot Length

3.102.952.80.122.116.110DOverall Length

1.751.631.50.069.064.059E1Molded Package Width

3.002.802.60.118.110.102EOverall Width

0.150.080.00.006.003.000A1Standoff

1.301.100.90.051.043.035A2Molded Package Thickness

1.451.180.90.057.046.035AOverall Height

1.90.075

Outside lead pitch (basic)

0.95

.038

Pitch

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERSINCHES*Units

exceed .005" (0.127mm) per side.

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

Notes:

EIAJ Equivalent: SC-74A

Drawing No. C04-091

*Controlling Parameter

24AAXX/24LCXX/24FCXX

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

(F)

n 1

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

.037 REF

FFootprint (Reference)

exceed .010" (0.254mm) per side.

Notes:

Drawing No. C04-111

*Controlling Parameter

Mold Draft Angle Top

Mold Draft Angle Bottom

Foot Angle

Lead Width

Lead Thickness

.003

.009

.006

.012

Dimension Limits

Overall Height

Molded Package Thickness

Molded Package Width

Overall Length

Foot Length

Standoff

Overall Width

Number of Pins

Pitch

.016 .024

.118 BSC

.000

.030

.193 TYP.

.033

MIN

Units

.026 BSC

NOM

INCHES

0.95 REF

.009

.016

0.08

0.22

0°

0.23

0.40

8°

MILLIMETERS*

0.65 BSC

0.85

3.00 BSC

0.60

4.90 BSC

.043

.031

.037

.006

0.40

0.00

0.75

MIN

MAX

NOM

1.10

0.80

0.15

0.95

MAX

15°5° -

JEDEC Equivalent: MO-187

0° - 8°

5°

5° -

15°

24AAXX/24LCXX/24FCXX

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

10501050

Mold Draft Angle Bottom

10501050

Mold Draft Angle Top

0.300.250.19.012.010.007BLead Width

0.200.150.09.008.006.004

Lead Thickness

0.700.600.50.028.024.020LFoot Length

3.103.002.90.122.118.114DMolded Package Length

4.504.404.30.177.173.169

Molded Package Width

6.506.386.25.256.251.246EOverall Width

0.150.100.05.006.004.002A1Standoff §

0.950.900.85.037.035.033

Molded Package Thickness

1.10.043AOverall Height

0.65.026

Pitch

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERS*INCHES

Units

Foot Angle φ048048

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-086

§ Significant Characteristic

24AAXX/24LCXX/24FCXX

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body (TSSOP)

840840

Foot Angle

10501050

Mold Draft Angle Bottom

10501050

Mold Draft Angle Top

0.300.250.19.012.010.007BLead Width

0.200.150.09.008.006.004

Lead Thickness

0.700.600.50.028.024.020LFoot Length

5.105.004.90.201.197.193DMolded Package Length

4.504.404.30.177.173.169E1Molded Package Width

6.506.386.25.256.251.246EOverall Width

0.150.100.05.006.004.002A1Standoff §

0.950.900.85.037.035.033

Molded Package Thickness

1.10.043AOverall Height

0.65.026

Pitch

1414

Number of Pins

MAXNOMMINMAXNOMMINDimension Limits

MILLIMETERS*INCHESUnits

A2A1

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-087

§ Significant Characteristic

24AAXX/24LCXX/24FCXX

NOTES:

24AAXX/24LCXX/24FCXX

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical support is available through the web site

at: http://support.microchip.com

In addition, there is a Development Systems

Information Line which lists the latest versions of

Microchip’s development systems software products.

This line also provides information on how customers

can receive currently available upgrade kits.

The Development Systems Information Line

numbers are:

1-800-755-2345 – United States and most of Canada

1-480-792-7302 – Other International Locations

24AAXX/24LCXX/24FCXX

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response

Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21930A24AAXX/24LCXX/24FCXX

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

24AAXX/24LCXX/24FCXX

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Note 1: Most products manufactured after January 2005 have a Matte Tin (Pb-free) finish.

Most products manufactured before January 2005 have a finish of approximately 63% Sn and 37% Pb (Sn/Pb).

Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion, including conversion date codes.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

Customer Notification System

PART NO.

X/XX

PackageTemperature

Range

Device Part

Examples:

a) 24C00/P: 128-bit, Commercial Temper-

ature, 5V, PDIP package

b) 24AA014-I/SN: 1 Kbit, Industrial

Temperature, 1.8V, SOIC package

c) 24AA02T-I/OT: 2 Kbit, Industrial

Temperature, 1.8V, SOT-23 package,

Tape and Reel

d) 24LC16B-I/P: 16 Kbit, Industrial Tempera-

ture, 2.5V, PDIP package

e) 24LC32A-E/MS: 32 Kbit, Extended

Temperature, 2.5V, MSOP package

f) 24LC64T-I/MC: 64 Kbit, Industrial

Temperature, 2.5V 2x3 mm DFN package,

Tape and Reel

g) 24LC256-E/STG: 256 Kbit, Extended

Temperature, 2.5V, TSSOP package,

Pb-free

h) 24FC512T-I/SM: 512 Kbit, Industrial

Temperature, 1 MHz, SOIC package,

Tape and Reel

Lead Finish

Device: See Table 1-1

Temperature

Range:

I = -40°C to +85°C

E = -40°C to +125°C

C = 0°C to +70°C

Packaging

Medium:

T = Tape and Reel

Blank = Tube

Package: P = Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC (150 mil body), 8-lead

SM = Plastic SOIC (208 mil body), 8-lead

ST = Plastic TSSOP (4.4 mm), 8-lead

ST14 = Plastic TSSOP (4.4 mm), 14-lead

MS = Plastic Micro Small Outline (MSOP), 8-lead

OT = SOT-23, 5-lead (Tape and Reel only)

MC = 2x3 mm DFN, 8-lead

MF = 5x6 mm DFN, 8-lead

Lead finish: Blank = Pb-free – Matte Tin (see Note 1)

G = Pb-free – Matte Tin only

Number

(Table 1-1)

Packaging

Medium

24AAXX/24LCXX/24FCXX

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. Use of Microchip’s products as critical components in

life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Linear Active Thermistor,

MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,

PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,

PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode,

Smart Serial, SmartTel, Total Endurance and WiperLock are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Atlanta

Alpharetta, GA

Tel: 770-640-0034

Fax: 770-640-0307

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

San Jose

Mountain View, CA

Tel: 650-215-1444

Fax: 650-961-0286

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8676-6200

Fax: 86-28-8676-6599

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

China - Qingdao

Tel: 86-532-502-7355

Fax: 86-532-502-7205

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-2229-0061

Fax: 91-80-2229-0062

India - New Delhi

Tel: 91-11-5160-8631

Fax: 91-11-5160-8632

Japan - Kanagawa

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Penang

Tel:011-604-646-8870

Fax:011-604-646-5086

Philippines - Manila

Tel: 011-632-634-9065

Fax: 011-632-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Taiwan - Hsinchu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

EUROPE

Austria - Weis

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

Denmark - Ballerup

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Massy

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Ismaning

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

England - Berkshire

Tel: 44-118-921-5869

Fax: 44-118-921-5820

WORLDWIDE SALES AND SERVICE

04/20/05