DAC5675A-SP www.ti.com SGLS387E - JULY 2007 - REVISED APRIL 2013 CLASS V, 14-BIT, 400-MSPS DIGITAL-TO-ANALOG CONVERTER Check for Samples: DAC5675A-SP FEATURES * * * * * * 1 * * * * * 400-MSPS Update Rate LVDS-Compatible Input Interface Spurious-Free Dynamic Range (SFDR) to Nyquist - 69 dBc at 70 MHz IF, 400 MSPS W-CDMA Adjacent Channel Power Ratio (ACPR) - 73 dBc at 30.72 MHz IF, 122.88 MSPS - 71 dBc at 61.44 MHz IF, 245.76 MSPS Differential Scalable Current Outputs: 2 mA to 20 mA On-Chip 1.2-V Reference Single 3.3-V Supply Operation Power Dissipation: 660 mW at fCLK = 400 MSPS, fOUT = 20 MHz High-Performance 52-Pin Ceramic Quad Flat Pack (HFG) QML-V Qualified, SMD 5962-07204 Military Temperature Range (-55C to 125C) APPLICATIONS * * Cellular Base Transceiver Station Transmit Channel: - CDMA: WCDMA, CDMA2000, IS-95 - TDMA: GSM, IS-136, EDGE/GPRS - Supports Single-Carrier and Multicarrier Applications Test and Measurement: Arbitrary Waveform Generation DESCRIPTION/ORDERING INFORMATION The DAC5675A is a 14-bit resolution high-speed digital-to-analog converter (DAC). The DAC5675A is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A has excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes it well suited for multicarrier transmission in TDMA and CDMA based cellular base transceiver stations (BTSs). The DAC5675A operates from a single supply voltage of 3.3 V. Power dissipation is 660 mW at fCLK = 400 MSPS, fOUT = 70 MHz. The DAC5675A provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD. The DAC5675A includes a low-voltage differential signaling (LVDS) interface for high-speed digital data input. LVDS features a low differential voltage swing with a low constant power consumption across frequency, allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference (EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for high-speed interfacing between the DAC5675A and high-speed low-voltage CMOS ASICs or FPGAs. The DAC5675A current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered input latches provide for minimum setup and hold times, thereby relaxing interface timing. The DAC5675A is specifically designed for a differential transformer-coupled output with a 50- doublyterminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (-2 dBm) is supported. The last configuration is preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and have voltage compliance ranges from AVDD - 1 to AVDD + 0.3 V. An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user to adjust this output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage may be applied. The DAC5675A features a SLEEP mode, which reduces the standby power to approximately 18 mW. The DAC5675A is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The device is specified for operation over the military temperature range of -55C to 125C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007-2013, Texas Instruments Incorporated DAC5675A-SP SGLS387E - JULY 2007 - REVISED APRIL 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. ORDERING INFORMATION (1) TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING 5962-0720401VXC 5962-0720401VXC DAC5675AMHFG-V DAC5675AHFGMPR DAC5675AHFG/EM (3) EVAL ONLY -55C to 125C 52 / HFG 25C (1) (2) (3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. No Burn-In, etc.) and are tested to a temperature rating of 25C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of -55C to 125C or operating life. FUNCTIONAL BLOCK DIAGRAM SLEEP DAC5675A Bandgap Reference 1.2V EXTIO BIASJ Current Source Array Output Current Switches Decoder DAC Latch + Drivers Control Amp 14 D[13:0]A LVDS Input Interface D[13:0]B Input Latches 14 CLK Clock Distribution CLKC AVDD(4x) AGND(4x) 2 DVDD(2x) DGND(2x) Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387E - JULY 2007 - REVISED APRIL 2013 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range AVDD (2) -0.3 to 3.6 DVDD (3) -0.3 to 3.6 AVDD to DVDD -3.6 to 3.6 Voltage between AGND and DGND CLK, CLKC (2) V -0.3 to 0.5 V -0.3 to AVDD + 0.3 V -0.3 to DVDD + 0.3 V IOUT1, IOUT2 (2) -1 to AVDD + 0.3 V (2) Digital input D[13:0]A, D[13:0]B (3), SLEEP, DLLOFF EXTIO, BIASJ -1 to AVDD + 0.3 V Peak input current (any input) 20 mA Peak total input current (all inputs) -30 mA Operating free-air temperature range, TA -55 to 125 C Storage temperature range -65 to 150 C 260 C Lead temperature 1,6 mm (1/16 in) from the case for 10 s (1) (2) (3) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Measured with respect to AGND Measured with respect to DGND Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 3 DAC5675A-SP SGLS387E - JULY 2007 - REVISED APRIL 2013 www.ti.com DC Electrical Characteristics (Unchanged after 100 kRad) over operating free-air temperature range, typical values at 25C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Resolution TYP MAX 14 DC Accuracy UNIT Bit (1) INL Integral nonlinearity TMIN to TMAX -4 1.5 4.6 DNL Differential nonlinearity T25C to TMAX -2 0.6 2.2 TMIN -2 0.6 2.5 Monotonicity LSB LSB Monotonic 12b Level Analog Output IO(FS) Full-scale output current Output compliance range AVDD = 3.15 V to 3.45 V, IO(FS) = 20 mA 2 20 AVDD - 1 AVDD + 0.3 Offset error Gain error 0.01 -10 5 10 With internal reference -10 2.5 10 Output capacitance V %FSR Without internal reference Output resistance mA %FSR 300 k 5 pF Reference Output V(EXTIO) Reference voltage 1.17 Reference output current (2) 1.23 1.30 100 V nA Reference Input V(EXTIO) Input reference voltage 0.6 Input resistance 1.2 1.25 V 1 M Small-signal bandwidth 1.4 MHz Input capacitance 100 pF 12 ppm of FSR/C 50 ppm/C Temperature Coefficients Offset drift V(EXTIO) Reference voltage drift Power Supply AVDD Analog supply voltage 3.15 DVDD Digital supply voltage 3.15 3.3 3.6 V I(AVDD) Analog supply current (3) 115 148 mA I(DVDD) Digital supply current (3) 85 130 mA PD Power dissipation APSRR Analog and digital power-supply rejection ratio DPSRR (1) (2) (3) 4 Sleep mode 3.6 18 AVDD = 3.3 V, DVDD = 3.3 V AVDD = 3.15 V to 3.45 V 3.3 660 900 -0.9 0.1 0.9 -0.9 0.1 0.9 V mW %FSR/V Measured differential at IOUT1 and IOUT2: 25 to AVDD Use an external buffer amplifier with high impedance input to drive any external load. Measured at fCLK = 400 MSPS and fOUT = 70 MHz Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387E - JULY 2007 - REVISED APRIL 2013 AC Electrical Characteristics (Unchanged after 100 kRad) over operating free-air temperature range, typical values at 25C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA, differential transformer-coupled output, 50- doubly-terminated load (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 400 MSPS Analog Output fCLK Output update rate ts(DAC) Output setting time to 0.1% tPD Output propagation delay tr(IOUT) Output rise time, 10% to 90% tf(IOUT) Output fall time, 90% to 10% Output noise Transition: code x2000 to x23FF 12 ns 1 ns 300 ps 300 ps IOUTFS = 20 mA 55 IOUTFS = 2 mA 30 pA/Hz AC Linearity THD fCLK = 100 MSPS, fOUT = 19.9 MHz 70 fCLK = 160 MSPS, fOUT = 41 MHz 72 fCLK = 200 MSPS, fOUT = 70 MHz Total harmonic distortion fCLK = 400 MSPS SFDR fOUT = 20.0 MHz, for TMIN 57 fOUT = 70 MHz 67 55 fOUT = 19.9 MHz 70 fCLK = 160 MSPS, fOUT = 41 MHz 73 fCLK = 200 MSPS, fOUT = 70 MHz 62 fOUT = 20.0 MHz, for TMIN 61 ACPR IMD 68 69 fOUT = 140 MHz 56 fCLK = 100 MSPS, fOUT = 19.9 MHz 82 fCLK = 160 MSPS, fOUT = 41 MHz 77 fCLK = 200 MSPS, fOUT = 70 MHz 82 fOUT = 20.0 MHz 82 fOUT = 70 MHz 82 fOUT = 140 MHz Signal-to-noise ratio fCLK = 400 MSPS fOUT = 20.0 MHz 67 73 fCLK = 245.76 MSPS, IF = 61.44 MHz, 71 fCLK = 399.36 MSPS, IF = 153.36 MHz, See Figure 13 65 Two-tone intermodulation to Nyquist (each tone at -6 dBfs) fCLK = 400 MSPS, fOUT1 = 70 MHz, fOUT2 = 71 MHz 73 fCLK = 400 MSPS, fOUT1 = 140 MHz, fOUT2 = 141 MHz 62 Four-tone intermodulation, 15-MHz span, missing center tone (each tone at -16 dBfs) fCLK = 156 MSPS, fOUT = 15.6, 15.8, 16.2, 16.4 MHz 82 fCLK = 400 MSPS, fOUT = 68.1, 69.3, 71.2, 72 MHz 74 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP dBc dBc 75 60 fCLK = 122.88 MSPS, IF = 30.72 MHz, See Figure 11 Adjacent channel power ratio WCDM A with 3.84 MHz BW, 5 MHz channel spacing dBc 70 fOUT = 20.0 MHz fOUT = 70 MHz fCLK = 400 MSPS SNR 68 fOUT = 140 MHz Spurious-free dynamic range to Nyquist Spurious-free dynamic range within a window, 5 MHz span 60 fCLK = 100 MSPS, fCLK = 400 MSPS SFDR 68 fOUT = 20.0 MHz dBc dB dBc 5 DAC5675A-SP SGLS387E - JULY 2007 - REVISED APRIL 2013 www.ti.com Digital Specifications (Unchanged after 100 kRad) over operating free-air temperature range, typical values at 25C, AVDD = 3.3 V, DVDD = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS Interface: Nodes D[13:0]A, D[13:0]B VITH+ Positive-going differential input voltage threshold 100 mV VITH- Negative-going differential input voltage threshold -100 mV ZT Internal termination impedance CI Input capacitance 90 110 132 2 pF CMOS Interface (SLEEP) VIH High-level input voltage VIL Low-level input voltage 2 IIH High-level input current -100 IIL Low-level input current -10 3.3 0 Input capacitance V 0.8 V 100 A 10 A 2 pF Clock Interface (CLK, CLKC) |CLK-CLKC| Clock differential input voltage tw(H) Clock pulse width high 1.25 ns tw(L) Clock pulse width low 1.25 ns VCM 0.4 Clock duty cycle 40 Common-mode voltage range 1.6 0.8 60 2 2.4 VPP % V Input resistance Node CLK, CLKC 670 Input capacitance Node CLK, CLKC 2 pF Input resistance Differential 1.3 k Input capacitance Differential 1 pF Timing tSU Input setup time 1.5 tH Input hold time 0.0 tDD Digital delay time (DAC latency) 6 ns ns 3 Submit Documentation Feedback clk Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387E - JULY 2007 - REVISED APRIL 2013 Timing Information Figure 1. Timing Diagram Electrical Characteristics (1) over operating free-air temperature range, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless otherwise noted) APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON-MODE INPUT VOLTAGE LOGICAL BIT BINARY EQUIVALENT VA (V) VB (V) VA,B (mV) VCOM (V) 1.25 1.15 100 1.2 1 1.15 1.25 -100 1.2 0 2.4 2.3 100 2.35 1 2.3 2.4 -100 2.35 0 0.1 0 100 0.05 1 0 0.1 -100 0.05 0 1.5 0.9 600 1.2 1 0.9 1.5 -600 1.2 0 2.4 1.8 600 2.1 1 1.8 2.4 -600 2.1 0 0.6 0 600 0.3 1 0 0.6 -600 0.3 0 (1) COMMENT Operation with minimum differential voltage (100 mV) applied to the complementary inputs versus common-mode range Operation with maximum differential voltage (600 mV) applied to the complementary inputs versus common-mode range Specifications subject to change. DVDD DAC5675A VA 1.4 V VB 1V VA, B VA, B 0.4 V 0V - 0.4 V VCOM = VA + VB 2 VA Logical Bit Equivalent VB DGND 1 0 Figure 2. LVDS Timing Test Circuit and Input Test Levels Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 7 DAC5675A-SP SGLS387E - JULY 2007 - REVISED APRIL 2013 www.ti.com NC SLEEP BIASJ EXTIO AVDD AGND IOUT2 IOUT1 AVDD AGND AGND AVDD AGND HFG PACKAGE (TOP VIEW) 52 51 50 49 48 47 46 45 44 43 42 41 40 D13A 1 39 AGND D13B 2 38 D0B D12A 3 37 D0A D12B D11A 4 36 D1B 5 35 D1A D11B 6 D2B D10A 7 34 33 D10B D9A 8 32 D3B 9 31 D3A D9B 10 30 D4B 11 29 D4A D8B 12 28 D5B AGND 13 27 D5A D8A D2A 8 D6B AGND CLK D6A CLKC AGND AVDD DGND DVDD DVDD DGND D7B D7A 14 15 16 17 18 19 20 21 22 23 24 25 26 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387E - JULY 2007 - REVISED APRIL 2013 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION AGND 13, 20, 26, 39, 44, 49, 50, 52 I Analog negative supply voltage (ground). Pin 13 is internally connected to the heat slug and lid (lid is also grounded internally). AVDD 21, 45, 48, 51 I Analog positive supply voltage BIASJ 42 O Full-scale output current bias CLK 23 I External clock input CLKC 22 I Complementary external clock D[13:0]A 1, 3, 5, 7, 9, 11, 14, 24, 27, 29, 31, 33, 35, 37 I LVDS positive input, data bits 13-0. D13A is the most significant data bit (MSB). D0A is the least significant data bit (LSB). D[13:0]B 2, 4, 6, 8, 10, 12, 15, 25, 28, 30, 32, 34, 36, 38 I LVDS negative input, data bits 13-0. D13B is the most significant data bit (MSB). D0B is the least significant data bit (LSB). DGND 17, 19 I Digital negative supply voltage (ground) DVDD 16, 18 I Digital positive supply voltage EXTIO 43 I/O Internal reference output or external reference input. Requires a 0.1-F decoupling capacitor to AGND when used as reference output. IOUT1 46 O DAC current output. Full-scale when all input bits are set '0'. Connect the reference side of the DAC load resistors to AVDD. IOUT2 47 O DAC complementary current output. Full-scale when all input bits are '1'. Connect the reference side of the DAC load resistors to AVDD. NC 41 SLEEP 40 Not connected in chip. Can be high or low. I Asynchronous hardware power-down input. Active high. Internal pulldown. Table 2. THERMAL INFORMATION PARAMETER RJA Junction-to-free-air thermal resistance RJC Junction-to-case thermal resistance TEST CONDITIONS TYP UNIT Board mounted, per JESD 51-5 methodology 21.813 C/W MIL-STD-883 test method 1012 0.849 C/W Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 9 DAC5675A-SP SGLS387E - JULY 2007 - REVISED APRIL 2013 www.ti.com THERMAL NOTES This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is required on the surface of the PCB directly under the body of the package. During normal surface mount flow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat removal. TI typically recommends an 11, 9 mm 2 board-mount thermal pad. This allows maximum area for thermal dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity of thermal/electrical vias must be included to keep the device within recommended operating conditions. This pad must be electrically ground potential. 70.00 60.00 Years estimated life 50.00 40.00 30.00 20.00 10.00 0.00 100 105 110 115 120 125 130 135 140 145 150 155 160 Continuous Tj (C) Figure 3. Estimated Device Life at Elevated Temperatures Electromigration Fail Modes 10 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387E - JULY 2007 - REVISED APRIL 2013 TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY (DNL) vs INPUT CODE INTEGRAL NONLINEARITY (INL) vs INPUT CODE 1.5 1.0 0.8 1.0 0.6 0.5 INL (LSB) DNL (LSB) 0.4 0.2 0 -0.2 0 -0.5 -0.4 -0.6 -1.0 -0.8 -1.0 -1.5 0 0 4000 6000 8000 10000 12000 14000 16000 0 -30 -40 8000 10000 12000 14000 16000 Figure 5. TWO-TONE IMD (POWER) vs FREQUENCY TWO-TONE IMD3 vs FREQUENCY -60 -70 -80 -90 -100 67 69 71 73 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 75 f2 - f1 = 1 MHz (-6 dBFS each) VCC = VAA = 3.3 V fCLK = 200 MHz 5 15 25 Frequency (MHz) 35 45 55 65 75 85 Center Frequency (MHz) Figure 6. Figure 7. SINGLE-TONE SPECTRUM POWER vs FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs FREQUENCY 0 80 VCC = VAA = 3.3 V fCLK = 400 MHz fOUT = 20.1 MHz, 0 dBFS SFDR = 74.75 dBc 20.1 MHz -10 -20 - 3 dBFS -30 -40 -50 40.06 MHz -60 70 -6 dBFS 65 0 dBFS 60 60.25 MHz -70 VCC = VAA = 3.3 V fclk = 400 MHz 75 SFDR (dBFS) Power (dBFS) 6000 Figure 4. -50 65 4000 Input Code Two-Tone IMD3 (dBc) -20 2000 Input Code f1 = 69.5 MHz, -6 dBFS f2 = 70.5 MHz, -6 dBFS IMD3 = 77.41 dBc VCC = VAA = 3.3 V fCLK = 200 MHz -10 Power (dBFS) 2000 -80 55 -90 0 20 40 60 80 100 120 140 Frequency (MHz) 160 180 200 50 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 Output Frequency (MHz) Figure 8. Figure 9. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 11 DAC5675A-SP SGLS387E - JULY 2007 - REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) W-CDMA TM1 SINGLE CARRIER POWER vs FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs FREQUENCY -25 85 -3 dBFS VCC = VAA = 3.3 V fclk= 200 MHz 80 Power (dBm/30kHz) -6 dBFS SFDR (dBFS) 75 0 dBFS 70 VCC = VAA = 3.3 V fCLK = 122.88 MHz fCENTER = 30.72 MHz ACLR = 72.29 dB - 35 65 -45 -55 -65 -75 -85 -95 60 -105 55 -115 18 50 10 20 30 40 50 60 70 80 90 100 110 23 28 120 33 38 43 Frequency Output Frequency (MHz) -30 Figure 11. W-CDMA TM1 DUAL CARRIER POWER vs FREQUENCY W-CDMA TM1 SINGLE CARRIER ACLR vs OUTPUT FREQUENCY V CC = V AA = 3.3 V fCENTER = 92.16 MHz 80 fCLK = 368.64 MHz 76 -50 74 -60 -70 -80 72 70 68 66 -90 64 -100 -110 82.2 VCC = VAA = 3.3 V fCLK = 399.36 MHz Single Channel 78 ACLR = 65 dBc ACLR (dBc) Power (dBm/30kHz) -40 Figure 10. 62 60 87.2 92.2 97.2 10.2 10 30 Frequency 70 90 110 130 150 Output Frequency (MHz) Figure 12. 12 50 Figure 13. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387E - JULY 2007 - REVISED APRIL 2013 APPLICATION INFORMATION Detailed Description Figure 14 shows a simplified block diagram of the current steering DAC5675A. The DAC5675A consists of a segmented array of NPN-transistor current sources, capable of delivering a full-scale output current up to 20 mA. Differential current switches direct the current of each current source to either one of the complementary output nodes IOUT1 or IOUT2. The complementary current output enables differential operation, canceling out common-mode noise sources (digital feedthrough, on-chip, and PCB noise), dc offsets, and even-order distortion components, and doubling signal output power. The full-scale output current is set using an external resistor (RBIAS) with an on-chip bandgap voltage reference source (1.2 V) and control amplifier. The current (IBIAS) through resistor RBIAS is mirrored internally to provide a full-scale output current equal to 16 times IBIAS. The full-scale current is adjustable from 20 mA down to 2 mA by using the appropriate bias resistor value. SLEEP 3.3 V (AVDD) DAC5675A Bandgap Reference 1.2 V 50 IOUT Output 1:1 EXTIO Current Source Array BIASJ CEXT 0.1 F Output Current Switches Control Amp RBIAS 1 k IOUT 50 RLOAD 50 3.3 V (AVDD) 14 D[13:0]A LVDS Input Interface D[13:0]B Input Latches Decoder 14 DAC Latch + Drivers 3.3 V (AVDD) CLK 1:4 Clock Input 100 RT 200 Clock Distribution CLKC AVDD(4x) AGND(4x) DVDD(2x) DGND(2x) Figure 14. Application Simplified Block Diagram Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 13 DAC5675A-SP SGLS387E - JULY 2007 - REVISED APRIL 2013 www.ti.com Digital Inputs The DAC5675A uses a low-voltage differential signaling (LVDS) bus input interface. The LVDS features a low differential voltage swing with low constant power consumption (4 mA per complementary data input) across frequency. The differential characteristic of LVDS allows for high-speed data transmission with low electromagnetic interference (EMI) levels. Figure 15 shows the equivalent complementary digital input interface for the DAC5675A, valid for pins D[13:0]A and D[13:0]B. Note that the LVDS interface features internal 110- resistors for proper termination. Figure 2 shows the LVDS input timing measurement circuit and waveforms. A common-mode level of 1.2 V and a differential input swing of 0.8 VPP is applied to the inputs. Figure 16 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5675A, valid for the SLEEP pin. DVDD DAC5675A D[13..0]A DAC5675A 110 Termination Resistor Internal Digital In D[13..0]B D[13:0]A D[13:0]B Internal Digital In DGND Figure 15. LVDS Digital Equivalent Input DVDD DAC5675A Internal Digital In Digital Input DGND Figure 16. CMOS/TTL Digital Equivalent Input Clock Input The DAC5675A features differential LVPECL-compatible clock inputs (CLK, CLKC). Figure 17 shows the equivalent schematic of the clock input buffer. The internal biasing resistors set the input common-mode voltage to approximately 2 V, while the input resistance is typically 670 . A variety of clock sources can be ac-coupled to the device, including a sine-wave source (see Figure 18). 14 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387E - JULY 2007 - REVISED APRIL 2013 AVDD DAC5675A R1 1 k R1 1 k Internal Clock CLK CLKC R2 2 k R2 2 k AGND Figure 17. Clock Equivalent Input Optional, may be bypassed for sinewave input Swing Limitation CAC 0.1 F 1:4 CLK RT 200 DAC5675A CLKC Termination Resistor Figure 18. Driving the DAC5675A With a Single-Ended Clock Source Using a Transformer To obtain best ac performance, the DAC5675A clock input should be driven with a differential LVPECL or sinewave source as shown in Figure 19 and Figure 20. Here, the potential of VTT should be set to the termination voltage required by the driver along with the proper termination resistors (RT). The DAC5675A clock input can also be driven single ended; this is shown in Figure 21. Single-Ended ECL or (LV)PECL Source CAC 0.01 F ECL/PECL Gate CLK CAC 0.01 F DAC5675A CLKC RT 50 RT 50 VTT Figure 19. Driving the DAC5675A With a Single-Ended ECL/PECL Clock Source Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 15 DAC5675A-SP SGLS387E - JULY 2007 - REVISED APRIL 2013 www.ti.com CAC 0.01 F Differential ECL or (LV)PECL Source CLK + CAC 0.01 F DAC5675A - RT 50 CLKC RT 50 VTT Figure 20. Driving the DAC5675A With a Differential ECL/PECL Clock Source TTL/CMOS Source DAC5675A CLK ROPT 22 CLKC 0.01 F Node CLKC Internally Biased to AVDD/2 Figure 21. Driving the DAC5675A With a Single-Ended TTL/CMOS Clock Source Supply Inputs The DAC5675A comprises separate analog and digital supplies, (AVDD and DVDD) respectively. These supply inputs can be set independently from 3.6 V down to 3.15 V. DAC Transfer Function The DAC5675A has a current sink output. The current flow through IOUT1 and IOUT2 is controlled by D[13:0]A and D[13:0]B. For ease of use, D[13:0] is denoted as the logical bit equivalent of D[13:0]A and its complement D[13:0]B. The DAC5675A supports straight binary coding with D13 being the MSB and D0 the LSB. Full-scale current flows through IOUT2 when all D[13:0] inputs are set high and through IOUT1 when all D[13:0] inputs are set low. The relationship between IOUT1 and IOUT2 can be expressed as Equation 1: (1) IO(FS) is the full-scale output current sink (2 mA to 20 mA). Because the output stage is a current sink, the current can only flow from AVDD through the load resistors RL into the IOUT1 and IOUT2 pins. The output current flow in each pin driving a resistive load can be expressed as shown in Figure 22, as well as in Equation 2 and Equation 3. Figure 22. Relationship Between D[13:0], IOUT1 and IOUT2 16 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387E - JULY 2007 - REVISED APRIL 2013 (2) (3) where CODE is the decimal representation of the DAC input word. This would translate into single-ended voltages at IOUT1 and IOUT2, as shown in Equation 4 and Equation 5: (4) (5) Assuming that D[13:0] = 1 and the RL is 50, the differential voltage between pins IOUT1 and IOUT2 can be expressed as shown in Equation 6 through Equation 8: (6) (7) (8) If D[13:0] = 0, then IOUT2 = 0mA and IOUT1 = 20mA and the differential voltage VDIFF = -1V. The output currents and voltages in IOUT1 and IOUT2 are complementary. The voltage, when measured differentially, is doubled compared to measuring each output individually. Care must be taken not to exceed the compliance voltages at the IOUT1 and IOUT2 pins to keep signal distortion low. Reference Operation The DAC5675A has a bandgap reference and control amplifier for biasing the full-scale output current. The fullscale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current equals 16 times this bias current. The full-scale output current IO(FS) is thus expressed as Equation 9: 16 V EXTIO I O(FS) + 16 I BIAS + RBIAS (9) where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers a stable voltage of 1.2 V. This reference can be overridden by applying an external voltage to terminal EXTIO. The bandgap reference can additionally be used for external reference operation. In such a case, an external buffer amplifier with high impedance input should be selected to limit the bandgap load current to less than 100 nA. The capacitor CEXT may be omitted. Terminal EXTIO serves as either an input or output node. The full-scale output current is adjustable from 20 mA down to 2 mA by varying resistor RBIAS. Analog Current Outputs Figure 23 shows a simplified schematic of the current source array output with corresponding switches. Differential NPN switches direct the current of each individual NPN current source to either the positive output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack of the current sources and differential switches and is >300 k in parallel with an output capacitance of 5 pF. The external output resistors are referred to the positive supply AVDD. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 17 DAC5675A-SP SGLS387E - JULY 2007 - REVISED APRIL 2013 www.ti.com 3.3 V AVDD RLOAD RLOAD IOUT1 IOUT2 DAC5675A S(1) S(1)C S(2) S(2)C S(N) S(N)C Current Sink Array AGND Figure 23. Equivalent Analog Current Output The DAC5675A easily can be configured to drive a doubly-terminated 50- cable using a properly selected transformer. Figure 24 and Figure 25 show the 1:1 and 4:1 impedance ratio configuration, respectively. These configurations provide maximum rejection of common-mode noise sources and even-order distortion components, thereby doubling the power of the DAC to the output. The center tap on the primary side of the transformer is terminated to AVDD, enabling a dc-current flow for both IOUT1 and IOUT2. Note that the ac performance of the DAC5675A is optimum and specified using a 1:1 differential transformer-coupled output. 3.3 V AVDD DAC5675A 50 1:1 IOUT1 100 RLOAD 50 IOUT2 50 3.3 V AVDD Figure 24. Driving a Doubly Terminated 50- Cable Using a 1:1 Impedance Ratio Transformer 18 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP DAC5675A-SP www.ti.com SGLS387E - JULY 2007 - REVISED APRIL 2013 3.3 V AVDD 100 DAC5675A 4:1 IOUT1 RLOAD 50 IOUT2 15 100 3.3 V AVDD Figure 25. Driving a Doubly Terminated 50 Cable Using a 4:1 Impedance Ratio Transformer Figure 26(a) shows the typical differential output configuration with two external matched resistor loads. The nominal resistor load of 25 gives a differential output swing of 1 VPP (0.5 VPP single ended) when applying a 20-mA full-scale output current. The output impedance of the DAC5675A slightly depends on the output voltage at nodes IOUT1 and IOUT2. Consequently, for optimum dc-integral nonlinearity, the configuration of Figure 26(b) should be chosen. In this current/voltage (I-V) configuration, terminal IOUT1 is kept at AVDD by the inverting operational amplifier. The complementary output should be connected to AVDD to provide a dc-current path for the current sources switched to IOUT1. The amplifier maximum output swing and the full-scale output current of the DAC determine the value of the feedback resistor RFB. The capacitor CFB filters the steep edges of the DAC5675A current output, thereby reducing the operational amplifier slew-rate requirements. In this configuration, the operational amplifier should operate at a supply voltage higher than the resistor output reference voltage AVDD as a result of its positive and negative output swing around AVDD. Node IOUT1 should be selected if a single-ended unipolar output is desired. 3.3 V AVDD DAC5675A CFB 200 (RFB) DAC5675A 25 IOUT1 VOUT1 IOUT2 VOUT2 25 IOUT1 VOUT IOUT2 Optional, for singleended output referred to AVDD 3.3 V AVDD (a) 3.3 V AVDD (b) Figure 26. Output Configurations Sleep Mode The DAC5675A features a power-down mode that turns off the output current and reduces the supply current to approximately 6 mA. The power-down mode is activated by applying a logic level one to the SLEEP pin, pulled down internally. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP 19 DAC5675A-SP SGLS387E - JULY 2007 - REVISED APRIL 2013 www.ti.com DEFINITIONS Definitions of Specifications and Terminology Gain error is as the percentage error in the ratio between the measured full-scale output current and the value of 16 x V(EXTIO)/RBIAS. A V(EXTIO) of 1.25 V is used to measure the gain error with an external reference voltage applied. With an internal reference, this error includes the deviation of V(EXTIO) (internal bandgap reference voltage) from the typical value of 1.25 V. Offset error is as the percentage error in the ratio of the differential output current (IOUT1-IOUT2) and the half of the full-scale output current for input code 8192. THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental output signal. SNR is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral components below the Nyquist frequency, including noise, but excluding the first six harmonics and dc. SINAD is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral components below the Nyquist frequency, including noise and harmonics, but excluding dc. ACPR or adjacent channel power ratio is defined for a 3.84-Mcps 3GPP W-CDMA input signal measured in a 3.84-MHz bandwidth at a 5-MHz offset from the carrier with a 12-dB peak-to-average ratio. APSSR or analog power supply ratio is the percentage variation of full-scale output current versus a 5% variation of the analog power supply AVDD from the nominal. This is a dc measurement. DPSSR or digital power supply ratio is the percentage variation of full-scale output current versus a 5% variation of the digital power supply DVDD from the nominal. This is a dc measurement. 20 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: DAC5675A-SP PACKAGE OPTION ADDENDUM www.ti.com 6-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty 5962-0720401VXC ACTIVE CFP HFG 52 DAC5675AHFG/EM PREVIEW CFP HFG 52 1 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking TBD Call TI N / A for Pkg Type -55 to 125 5962-0720401VX C DAC5675AMHFG-V TBD Call TI N / A for Pkg Type 25 Only DAC5675AHFG/EM EVAL ONLY (4/5) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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