DAC5675A-SP
www.ti.com
SGLS387E –JULY 2007–REVISED APRIL 2013
CLASS V, 14-BIT, 400-MSPS DIGITAL-TO-ANALOG CONVERTER
Check for Samples: DAC5675A-SP
1FEATURES • High-Performance 52-Pin Ceramic Quad Flat
Pack (HFG)
• 400-MSPS Update Rate • QML-V Qualified, SMD 5962-07204
• LVDS-Compatible Input Interface • Military Temperature Range (–55°C to 125°C)
• Spurious-Free Dynamic Range (SFDR) to
Nyquist APPLICATIONS
– 69 dBc at 70 MHz IF, 400 MSPS • Cellular Base Transceiver Station Transmit
• W-CDMA Adjacent Channel Power Ratio Channel:
(ACPR) – CDMA: WCDMA, CDMA2000, IS-95
– 73 dBc at 30.72 MHz IF, 122.88 MSPS – TDMA: GSM, IS-136, EDGE/GPRS
– 71 dBc at 61.44 MHz IF, 245.76 MSPS – Supports Single-Carrier and Multicarrier
• Differential Scalable Current Outputs: Applications
2 mA to 20 mA • Test and Measurement: Arbitrary Waveform
• On-Chip 1.2-V Reference Generation
• Single 3.3-V Supply Operation
• Power Dissipation: 660 mW at
fCLK = 400 MSPS, fOUT = 20 MHz
DESCRIPTION/ORDERING INFORMATION
The DAC5675A is a 14-bit resolution high-speed digital-to-analog converter (DAC). The DAC5675A is designed
for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct
digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A has
excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes it well suited for
multicarrier transmission in TDMA and CDMA based cellular base transceiver stations (BTSs).
The DAC5675A operates from a single supply voltage of 3.3 V. Power dissipation is 660 mW at
fCLK = 400 MSPS, fOUT = 70 MHz. The DAC5675A provides a nominal full-scale differential current output of
20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the
load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD.
The DAC5675A includes a low-voltage differential signaling (LVDS) interface for high-speed digital data input.
LVDS features a low differential voltage swing with a low constant power consumption across frequency,
allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference
(EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for
high-speed interfacing between the DAC5675A and high-speed low-voltage CMOS ASICs or FPGAs. The
DAC5675A current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered
input latches provide for minimum setup and hold times, thereby relaxing interface timing.
The DAC5675A is specifically designed for a differential transformer-coupled output with a 50-Ωdoubly-
terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output
power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration is preferred
for optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and
have voltage compliance ranges from AVDD – 1 to AVDD + 0.3 V.
An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user to
adjust this output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities.
Alternatively, an external reference voltage may be applied. The DAC5675A features a SLEEP mode, which
reduces the standby power to approximately 18 mW.
The DAC5675A is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The device is specified for
operation over the military temperature range of –55°C to 125°C.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Bandgap
Reference
1.2V
Control Amp
Current
Source
Array
Output
Current
Switches
DAC
Latch
+
Drivers
Decoder
Input
Latches
LVDS
Input
Interface
Clock Distribution
SLEEP
EXTIO
BIASJ
D[13:0]A
D[13:0]B
CLK
CLKC
AVDD(4x) AGND(4x) DVDD(2x) DGND(2x)
14
14
DAC5675A
DAC5675A-SP
SGLS387E –JULY 2007–REVISED APRIL 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION(1)
TAPACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING
5962-0720401VXC
–55°C to 125°C 5962-0720401VXC DAC5675AMHFG-V
52 / HFG DAC5675AHFG/EM(3)
25°C DAC5675AHFGMPR EVAL ONLY
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. No Burn-In, etc.) and are
tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts
are not warranted for performance over the full MIL specified temperature range of -55°C to 125°C or operating life.
FUNCTIONAL BLOCK DIAGRAM
2Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DAC5675A-SP
DAC5675A-SP
www.ti.com
SGLS387E –JULY 2007–REVISED APRIL 2013
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
AVDD (2) –0.3 to 3.6
Supply voltage range DVDD (3) –0.3 to 3.6 V
AVDD to DVDD –3.6 to 3.6
Voltage between AGND and DGND –0.3 to 0.5 V
CLK, CLKC(2) –0.3 to AVDD + 0.3 V
Digital input D[13:0]A, D[13:0]B(3), SLEEP, DLLOFF –0.3 to DVDD + 0.3 V
IOUT1, IOUT2(2) –1 to AVDD + 0.3 V
EXTIO, BIASJ(2) –1 to AVDD + 0.3 V
Peak input current (any input) 20 mA
Peak total input current (all inputs) –30 mA
Operating free-air temperature range, TA–55 to 125 °C
Storage temperature range –65 to 150 °C
Lead temperature 1,6 mm (1/16 in) from the case for 10 s 260 °C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to AGND
(3) Measured with respect to DGND
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DAC5675A-SP
DAC5675A-SP
SGLS387E –JULY 2007–REVISED APRIL 2013
www.ti.com
DC Electrical Characteristics (Unchanged after 100 kRad)
over operating free-air temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 14 Bit
DC Accuracy(1)
INL Integral nonlinearity TMIN to TMAX –4 ±1.5 4.6 LSB
DNL Differential nonlinearity T25C to TMAX –2 ±0.6 2.2 LSB
TMIN –2 ±0.6 2.5
Monotonicity Monotonic 12b Level
Analog Output
IO(FS) Full-scale output current 2 20 mA
AVDD = 3.15 V to 3.45 V,
Output compliance range AVDD – 1 AVDD + 0.3 V
IO(FS) = 20 mA
Offset error 0.01 %FSR
Without internal reference –10 5 10
Gain error %FSR
With internal reference –10 2.5 10
Output resistance 300 kΩ
Output capacitance 5 pF
Reference Output
V(EXTIO) Reference voltage 1.17 1.23 1.30 V
Reference output current(2) 100 nA
Reference Input
V(EXTIO) Input reference voltage 0.6 1.2 1.25 V
Input resistance 1 MΩ
Small-signal bandwidth 1.4 MHz
Input capacitance 100 pF
Temperature Coefficients
Offset drift 12 ppm of FSR/°C
ΔV(EXTIO) Reference voltage drift ±50 ppm/°C
Power Supply
AVDD Analog supply voltage 3.15 3.3 3.6 V
DVDD Digital supply voltage 3.15 3.3 3.6 V
I(AVDD) Analog supply current(3) 115 148 mA
I(DVDD) Digital supply current(3) 85 130 mA
Sleep mode 18
PDPower dissipation mW
AVDD = 3.3 V, DVDD = 3.3 V 660 900
APSRR –0.9 ±0.1 0.9
Analog and digital AVDD = 3.15 V to 3.45 V %FSR/V
power-supply rejection ratio
DPSRR –0.9 ±0.1 0.9
(1) Measured differential at IOUT1 and IOUT2: 25 Ωto AVDD
(2) Use an external buffer amplifier with high impedance input to drive any external load.
(3) Measured at fCLK = 400 MSPS and fOUT = 70 MHz
4Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DAC5675A-SP
DAC5675A-SP
www.ti.com
SGLS387E –JULY 2007–REVISED APRIL 2013
AC Electrical Characteristics (Unchanged after 100 kRad)
over operating free-air temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA, differential
transformer-coupled output, 50-Ωdoubly-terminated load (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Output
fCLK Output update rate 400 MSPS
ts(DAC) Output setting time to 0.1% Transition: code x2000 to x23FF 12 ns
tPD Output propagation delay 1 ns
tr(IOUT) Output rise time, 10% to 90% 300 ps
tf(IOUT) Output fall time, 90% to 10% 300 ps
IOUTFS = 20 mA 55
Output noise pA/√Hz
IOUTFS = 2 mA 30
AC Linearity
fCLK = 100 MSPS, fOUT = 19.9 MHz 70
fCLK = 160 MSPS, fOUT = 41 MHz 72
fCLK = 200 MSPS, fOUT = 70 MHz 68
THD Total harmonic distortion fOUT = 20.0 MHz 60 68 dBc
fOUT = 20.0 MHz, for TMIN 57
fCLK = 400 MSPS fOUT = 70 MHz 67
fOUT = 140 MHz 55
fCLK = 100 MSPS, fOUT = 19.9 MHz 70
fCLK = 160 MSPS, fOUT = 41 MHz 73
fCLK = 200 MSPS, fOUT = 70 MHz 70
Spurious-free dynamic range
SFDR fOUT = 20.0 MHz 62 68 dBc
to Nyquist fOUT = 20.0 MHz, for TMIN 61
fCLK = 400 MSPS fOUT = 70 MHz 69
fOUT = 140 MHz 56
fCLK = 100 MSPS, fOUT = 19.9 MHz 82
fCLK = 160 MSPS, fOUT = 41 MHz 77
fCLK = 200 MSPS, fOUT = 70 MHz 82
Spurious-free dynamic range
SFDR dBc
within a window, 5 MHz span fOUT = 20.0 MHz 82
fCLK = 400 MSPS fOUT = 70 MHz 82
fOUT = 140 MHz 75
SNR Signal-to-noise ratio fCLK = 400 MSPS fOUT = 20.0 MHz 60 67 dBc
fCLK = 122.88 MSPS, IF = 30.72 MHz, See Figure 11 73
Adjacent channel power ratio
ACPR WCDM A with 3.84 MHz BW, fCLK = 245.76 MSPS, IF = 61.44 MHz, 71 dB
5 MHz channel spacing fCLK = 399.36 MSPS, IF = 153.36 MHz, See Figure 13 65
Two-tone intermodulation fCLK = 400 MSPS, fOUT1 = 70 MHz, fOUT2 = 71 MHz 73
to Nyquist (each tone at fCLK = 400 MSPS, fOUT1 = 140 MHz, fOUT2 = 141 MHz 62
–6 dBfs)
IMD dBc
Four-tone intermodulation, fCLK = 156 MSPS, fOUT = 15.6, 15.8, 16.2, 16.4 MHz 82
15-MHz span, missing center fCLK = 400 MSPS, fOUT = 68.1, 69.3, 71.2, 72 MHz 74
tone (each tone at –16 dBfs)
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DAC5675A-SP
DAC5675A-SP
SGLS387E –JULY 2007–REVISED APRIL 2013
www.ti.com
Digital Specifications (Unchanged after 100 kRad)
over operating free-air temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVDS Interface: Nodes D[13:0]A, D[13:0]B
Positive-going differential input
VITH+ 100 mV
voltage threshold
Negative-going differential input
VITH– –100 mV
voltage threshold
ZTInternal termination impedance 90 110 132 Ω
CIInput capacitance 2 pF
CMOS Interface (SLEEP)
VIH High-level input voltage 2 3.3 V
VIL Low-level input voltage 0 0.8 V
IIH High-level input current –100 100 μA
IIL Low-level input current –10 10 μA
Input capacitance 2 pF
Clock Interface (CLK, CLKC)
|CLK-CLKC| Clock differential input voltage 0.4 0.8 VPP
tw(H) Clock pulse width high 1.25 ns
tw(L) Clock pulse width low 1.25 ns
Clock duty cycle 40 60 %
VCM Common-mode voltage range 1.6 2 2.4 V
Input resistance Node CLK, CLKC 670 Ω
Input capacitance Node CLK, CLKC 2 pF
Input resistance Differential 1.3 kΩ
Input capacitance Differential 1 pF
Timing
tSU Input setup time 1.5 ns
tHInput hold time 0.0 ns
tDD Digital delay time (DAC latency) 3 clk
6Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DAC5675A-SP
VA+ VB
2
VCOM =
VA
VB
VA, B
VA, B
VB
VA
DVDD
DGND
Logical Bit
Equivalent
1.4 V
1 V
0.4 V
−0.4 V
1
0
0 V
DAC5675A
DAC5675A-SP
www.ti.com
SGLS387E –JULY 2007–REVISED APRIL 2013
Timing Information
Figure 1. Timing Diagram
Electrical Characteristics(1)
over operating free-air temperature range, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless otherwise noted)
RESULTING RESULTING LOGICAL BIT
APPLIED DIFFERENTIAL COMMON-MODE BINARY COMMENT
VOLTAGES INPUT VOLTAGE INPUT VOLTAGE EQUIVALENT
VA(V) VB(V) VA,B (mV) VCOM (V)
1.25 1.15 100 1.2 1
1.15 1.25 –100 1.2 0 Operation with minimum differential voltage
2.4 2.3 100 2.35 1 (±100 mV) applied to the complementary inputs
2.3 2.4 –100 2.35 0 versus common-mode range
0.1 0 100 0.05 1
0 0.1 –100 0.05 0
1.5 0.9 600 1.2 1
0.9 1.5 –600 1.2 0 Operation with maximum differential voltage
2.4 1.8 600 2.1 1 (±600 mV) applied to the complementary inputs
1.8 2.4 –600 2.1 0 versus common-mode range
0.6 0 600 0.3 1
0 0.6 –600 0.3 0
(1) Specifications subject to change.
Figure 2. LVDS Timing Test Circuit and Input Test Levels
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: DAC5675A-SP
39
38
37
36
35
34
32
33
31
30
29
28
27
AGND
D0B
D0A
D1B
D1A
D2B
D2A
D3B
D3A
D4B
D4A
D5B
D5A
1
2
3
4
5
6
7
8
9
10
11
12
13
D13A
D13B
D12A
D12B
D11A
D11B
D10A
D10B
D9A
D9B
D8A
D8B
AGND
D6A
D6B
AGND
DGND
DVDD
DGND
CLKC
CLK
D7B
DVDD
14 15 16 17 18
19
20 21 22 23 24 25 26
AVDD
D7A
AGND
HFGPACKAGE
(TOPVIEW)
NC
AVDD
AGND
AVDD
AGND
AGND
EXTIO
BIASJ
SLEEP
51 50 49 48 4752 46
44
43
42
45 41 40
AGND
IOUT2
AVDD
IOUT1
DAC5675A-SP
SGLS387E –JULY 2007–REVISED APRIL 2013
www.ti.com
8Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DAC5675A-SP
DAC5675A-SP
www.ti.com
SGLS387E –JULY 2007–REVISED APRIL 2013
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NAME NO.
13, 20, 26, 39, 44, 49, 50, Analog negative supply voltage (ground). Pin 13 is internally connected to the heat
AGND I
52 slug and lid (lid is also grounded internally).
AVDD 21, 45, 48, 51 I Analog positive supply voltage
BIASJ 42 O Full-scale output current bias
CLK 23 I External clock input
CLKC 22 I Complementary external clock
LVDS positive input, data bits 13–0.
1, 3, 5, 7, 9, 11, 14, 24, 27,
D[13:0]A I D13A is the most significant data bit (MSB).
29, 31, 33, 35, 37 D0A is the least significant data bit (LSB).
LVDS negative input, data bits 13–0.
2, 4, 6, 8, 10, 12, 15, 25,
D[13:0]B I D13B is the most significant data bit (MSB).
28, 30, 32, 34, 36, 38 D0B is the least significant data bit (LSB).
DGND 17, 19 I Digital negative supply voltage (ground)
DVDD 16, 18 I Digital positive supply voltage
Internal reference output or external reference input. Requires a 0.1-μF decoupling
EXTIO 43 I/O capacitor to AGND when used as reference output.
DAC current output. Full-scale when all input bits are set '0'. Connect the reference
IOUT1 46 O side of the DAC load resistors to AVDD.
DAC complementary current output. Full-scale when all input bits are '1'. Connect the
IOUT2 47 O reference side of the DAC load resistors to AVDD.
NC 41 Not connected in chip. Can be high or low.
SLEEP 40 I Asynchronous hardware power-down input. Active high. Internal pulldown.
Table 2. THERMAL INFORMATION
PARAMETER TEST CONDITIONS TYP UNIT
Junction-to-free-air thermal
RθJA Board mounted, per JESD 51-5 methodology 21.813 °C/W
resistance
RθJC Junction-to-case thermal resistance MIL-STD-883 test method 1012 0.849 °C/W
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: DAC5675A-SP
0.00
10.00
20.00
30.00
40.00
50.00
60.00
70.00
100 105 110 115 120 125 130 135 140 145 150 155 160
Continuous Tj (°C)
Years estimated life
DAC5675A-SP
SGLS387E –JULY 2007–REVISED APRIL 2013
www.ti.com
THERMAL NOTES
This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the
bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is
required on the surface of the PCB directly under the body of the package. During normal surface mount flow
solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an
efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a
thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat
removal. TI typically recommends an 11, 9 mm 2 board-mount thermal pad. This allows maximum area for
thermal dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity
of thermal/electrical vias must be included to keep the device within recommended operating conditions. This
pad must be electrically ground potential.
Figure 3. Estimated Device Life at Elevated Temperatures Electromigration Fail Modes
10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DAC5675A-SP
50
55
60
65
70
75
80
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
Output Frequency (MHz)
SFDR (dBFS)
VCC = VAA = 3.3 V
fclk = 400 MHz
0 dBFS
- 3 dBFS
-6 dBFS
Frequency (MHz)
Power (dBFS)
0 4020
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
80 10060 120 140 160 180 200
VCC = VAA = 3.3 V
fCLK = 400 MHz
fOUT = 20.1 MHz, 0 dBFS
SFDR = 74.75 dBc
20.1 MHz
40.06 MHz
60.25 MHz
Frequency (MHz)
Power (dBFS)
65
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
67 69 71 73 75
f1=69.5MHz, −6dBFS
f2=70.5MHz, −6dBFS
IMD3=77.41dBc
VCC =VAA=3.3V
fCLK =200MHz
Center Frequency (MHz)
Two-ToneIMD3(dBc)
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
5 15 25 35 45 55 65 75 85
f2−f1= 1MHz( 6dBFSeach)–
VCC = VAA = 3.3 V
fCLK = 200MHz
InputCode
DNL(LSB)
0 2000
1.0
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1.0
4000 6000 8000 10000 12000 14000 16000
Input Code
INL (LSB)
0 2000
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
4000 6000 8000 10000 12000 14000 16000
DAC5675A-SP
www.ti.com
SGLS387E –JULY 2007–REVISED APRIL 2013
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY (DNL) INTEGRAL NONLINEARITY (INL)
vs vs
INPUT CODE INPUT CODE
Figure 4. Figure 5.
TWO-TONE IMD (POWER) TWO-TONE IMD3
vs vs
FREQUENCY FREQUENCY
Figure 6. Figure 7.
SINGLE-TONE SPECTRUM
POWER SPURIOUS-FREE DYNAMIC RANGE
vs vs
FREQUENCY FREQUENCY
Figure 8. Figure 9.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: DAC5675A-SP
Output Frequency (MHz)
ACLR (dBc)
80
78
76
74
72
70
68
66
64
62
60
10 30 50 70 90 110 130 150
VCC = VAA = 3.3 V
fCLK = 399.36 MHz
Single Channel
50
55
60
65
70
75
80
85
10 20 30 40 50 60 70 80 90 100 110 120
Output Frequency (MHz)
SFDR (dBFS)
0 dBFS
-3 dBFS
-6 dBFS
VCC = VAA = 3.3 V
fclk= 200 MHz
Frequency
Power (dBm/30kHz)
18
−25
−35
−45
−55
−65
−75
−85
−95
−105
−115
23 28 33 38 43
VCC = VAA = 3.3 V
fCLK = 122.88 MHz
fCENTER = 30.72 MHz
ACLR = 72.29 dB
DAC5675A-SP
SGLS387E –JULY 2007–REVISED APRIL 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
W-CDMA TM1 SINGLE CARRIER
SPURIOUS-FREE DYNAMIC RANGE POWER
vs vs
FREQUENCY FREQUENCY
Figure 10. Figure 11.
W-CDMA TM1 DUAL CARRIER W-CDMA TM1 SINGLE CARRIER
POWER ACLR
vs vs
FREQUENCY OUTPUT FREQUENCY
Figure 12. Figure 13.
12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DAC5675A-SP
Bandgap
Reference
1.2 V
Control Amp
Current
Source
Array
Output
Current
Switches
DAC
Latch
+
Drivers
Decoder
Input
Latches
LVDS
Input
Interface
Clock Distribution
SLEEP
EXTIO
BIASJ
D[13:0]A
D[13:0]B
CLK
CLKC
DVDD(2x) DGND(2x)
14
14
AVDD(4x) AGND(4x)
CEXT
0.1 Fµ
RBIAS
1 kΩ
1:4
Clock
Input
RT
200 Ω
3.3V
(AVDD)
3.3V
(AVDD)
3.3V
(AVDD)
100 Ω
50 Ω
50 Ω
IOUT
IOUT
1:1 Output
RLOAD
50 Ω
DAC5675A
DAC5675A-SP
www.ti.com
SGLS387E –JULY 2007–REVISED APRIL 2013
APPLICATION INFORMATION
Detailed Description
Figure 14 shows a simplified block diagram of the current steering DAC5675A. The DAC5675A consists of a
segmented array of NPN-transistor current sources, capable of delivering a full-scale output current up to 20 mA.
Differential current switches direct the current of each current source to either one of the complementary output
nodes IOUT1 or IOUT2. The complementary current output enables differential operation, canceling out
common-mode noise sources (digital feedthrough, on-chip, and PCB noise), dc offsets, and even-order distortion
components, and doubling signal output power.
The full-scale output current is set using an external resistor (RBIAS) with an on-chip bandgap voltage reference
source (1.2 V) and control amplifier. The current (IBIAS) through resistor RBIAS is mirrored internally to provide a
full-scale output current equal to 16 times IBIAS. The full-scale current is adjustable from
20 mA down to 2 mA by using the appropriate bias resistor value.
Figure 14. Application Simplified Block Diagram
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: DAC5675A-SP
Internal
Digital In
DVDD
DGND
Digital Input
DAC5675A
Internal
DigitalIn
110 Ω
Termination
Resistor
Internal
Digital In
D[13:0]A
D[13..0]A
D[13..0]B
D[13:0]B
DGND
DVDD
DAC5675A DAC5675A
DAC5675A-SP
SGLS387E –JULY 2007–REVISED APRIL 2013
www.ti.com
Digital Inputs
The DAC5675A uses a low-voltage differential signaling (LVDS) bus input interface. The LVDS features a low
differential voltage swing with low constant power consumption (4 mA per complementary data input) across
frequency. The differential characteristic of LVDS allows for high-speed data transmission with low
electromagnetic interference (EMI) levels. Figure 15 shows the equivalent complementary digital input interface
for the DAC5675A, valid for pins D[13:0]A and D[13:0]B. Note that the LVDS interface features internal 110-Ω
resistors for proper termination. Figure 2 shows the LVDS input timing measurement circuit and waveforms. A
common-mode level of 1.2 V and a differential input swing of 0.8 VPP is applied to the inputs.
Figure 16 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5675A, valid for
the SLEEP pin.
Figure 15. LVDS Digital Equivalent Input
Figure 16. CMOS/TTL Digital Equivalent Input
Clock Input
The DAC5675A features differential LVPECL-compatible clock inputs (CLK, CLKC). Figure 17 shows the
equivalent schematic of the clock input buffer. The internal biasing resistors set the input common-mode voltage
to approximately 2 V, while the input resistance is typically 670 Ω. A variety of clock sources can be ac-coupled
to the device, including a sine-wave source (see Figure 18).
14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DAC5675A-SP
CLK
CLKC
Single-Ended
ECL
or
(LV)PECL
Source
ECL/PECL
Gate
CAC
RT
50 Ω
RT
50 Ω
VTT
CAC
0.01 µF
0.01 µF
DAC5675A
CLK
CLKC
Optional, may be
bypassedforsine-
waveinput
RT
200 Ω
Swing Limitation
Termination
Resistor
1:4
CAC
0.1 µF
DAC5675A
Internal
Clock
CLKC
AGND
AVDD
CLK
R1
1kΩ
R1
1kΩ
R2
2kΩ
R2
2kΩ
DAC5675A
DAC5675A-SP
www.ti.com
SGLS387E –JULY 2007–REVISED APRIL 2013
Figure 17. Clock Equivalent Input
Figure 18. Driving the DAC5675A With a Single-Ended Clock Source Using a Transformer
To obtain best ac performance, the DAC5675A clock input should be driven with a differential LVPECL or sine-
wave source as shown in Figure 19 and Figure 20. Here, the potential of VTT should be set to the termination
voltage required by the driver along with the proper termination resistors (RT). The DAC5675A clock input can
also be driven single ended; this is shown in Figure 21.
Figure 19. Driving the DAC5675A With a Single-Ended ECL/PECL Clock Source
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: DAC5675A-SP
CLK
CLKC
0.01µF
ROPT
22 Ω
TTL/CMOS
Source
Node CLKC
Internally Biased to
AVDD/2
DAC5675A
CLK
CLKC
CAC
RT
50 Ω
RT
50 Ω
VTT
CAC
0.01 µF
0.01 µF
Differential
ECL
or
(LV)PECL
Source
+
−
DAC5675A
DAC5675A-SP
SGLS387E –JULY 2007–REVISED APRIL 2013
www.ti.com
Figure 20. Driving the DAC5675A With a Differential ECL/PECL Clock Source
Figure 21. Driving the DAC5675A With a Single-Ended TTL/CMOS Clock Source
Supply Inputs
The DAC5675A comprises separate analog and digital supplies, (AVDD and DVDD) respectively. These supply
inputs can be set independently from 3.6 V down to 3.15 V.
DAC Transfer Function
The DAC5675A has a current sink output. The current flow through IOUT1 and IOUT2 is controlled by D[13:0]A
and D[13:0]B. For ease of use, D[13:0] is denoted as the logical bit equivalent of D[13:0]A and its complement
D[13:0]B. The DAC5675A supports straight binary coding with D13 being the MSB and D0 the LSB. Full-scale
current flows through IOUT2 when all D[13:0] inputs are set high and through IOUT1 when all D[13:0] inputs are
set low. The relationship between IOUT1 and IOUT2 can be expressed as Equation 1:
(1)
IO(FS) is the full-scale output current sink (2 mA to 20 mA). Because the output stage is a current sink, the current
can only flow from AVDD through the load resistors RLinto the IOUT1 and IOUT2 pins.
The output current flow in each pin driving a resistive load can be expressed as shown in Figure 22, as well as in
Equation 2 and Equation 3.
Figure 22. Relationship Between D[13:0], IOUT1 and IOUT2
16 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DAC5675A-SP
IO(FS)+16 IBIAS +16 VEXTIO
RBIAS
DAC5675A-SP
www.ti.com
SGLS387E –JULY 2007–REVISED APRIL 2013
(2)
(3)
where CODE is the decimal representation of the DAC input word. This would translate into single-ended
voltages at IOUT1 and IOUT2, as shown in Equation 4 and Equation 5:
(4)
(5)
Assuming that D[13:0] = 1 and the RLis 50Ω, the differential voltage between pins IOUT1 and IOUT2 can be
expressed as shown in Equation 6 through Equation 8:(6)
(7)
(8)
If D[13:0] = 0, then IOUT2 = 0mA and IOUT1 = 20mA and the differential voltage VDIFF = –1V.
The output currents and voltages in IOUT1 and IOUT2 are complementary. The voltage, when measured
differentially, is doubled compared to measuring each output individually. Care must be taken not to exceed the
compliance voltages at the IOUT1 and IOUT2 pins to keep signal distortion low.
Reference Operation
The DAC5675A has a bandgap reference and control amplifier for biasing the full-scale output current. The full-
scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor RBIAS is
defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current equals
16 times this bias current. The full-scale output current IO(FS) is thus expressed as Equation 9:
(9)
where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers a stable voltage of 1.2 V.
This reference can be overridden by applying an external voltage to terminal EXTIO. The bandgap reference can
additionally be used for external reference operation. In such a case, an external buffer amplifier with high
impedance input should be selected to limit the bandgap load current to less than 100 nA. The capacitor CEXT
may be omitted. Terminal EXTIO serves as either an input or output node. The full-scale output current is
adjustable from 20 mA down to 2 mA by varying resistor RBIAS.
Analog Current Outputs
Figure 23 shows a simplified schematic of the current source array output with corresponding switches.
Differential NPN switches direct the current of each individual NPN current source to either the positive output
node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the
stack of the current sources and differential switches and is >300 kΩin parallel with an output capacitance
of 5 pF.
The external output resistors are referred to the positive supply AVDD.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: DAC5675A-SP
IOUT1
IOUT2
3.3V
AVDD
3.3V
AVDD
50 Ω
50 Ω
100 Ω
1:1
RLOAD
50 Ω
DAC5675A
S(1) S(1)C S(2)C S(N)CS(2) S(N)
Current Sink Array
IOUT1 IOUT2
RLOAD
RLOAD
3.3V
AVDD
AGND
DAC5675A
DAC5675A-SP
SGLS387E –JULY 2007–REVISED APRIL 2013
www.ti.com
Figure 23. Equivalent Analog Current Output
The DAC5675A easily can be configured to drive a doubly-terminated 50-Ωcable using a properly selected
transformer. Figure 24 and Figure 25 show the 1:1 and 4:1 impedance ratio configuration, respectively. These
configurations provide maximum rejection of common-mode noise sources and even-order distortion
components, thereby doubling the power of the DAC to the output. The center tap on the primary side of the
transformer is terminated to AVDD, enabling a dc-current flow for both IOUT1 and IOUT2. Note that the ac
performance of the DAC5675A is optimum and specified using a 1:1 differential transformer-coupled output.
Figure 24. Driving a Doubly Terminated 50-ΩCable Using a 1:1 Impedance Ratio Transformer
18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DAC5675A-SP
(a)
VOUT
3.3V
AVDD
3.3V
AVDD
25 Ω
25 Ω
VOUT1
VOUT2
Optional, for single-
ended output
referred to AVDD
IOUT1
IOUT2
CFB
IOUT1
IOUT2
3.3V
AVDD
200 Ω(RFB)
(b)
DAC5675A DAC5675A
IOUT1
IOUT2
3.3V
AVDD
3.3V
AVDD
100 Ω
100 Ω
4:1
RLOAD
50 Ω
15 Ω
DAC5675A
DAC5675A-SP
www.ti.com
SGLS387E –JULY 2007–REVISED APRIL 2013
Figure 25. Driving a Doubly Terminated 50 ΩCable Using a 4:1 Impedance Ratio Transformer
Figure 26(a) shows the typical differential output configuration with two external matched resistor loads. The
nominal resistor load of 25 Ωgives a differential output swing of 1 VPP (0.5 VPP single ended) when applying a
20-mA full-scale output current. The output impedance of the DAC5675A slightly depends on the output voltage
at nodes IOUT1 and IOUT2. Consequently, for optimum dc-integral nonlinearity, the configuration of Figure 26(b)
should be chosen. In this current/voltage (I-V) configuration, terminal IOUT1 is kept at AVDD by the inverting
operational amplifier. The complementary output should be connected to AVDD to provide a dc-current path for
the current sources switched to IOUT1. The amplifier maximum output swing and the full-scale output current of
the DAC determine the value of the feedback resistor RFB. The capacitor CFB filters the steep edges of the
DAC5675A current output, thereby reducing the operational amplifier slew-rate requirements. In this
configuration, the operational amplifier should operate at a supply voltage higher than the resistor output
reference voltage AVDD as a result of its positive and negative output swing around AVDD. Node IOUT1 should be
selected if a single-ended unipolar output is desired.
Figure 26. Output Configurations
Sleep Mode
The DAC5675A features a power-down mode that turns off the output current and reduces the supply current to
approximately 6 mA. The power-down mode is activated by applying a logic level one to the SLEEP pin, pulled
down internally.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: DAC5675A-SP
DAC5675A-SP
SGLS387E –JULY 2007–REVISED APRIL 2013
www.ti.com
DEFINITIONS
Definitions of Specifications and Terminology
Gain error is as the percentage error in the ratio between the measured full-scale output current and the value of
16 × V(EXTIO)/RBIAS.AV(EXTIO) of 1.25 V is used to measure the gain error with an external reference voltage
applied. With an internal reference, this error includes the deviation of V(EXTIO) (internal bandgap reference
voltage) from the typical value of 1.25 V.
Offset error is as the percentage error in the ratio of the differential output current (IOUT1-IOUT2) and the half
of the full-scale output current for input code 8192.
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental output
signal.
SNR is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral
components below the Nyquist frequency, including noise, but excluding the first six harmonics and dc.
SINAD is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral
components below the Nyquist frequency, including noise and harmonics, but excluding dc.
ACPR or adjacent channel power ratio is defined for a 3.84-Mcps 3GPP W-CDMA input signal measured in a
3.84-MHz bandwidth at a 5-MHz offset from the carrier with a 12-dB peak-to-average ratio.
APSSR or analog power supply ratio is the percentage variation of full-scale output current versus a 5% variation
of the analog power supply AVDD from the nominal. This is a dc measurement.
DPSSR or digital power supply ratio is the percentage variation of full-scale output current versus a 5% variation
of the digital power supply DVDD from the nominal. This is a dc measurement.
20 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DAC5675A-SP
PACKAGE OPTION ADDENDUM
www.ti.com 6-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-0720401VXC ACTIVE CFP HFG 52 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-0720401VX
C
DAC5675AMHFG-V
DAC5675AHFG/EM PREVIEW CFP HFG 52 TBD Call TI N / A for Pkg Type 25 Only DAC5675AHFG/EM
EVAL ONLY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 6-Nov-2013
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC5675A-SP :
•Catalog: DAC5675A
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated