User Defined Fault Protection and
Detection,10 Ω RON, Quad Channel Protector
Data Sheet
ADG5462F
Rev. C Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
User defined secondary supplies set overvoltage level
Overvoltage protection up to −55 V and +55 V
Power-off protection up to −55 V and +55 V
Overvoltage detection on source pins
Minimum secondary supply level: 4.5 V single-supply
Interrupt flag indicates fault status
Low on resistance: 10 Ω typical
On-resistance flatness: 0.5 Ω maximum
4 kV human body model (HBM) ESD rating
Latch-up immune under any circumstance
VSS to VDD analog signal range
±5 V to ±22 V dual supply operation
8 V to 44 V single-supply operation
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
APPLICATIONS
Analog input/output modules
Process control/distributed control systems
Data acquisition
Instrumentation
Avionics
Automatic test equipment
Communication systems
FUNCTIONAL BLOCK DIAGRAM
ADG5462F
V
DD
V
SS
D1
S1
S2
S3
S4
V
IN
V
OUT
D2
D3
D4
POSFV DRNEGFV
FF
12698-001
Figure 1.
GENERAL DESCRIPTION
The ADG5462F contains four channels that are overvoltage
protected. The channel protector is placed in series with the signal
path and protects sensitive components from overvoltage faults
in that path. The channel protector prevents overvoltages when
powered and unpowered, and it is ideal for use in applications
where correct power supply sequencing cannot always be guaranteed.
The primary supply voltages define the on-resistance profile,
while the secondary supply voltages define the voltage level at
which the overvoltage protection engages.
When no power supplies are present, the channel remains in the off
condition, and the channel inputs are high impedance. Under
normal operating conditions, if the analog input signal levels on
any Sx pin exceed positive fault voltage (POSFV) or negative fault
voltage (NEGFV) by a threshold voltage (VT), the channel turns
off and that Sx pin becomes high impedance. If the DR pin is
driven low, the drain pin (Dx) is pulled to the secondary supply
voltage that was exceeded. The output profile for each DR voltage
level is shown in Figure 49. Input signal levels up to −55 V or
+55 V relative to ground are blocked in both the powered and
unpowered conditions.
The low on-resistance of these switches, combined with the
on-resistance flatness over a significant portion of the signal
range make them an ideal solution for data acquisition and
instrumentation applications where excellent linearity and low
distortion are critical.
PRODUCT HIGHLIGHTS
1. Source pins (Sx) are protected against voltages greater than
the secondary supply rails (POSFV and NEGFV), up to
−55 V and +55 V.
2. In an unpowered state, source pins (Sx) are protected
against voltages from −55 V to +55 V.
3. Overvoltage detection with digital output indicates the
operating state of the channels.
4. Trench isolation guards against latch-up.
5. Optimized for low on-resistance and on-resistance flatness.
6. The ADG5462F operates from a dual power supply range of
±5 V to ±22 V or a single power supply range of 8 V to 44 V.
ADG5462F Data Sheet
Rev. C | Page 2 of 29
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
±20 V Dual Supply ....................................................................... 5
12 V Single Supply ........................................................................ 7
36 V Single Supply ........................................................................ 9
Continuous Current per Channel, Sx or Dx ........................... 10
Absolute Maximum Ratings .......................................................... 11
ESD Caution ................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 13
Test Circuits ..................................................................................... 19
Terminology .................................................................................... 23
Theory of Operation ...................................................................... 24
Switch Architecture .................................................................... 24
User Defined Fault Protection .................................................. 25
Applications Information .............................................................. 27
Power Supply Rails ..................................................................... 27
Power Supply Sequencing Protection ...................................... 27
Power Supply Recommendations ............................................. 27
User Defined Signal Range ....................................................... 27
Low Impedance Channel Protection ....................................... 27
High Voltage Surge Suppression .............................................. 27
Intelligent Fault Detection ........................................................ 28
Large Voltage, High Frequency Signals ................................... 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
10/2017—Rev. B to Rev. C
Changes to Fault Drain Leakage Current With Overvoltage
Parameter, Table 1 ............................................................................. 3
Changes to Fault Drain Leakage Current With Overvoltage
Parameter, Table 2 ............................................................................. 7
Changes to Fault Drain Leakage Current With Overvoltage
Parameter, Table 4 ............................................................................ 9
Updated Outline Dimensions ....................................................... 29
Changes to Ordering Guide .......................................................... 29
1/2016—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Channel On Leakage, ID (On), IS (On) Maximum
Parameter, Table 2 .............................................................................. 5
Changes to Table 3 ............................................................................ 7
Changes to Table 4 ............................................................................ 9
5/2015—Rev. 0 to Rev. A
Added 16-Lead LFCSP Package ....................................... Universal
Changes to Drain Leakage Current, ID, with Overvoltage
Parameter Test Condition/Comment, Table 3 ............................... 7
Changes to Drain Leakage Current, ID, with Overvoltage
Parameter Test Condition/Comment, Table 4 ............................... 9
Changes to Table 5 .......................................................................... 10
Changes to Table 6 .......................................................................... 11
Added Figure 3; Renumbered Sequentially ................................ 12
Changes to Table 7 .......................................................................... 12
Added Figure 54 ............................................................................. 29
Updated Outline Dimensions ....................................................... 29
Changes to Ordering Guide .......................................................... 29
1/2015—Revision 0: Initial Versi on
Data Sheet ADG5462F
Rev. C | Page 3 of 29
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 1.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH VDD = +13.5 V, VSS = −13.5 V, see Figure 35
Analog Signal Range VDD to VSS V
On Resistance, RON 10 Ω typ VS = ±10 V, IS = −10 mA
11.2 14 16.5 Ω max
9.5 Ω typ VS = ±9 V, IS = −10 mA
10.7 13.5 16 Ω max
On-Resistance Match Between Channels, ∆RON 0.05 Ω typ VS = ±10 V, IS = −10 mA
0.5 0.6 0.7 Ω max
0.05 Ω typ VS = ±9 V, IS = −10 mA
0.35 0.5 0.5 Ω max
On-Resistance Flatness, RFLAT(O N) 0.6 Ω typ VS = ±10 V, IS = −10 mA
0.9 1.1 1.1 Ω max
0.1
Ω typ
V
S
= ±9 V, I
S
= −10 mA
0.4 0.5 0.5 Ω max
Threshold Voltage, VT 0.7 V typ See Figure 23
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Channel On Leakage, ID (On), IS (On) ±0.3 nA typ VS = VD = ±10 V, see Figure 36
±1.5 ±2.0 ±4.5 nA max
FAULT
Source Leakage Current, IS
With Overvoltage ±78 µA typ VDD = +16.5 V, VSS = −16.5 V, GND = 0 V,
VS = ±55 V, see Figure 37
Power Supplies Grounded or Floating ±40 µA typ VDD = 0 V or floating, VSS = 0 V or floating,
GND = 0 V, VS = ±55 V, see Figure 38
Drain Leakage Current, ID DR = floating or VDD
With Overvoltage ±2.0 nA typ VDD = +16.5 V, VSS = −16.5 V, GND = 0 V,
VS = ±55 V, see Figure 37
±20 ±30 ±65 nA max
Power Supplies Grounded ±10 nA typ VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±55 V, see Figure 38
±30 ±50 ±100 nA max
Power Supplies Floating ±10 ±10 ±10 µA typ VDD = floating, VSS = floating, GND = 0 V,
VS = ±55 V, see Figure 38
DIGITAL INPUTS/OUTPUTS (DR/FF)
Input Voltage High, VINH 2.0 V min
Input Voltage Low, VINL 0.8 V max
Input Current, IINL or IINH ±0.7 µA typ VIN = VGND or VDD
µA max
Digital Input Capacitance, CIN 5.0 pF typ
Output Voltage High, VOH 2.0 V min
Output Voltage Low, VOL 0.8 V max
ADG5462F Data Sheet
Rev. C | Page 4 of 29
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
DYNAMIC CHARACTERISTICS1
Overvoltage Response Time, tRESPONSE 460 ns typ RL = 1 kΩ, CL = 2 pF, see Figure 42
585 615 630 ns max
Overvoltage Recovery Time, tRECOVERY 720 ns typ RL = 1 kΩ, CL = 2 pF, see Figure 43
930 1050 1100 ns max
Drain Pull-Up/Pull-Down Time Following
Overvoltage, tRESPONSE (DR)
4 µs typ CL = 12 pF, see Figure 47
Interrupt Flag Response Time, t
DIGRESP
85
ns typ
C
L
= 12 pF, see Figure 44
Interrupt Flag Recovery Time, t
DIGREC
60
µs typ
C
L
= 12 pF, see Figure 45
600 ns typ CL = 12 pF, RPULLUP = 1 kΩ, see Figure 46
Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
Total Harmonic Distortion Plus Noise, THD + N 0.0015 % typ RL = 10 kΩ, VS = 15 V p-p,
f = 20 Hz to 20 kHz, see Figure 41
−3 dB Bandwidth 318 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 40
Insertion Loss
–0.8
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 40
CD (On), CS (On) 24 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
V
DD
= POSFV = +16.5 V, V
SS
= NEGFV = −16.5 V,
GND = 0 V
Normal Mode
IDD 0.9 mA typ
IPOSFV 0.1 mA typ
IDD + IPOSFV 1.2 1.3 mA max
I
GND
0.4
mA typ
0.55 0.6 mA max
ISS 0.5 mA typ
INEGFV 0.1 mA typ
ISS + INEGFV 0.65 0.7 mA max
Fault Mode VS = ±55 V
IDD 1.2 mA typ
IPOSFV 0.1 mA typ
IDD + IPOSFV 1.6 1.8 mA max
IGND 0.8 mA typ
1.0 1.1 mA max
ISS 0.5 mA typ
INEGFV 0.1 mA typ
ISS + INEGFV 1.0 1.8 mA max
VDD/VSS ±5 V min GND = 0 V
±22 V max GND = 0 V
1 Guaranteed by design; not subject to production test.
Data Sheet ADG5462F
Rev. C | Page 5 of 29
±20 V DUAL SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 2.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH VDD = +18 V, VSS = −18 V, see Figure 35
Analog Signal Range VDD to VSS V
On Resistance, RON 10 Ω typ VS = ±15 V, IS = −10 mA
11.5
14.5
16.5
Ω max
9.5 Ω typ VS = ±13.5 V, IS = −10 mA
11 14 16.5 Ω max
On-Resistance Match Between Channels, ∆RON 0.05 Ω typ VS = ±15 V, IS = −10 mA
0.35 0.5 0.5 Ω max
0.05 Ω typ VS = ±13.5 V, IS = −10 mA
0.35 0.5 0.5 Ω max
On-Resistance Flatness, RFLAT(O N) 1.0 Ω typ VS = ±15 V, IS = −10 mA
1.4 1.5 1.5 Ω max
0.1 Ω typ VS = ±13.5 V, IS = −10 mA
0.4 0.5 0.5 Ω max
Threshold Voltage, VT 0.7 V typ See Figure 23
LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V
Channel On Leakage, ID (On), IS (On) ±0.3 nA typ VS = VD = ±15 V, see Figure 36
±1.5
±2.0
±4.5
nA max
FAULT
Source Leakage Current, I
S
With Overvoltage
±78
µA typ
V
DD
= +22 V, V
SS
= −22 V, GND = 0 V,
VS = ±55 V, see Figure 37
Power Supplies Grounded or Floating ±40 µA typ VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, VS = ±55 V,
see Figure 38
Drain Leakage Current, ID DR = floating or VDD
With Overvoltage ±5.0 nA typ VDD = +22 V, VSS = −22 V, GND = 0 V,
VS = ±55 V, see Figure 37
±1.0 ±1.0 ±1.0 µA max
Power Supplies Grounded ±10 nA typ VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±55 V, see Figure 38
±30 ±50 ±100 nA max
Power Supplies Floating ±10 ±10 ±10 µA typ VDD = floating, VSS = floating, GND = 0 V,
VS = ±55 V, see Figure 38
DIGITAL INPUTS/OUTPUTS
Input Voltage High, VINH 2.0 V min
Input Voltage Low, VINL 0.8 V max
Input Current, IINL or IINH 0.7 µA typ VIN = VGND or VDD
1.2 µA max
Digital Input Capacitance, CIN 5.0 pF typ
Output Voltage High, VOH 2.0 V min
Output Voltage Low, VOL 0.8 V max
ADG5462F Data Sheet
Rev. C | Page 6 of 29
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
DYNAMIC CHARACTERISTICS1
Overvoltage Response Time, tRESPONSE 370 ns typ RL = 1 kΩ, CL = 2 pF, see Figure 42
480 500 515 ns max
Overvoltage Recovery Time, tRECOVERY 840 ns typ RL = 1 kΩ, CL = 2 pF, see Figure 43
1200 1400 1700 ns max
Drain Pull-Up/Pull-Down Time Following
Overvoltage, tRESPONSE (DR)
4 µs typ CL = 12 pF, see Figure 47
Interrupt Flag Response Time, t
DIGRESP
85
115
ns typ
C
L
= 12 pF, see Figure 44
Interrupt Flag Recovery Time, t
DIGREC
60
85
µs typ
C
L
= 12 pF, see Figure 45
600 ns typ CL = 12 pF, RPULLUP = 1 kΩ, see Figure 46
Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
Total Harmonic Distortion Plus Noise, THD + N 0.001 % typ RL = 10 kΩ, VS = 20 V p-p,
f = 20 Hz to 20 kHz, see Figure 41
−3 dB Bandwidth 310 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 40
Insertion Loss
–0.8
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 40
CD (On), CS (On) 23 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
V
DD
= POSFV = +22 V, V
SS
= NEGFV = −22 V
Normal Mode
IDD 0.9 mA typ
IPOSFV 0.1 mA typ
IDD + IPOSFV 1.2 1.3 mA max
IGND 0.4 mA typ
0.55 0.6 mA max
ISS 0.5 mA typ
INEGFV 0.1 mA typ
ISS + INEGFV 0.65 0.7 mA max
Fault Mode VS = ±55 V
IDD 1.2 mA typ
IPOSFV 0.1 mA typ
IDD + IPOSFV 1.6 1.8 mA max
IGND 0.8 mA typ
1.0 1.1 mA max
ISS 0.5 mA typ
I
NEGFV
0.1
mA typ
ISS + INEGFV 1.0 1.8 mA max
VDD/VSS ±5 V min GND = 0 V
±22 V max GND = 0 V
1 Guaranteed by design; not subject to production test.
Data Sheet ADG5462F
Rev. C | Page 7 of 29
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, G N D = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 3.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH VDD = +10.8 V, VSS = 0 V, see Figure 35
Analog Signal Range 0 V to VDD V
On Resistance, RON 22 Ω typ VS = 0 V to +10 V, IS = −10 mA
24.5
31
37
Ω max
10 Ω typ VS = +3.5 V to +8.5 V, IS = −10 mA
11.2 14 16.5 Ω max
On-Resistance Match Between Channels, ∆RON 0.05 Ω typ VS = 0 V to +10 V, IS = −10 mA
0.5 0.6 0.7 Ω max
0.05 Ω typ VS = +3.5 V to +8.5 V, IS = −10 mA
0.5 0.6 0.7 Ω max
On-Resistance Flatness, RFLAT(O N) 12.5 Ω typ VS = 0 V to +10 V, IS = −10 mA
14.5 19 23 Ω max
0.6 Ω typ VS = +3.5 V to +8.5 V, IS = −10 mA
0.9 1.1 1.3 Ω max
Threshold Voltage, VT 0.7 V typ See Figure 23
LEAKAGE CURRENTS VDD = +13.2 V, VSS = 0 V
Channel On Leakage, ID (On), IS (On) ±0.3 nA typ VS = VD = 1 V/10 V, see Figure 36
±1.5
±2.0
±4.5
nA max
FAULT
Source Leakage Current, I
S
With Overvoltage
±78
µA typ
V
DD
= +13.2 V, V
SS
= 0 V, GND = 0 V,
VS = ±55 V, see Figure 37
Power Supplies Grounded or Floating ±40 µA typ VDD = 0 V or floating, VSS = 0 V or floating,
GND = 0 V, VS = ±55 V, see Figure 38
Drain Leakage Current, ID DR = floating or VDD
With Overvoltage ±2.0 nA typ VDD = +13.2 V, VSS = 0 V, GND = 0 V, VS = ±55 V,
see Figure 37
±20 ±30 ±65 nA max
Power Supplies Grounded ±10 nA typ VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = ±55 V, see Figure 38
±30
±50
±100
nA max
Power Supplies Floating
±10
±10
±10
µA typ
V
DD
= floating, V
SS
= floating,
GND = 0 V, VS = ±55 V, see Figure 38
DIGITAL INPUTS/OUTPUTS
Input Voltage High, V
INH
2.0
V min
Input Voltage Low, VINL 0.8 V max
Input Current, IINL or IINH 0.7 µA typ VIN = VGND or VDD
1.2 µA max
Digital Input Capacitance, CIN 5.0 pF typ
Output Voltage High, V
OH
2.0
V min
Output Voltage Low, VOL 0.8 V max
ADG5462F Data Sheet
Rev. C | Page 8 of 29
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
DYNAMIC CHARACTERISTICS1
Overvoltage Response Time, tRESPONSE 560 ns typ RL = 1 kΩ, CL = 2 pF, see Figure 42
660 700 720 ns max
Overvoltage Recovery Time, tRECOVERY 640 ns typ RL = 1 kΩ, CL = 2 pF, see Figure 43
800 865 960 ns max
Drain Pull-Up/Pull-Down Time Following
Overvoltage, tRESPONSE (DR)
4 µs typ CL = 12 pF, see Figure 47
Interrupt Flag Response Time, t
DIGRESP
85
115
ns typ
C
L
= 12 pF, see Figure 44
Interrupt Flag Recovery Time, t
DIGREC
60
85
µs typ
C
L
= 12 pF, see Figure 45
600 ns typ CL = 12 pF, RPULLUP = 1 kΩ, see Figure 46
Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
Total Harmonic Distortion Plus Noise, THD + N 0.007 % typ RL = 10 kΩ, VS = 6 V p-p,
f = 20 Hz to 20 kHz, see Figure 41
−3 dB Bandwidth 284 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 40
Insertion Loss
–0.9
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 40
CD (On), CS (On) 25 pF typ VS = 6 V, f = 1 MHz
POWER REQUIREMENTS
V
DD
= +13.2 V, V
SS
= 0 V,
digital inputs = 0 V, 5 V, or VDD
Normal Mode
IDD 0.9 mA typ
IPOSFV 0.1 mA typ
IDD + IPOSFV 1.2 1.3 mA max
I
GND
0.4
mA typ
0.55 0.6 mA max
ISS 0.5 mA typ
INEGFV 0.1 mA typ
ISS + INEGFV 0.65 0.7 mA max
Fault Mode VS = ±55 V
IDD 1.2 mA typ
IPOSFV 0.1 mA typ
IDD + IPOSFV 1.6 1.8 mA max
IGND 0.8 mA typ
1.0 1.1 mA max
ISS 0.5 mA typ Digital inputs = 5 V
INEGFV 0.1 mA typ
ISS + INEGFV 1.0 1.8 mA max VS = ±55 V, VD = 0 V
VDD 8 V min GND = 0 V
44 V max GND = 0 V
1 Guaranteed by design; not subject to production test.
Data Sheet ADG5462F
Rev. C | Page 9 of 29
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, G N D = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 4.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH VDD = +32.4 V, VSS = 0 V, see Figure 35
Analog Signal Range 0 V to VDD V
On Resistance, RON 22 Ω typ VS = 0 V to +30 V, IS = −10 mA
24.5
31
37
Ω max
10 Ω typ VS = +4.5 V to +28 V, IS = −10 mA
11 14 16.5 Ω max
On-Resistance Match Between Channels, ∆RON 0.05 Ω typ VS = 0 V to +30 V, IS = −10 mA
0.5 0.6 0.7 Ω max
0.05 Ω typ VS = +4.5 V to +28 V, IS = −10 mA
0.35 0.5 0.5 Ω max
On-Resistance Flatness, RFLAT(O N) 12.5 Ω typ VS = 0 V to +30 V, IS = −10 mA
14.5 19 23 Ω max
0.1 Ω typ VS = +4.5 V to +28 V, IS = −10 mA
0.4 0.5 0.5 Ω max
Threshold Voltage, VT 0.7 V typ See Figure 23
LEAKAGE CURRENTS VDD = +39.6 V, VSS = 0 V
Channel On Leakage, ID (On), IS (On) ±0.3 nA typ VS = VD = 1 V/30 V, see Figure 36
±1.5
±2.0
±4.5
nA max
FAULT
Source Leakage Current, I
S
With Overvoltage
±78
µA typ
V
DD
= +39.6 V, V
SS
= 0 V, GND = 0 V,
VS = −40 V to +55 V, see Figure 37
Power Supplies Grounded or Floating ±40 µA typ VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, VS = +55 V, −40 V,
see Figure 38
Drain Leakage Current, ID DR = floating or VDD
With Overvoltage ±2.0 nA typ VDD = +39.6 V, VSS = 0 V, GND = 0 V,
VS = −40 V to +55 V, see Figure 37
±20 ±30 ±65 nA max
Power Supplies Grounded ±10 nA typ VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = −40 V to +55 V, see Figure 38
±30 ±50 ±100 nA max
Power Supplies Floating ±10 ±10 ±10 µA typ VDD = floating, VSS = floating, GND = 0 V,
VS = −40 V to +55 V, see Figure 38
DIGITAL INPUTS/OUTPUTS
Input Voltage High, VINH 2.0 V min
Input Voltage Low, VINL 0.8 V max
Input Current, IINL or IINH 0.7 µA typ VIN = VGND or VDD
1.2 µA max
Digital Input Capacitance, CIN 5.0 pF typ
Output Voltage High, VOH 2.0 V min
Output Voltage Low, VOL 0.8 V max
ADG5462F Data Sheet
Rev. C | Page 10 of 29
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
DYNAMIC CHARACTERISTICS1
Overvoltage Response Time, tRESPONSE 250 ns typ RL = 1 kΩ, CL = 2 pF, see Figure 42
350 360 375 ns max
Overvoltage Recovery Time, tRECOVERY 1500 ns typ RL = 1 kΩ, CL = 2 pF, see Figure 43
2000 2300 2700 ns max
Drain Pull-Up/Pull-Down Time Following
Overvoltage, tRESPONSE (DR)
4 µs typ CL = 12 pF, see Figure 47
Interrupt Flag Response Time, t
DIGRESP
85
115
ns typ
C
L
= 12 pF, see Figure 44
Interrupt Flag Recovery Time, t
DIGREC
60
85
µs typ
C
L
= 12 pF, see Figure 45
600 ns typ CL = 12 pF, RPULLUP = 1 kΩ, see Figure 46
Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
Total Harmonic Distortion Plus Noise, THD + N 0.001 % typ RL = 10 kΩ, VS = 18 V p-p,
f = 20 Hz to 20 kHz, see Figure 41
−3 dB Bandwidth 321 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 40
Insertion Loss
–0.8
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 40
CD (On), CS (On) 23 pF typ VS = 18 V, f = 1 MHz
POWER REQUIREMENTS
V
DD
= 39.6 V, V
SS
= 0 V,
digital inputs = 0 V, 5 V, or VDD
Normal Mode
IDD 0.9 mA typ
IPOSFV 0.1 mA typ
IDD + IPOSFV 1.2 1.3 mA max
I
GND
0.4
mA typ
0.55 0.6 mA max
ISS 0.5 mA typ
INEGFV 0.1 mA typ
ISS + INEGFV 0.65 0.7 mA max
Fault Mode VS = −40 V to +55 V
IDD 1.2 mA typ
IPOSFV 0.1 mA typ
IDD + IPOSFV 1.6 1.8 mA max
IGND 0.8 mA typ
1.0 1.1 mA max
ISS 0.5 mA typ
INEGFV 0.1 mA typ
ISS + INEGFV 1.0 1.8 mA max
VDD 8 V min GND = 0 V
44 V max GND = 0 V
1 Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter 25°C 85°C 125°C Unit Test Conditions/Comments
16-Lead TSSOP
θJA = 112.6°C/W 83 59 39 mA max VS = VSS + 4.5 V to VDD − 4.5 V
64 48 29 mA max VS = VSS to VDD
16-Lead LFCSP
θJA = 30.4°C/W 152 99 61 mA max VS = VSS + 4.5 V to VDD − 4.5 V
118 81 53 mA max VS = VSS to VDD
Data Sheet ADG5462F
Rev. C | Page 11 of 29
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND −48 V to +0.3 V
POSFV to GND −0.3 V to VDD + 0.3 V
NEGFV to GND VSS − 0.3V to +0.3 V
Sx Pins to GND −55 V to +55 V
Sx to V
DD
or V
SS
80 V
VS to VD 80 V
Dx Pins1, 2 to GND NEGFV − 0.7 V to POSFV +
0.7 V or 30 mA, whichever
occurs first
Digital Input (DR pin) to GND GND − 0.7 V to 48 V or 30 mA,
whichever occurs first
Peak Current, Sx or Dx Pins 288 mA (pulsed at 1 ms,
10% duty cycle maximum)
Continuous Current, Sx or Dx Pins Data3 + 15%
Digital Output (FF pin) GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
Dx Pins, Overvoltage State,
DR = GND, Load Current
1 mA
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Thermal Impedance, θ
JA
16-Lead TSSOP (4-Layer Board) 112.6°C/W
16-Lead LFCSP (4-Layer Board) 30.4°C/W
Reflow Soldering Peak
Temperature, Pb-Free
As per JEDEC J-STD-020
ESD (HBM: ESDA/JEDEC JS-001-2011)
Input/Output Port to Supplies 4 kV
Input/Output Port to
Input/Output Port
4 kV
All Other Pins 4 kV
1 Overvoltages at the Dx pins are clamped by internal diodes. Limit current to
the maximum ratings given.
2 POSFV and NEGFV must not exceed VDD and VSS, respectively.
3 See Table 5.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
ADG5462F Data Sheet
Rev. C | Page 12 of 29
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
NOTES
1. NI C = NOT INTE RNALLY CO NNE CTED.
16
15
14
13
12
11
10
9
D1
S1
V
SS
D4
S4
GND
NEGFV
D2
S2
V
DD
D3
DR NIC
S3
FF
POSFV
ADG5462F
TOP VIEW
(No t t o Scale)
12698-002
Figure 2. TSSOP Pin Configuration
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
NOTES
1.NIC= NOT INTERNALLY CONNECTED. DO NOT
CONNECT TO THIS PIN.
2. THE EX P OSED P AD IS CONNE CTED I NTERNAL LY.
FOR INCREASED RELIABILITY OF THE SOLDER
JOI NTS AND MAX IMUM THERMAL CAPABILITY,
IT IS RE COMME NDE D THAT THE PAD BE S OLDE RE D
TO THE LOWEST SUPPLY VOLTAGE, V
SS
.
S1
V
SS
GND
S4
S2
D2
POSFV
NEGFV
D1
V
DD
FF
S3
D4
DR
NIC
D3
ADG5462F
TOP VIEW
(No t t o Scale)
12698-103
Figure 3. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 15 NEGFV Negative Fault Voltage. This pin provides the negative supply voltage that determines the overvoltage
protection level. If a secondary supply is not used, connect this pin to VSS.
2 16 D1 Drain Terminal 1. This pin can be an input or an output.
3 1 S1 Overvoltage Protected Source Terminal 1. This pin can be an input or an output.
4 2 VSS Most Negative Power Supply Potential.
5 3 GND Ground (0 V) Reference.
6 4 S4 Overvoltage Protected Source Terminal 4. This pin can be an input or an output.
7 5 D4 Drain Terminal 4. This pin can be an input or an output.
8 6 DR Drain Response Digital Input. Tying this pin to GND enables the drain to pull to POSFV or NEGFV during an
overvoltage fault condition. The default condition of the drain is open-circuit when the pin is left
floating or if it is tied to VDD.
9 7 NIC Not Internally Connected.
10 8 D3 Drain Terminal 3. This pin can be an input or an output.
11 9 S3 Overvoltage Protected Source Terminal 3. This pin can be an input or an output.
12 10 FF Fault Flag Digital Output. This pin has a high output (nominally 3 V) when the device is in normal
operation or a low output when a fault condition occurs on any of the Sx inputs. The FF pin has a weak
internal pull-up that allows the signals to be combined into a single interrupt for larger modules that
contain multiple devices.
13 11 VDD Most Positive Power Supply Potential.
14
12
S2
Overvoltage Protected Source Terminal 2. This pin can be an input or an output.
15 13 D2 Drain Terminal 2. This pin can be an input or an output.
16 14 POSFV Positive Fault Voltage. This pin provides the positive supply voltage that determines the overvoltage
protection level. If a secondary supply is not used, connect this pin to VDD.
EP Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be soldered to the lowest supply voltage, VSS.
Data Sheet ADG5462F
Rev. C | Page 13 of 29
TYPICAL PERFORMANCE CHARACTERISTICS
25
20
15
10
5
0
–25 –20 –15 –10 –5 0 5 10 15 20 25
ON RESISTANCE (Ω)
V
S
, V
D
(V)
T
A
= 25° C
V
DD
= +22V
V
SS
= –22V
V
DD
= +20V
V
SS
= –20V
V
DD
= +18V
V
SS
= –18V
V
DD
= +16. 5V
V
SS
= –16.5V
V
DD
= +15V
V
SS
= –15V
V
DD
= +13. 5V
V
SS
= –13.5V
12698-003
Figure 4. On Resistance (RON) as a Function of VS, VD (Dual Supply)
25
20
15
10
5
001412108642
ON RESISTANCE (Ω)
V
S
, V
D
(V)
T
A
= 25° C
V
DD
= 10.8V
V
SS
= 0V
V
DD
= 12V
V
SS
= 0V
V
DD
= 13.2V
V
SS
= 0V
12698-004
Figure 5. On Resistance (RON) as a Function of VS, VD (12 V Single Supply)
25
20
15
10
5
00403530252015105
ON RESISTANCE (Ω)
V
S
, V
D
(V)
T
A
= 25° C
V
DD
= 36V
V
SS
= 0V
V
DD
= 32.4V
V
SS
= 0V
V
DD
= 39.6V
V
SS
= 0V
12698-005
Figure 6. On Resistance (RON) as a Function of VS, VD (36 V Single Supply)
40
30
20
35
25
15
10
5
0
–15 –12 –9 –6 –3 0 3 6 9 12 15
ON RESISTANCE (Ω)
V
S
, V
D
(V)
V
DD
= +15V
V
SS
= –15V
+125°C
+85°C
+25°C
–40°C
12698-006
Figure 7. On Resistance (RON) as a Function of VS,VD for Different
Temperatures, ±15 V Dual Supply
40
30
20
35
25
15
10
5
0
–20 –15 –10 –5 0 5 10 15 20
ON RESISTANCE (Ω)
V
S
, V
D
(V)
V
DD
= +20V
V
SS
= –20V
+125°C
+85°C
+25°C
–40°C
12698-007
Figure 8. On Resistance (RON) as a Function of VS, VD for Different
Temperatures, ±20 V Dual Supply
40
30
20
35
25
15
10
5
00246810 12
ON RESISTANCE (Ω)
V
S
, V
D
(V)
V
DD
= 12V
V
SS
= 0V
+125°C
+85°C
+25°C
–40°C
12698-008
Figure 9. On Resistance (RON) as a Function of VS, VD for Different
Temperatures, 12 V Single Supply
ADG5462F Data Sheet
Rev. C | Page 14 of 29
40
30
20
35
25
15
10
5
004 8 12 20 28 3616 24 32
ON RESISTANCE (Ω)
V
S
, V
D
(V)
V
DD
= 36V
V
SS
= 0V
+125°C
+85°C
+25°C
–40°C
12698-009
Figure 10. On Resistance (RON) as a Function of VS, VD for Different
Temperatures, 36 V Single Supply
2
–8
–7
–6
–5
–4
–3
–2
–1
0
1
012010080604020
LE AKAG E CURRE NT (n A)
TEMPERATURE (°C)
V
DD
= +15V
V
SS
= –15V
V
S
= V
D
= +10V/–10V
I
S
, I
D
(ON) + + I
S
, I
D
(O N) – –
12698-010
Figure 11. Leakage Current vs. Temperature, ±15 V Dual Supply
2
–10
–8
–6
–4
–2
0
012010080604020
LE AKAG E CURRE NT (n A)
TEMPERATURE (°C)
V
DD
= +20V
V
SS
= –20V
V
S
= V
D
= +15V/–15V
I
S
, I
D
(ON) + + I
S
, I
D
(O N) – –
12698-011
Figure 12. Leakage Current vs. Temperature, ±20 V Dual Supply
1
–5
–4
–3
–2
–1
0
0120100
80
604020
LE AKAG E CURRE NT (n A)
TEMPERATURE (°C)
V
DD
= 12V
V
SS
= 0V
V
S
= V
D
= 1V/ 10V
I
S
, I
D
(ON) + + I
S
, I
D
(O N) – –
12698-012
Figure 13. Leakage Current vs. Temperature, 12 V Single Supply
2
–10
–8
–6
–4
–2
0
0120
100
80
6040
20
LE AKAG E CURRE NT (n A)
TEMPERATURE (°C)
V
DD
= 36V
V
SS
= 0V
V
S
= V
D
= 1V/ 30V
I
S
, I
D
(ON) + + I
S
, I
D
(ON) – –
12698-013
Figure 14. Leakage Current vs. Temperature, 36 V Single Supply
5
–20
–15
–10
–5
0
012010080604020
DRAIN OVERVOLTAGE LEAKAGE CURRE NT (n A)
TEMPERATURE (°C)
VDD = + 15V
VSS = –15V
VS = –30V
VS = +30V
VS = –55V
VS = +55V
12698-014
Figure 15. Drain Overvoltage Leakage Current vs. Temperature,
±15 V Dual Supply
Data Sheet ADG5462F
Rev. C | Page 15 of 29
5
–25
–20
–15
–10
–5
0
012010080604020
DRAIN O V E RV OLTAGE LEAKAGE CURRE NT (n A)
TEMPERATURE (°C)
V
DD
= +20V
V
SS
= –20V
V
S
= –30V
V
S
= +30V
V
S
= –55V
V
S
= +55V
12698-015
Figure 16. Drain Overvoltage Leakage Current vs. Temperature,
±20 V Dual Supply
2
–16
–14
–12
–10
–8
–6
–4
–2
0
0120
100
80
6040
20
DRAIN O V E RV OLTAGE LEAKAGE CURRE NT (n A)
TEMPERATURE (°C)
V
DD
= 12V
V
SS
= 0V
V
S
= –30V
V
S
= +30V
V
S
= –55V
V
S
= +55V
12698-016
Figure 17. Drain Overvoltage Leakage Current vs. Temperature,
12 V Single Supply
2
–14
–12
–10
–8
–6
–4
–2
0
012010080604020
OVE RV OLTAGE LEAKAG E CURRE NT (n A)
TEMPERATURE (°C)
V
DD
= 36V
V
SS
= 0V
V
S
= –38V
V
S
= +38V
V
S
= –40V
V
S
= +55V
12698-017
Figure 18. Overvoltage Leakage Current vs. Temperature, 36 V Single Supply
0
–100
–90
–80
–60
–70
–50
–40
–30
–20
–10
10k 1G100M10M1M100k
CROS S TALK (dB)
FREQUENCY ( Hz )
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
12698-018
Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply
0
–120
–100
–80
–60
–40
–20
10k 1G100M10M1M100k
ACPSRR ( dB)
FREQUENCY ( Hz )
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
12698-019
Figure 20. AC Power Supply Rejection Ratio (ACPSRR) vs. Frequency,
±15 V Dual Supply
0.020
0
0.005
0.010
0.015
02000015000100005000
THD + N ( %)
FREQUENCY ( Hz )
LOAD = 10kΩ
T
A
= 25° C
V
DD
= 12V, V
SS
= 0V, V
S
= 6V p-p
V
DD
= 36V, V
SS
= 0V, V
S
= 18V p - p
V
DD
= 15V, V
SS
= –15V, V
S
= 15V p - p
V
DD
= 20V, V
SS
= –20V, V
S
= 20V p - p
12698-020
Figure 21. THD + N vs. Frequency, ±15 V Dual Supply
ADG5462F Data Sheet
Rev. C | Page 16 of 29
0
–5.0
–4.5
–4.0
–3.0
–3.5
–2.5
–2.0
–1.5
–1.0
–0.5
10k 1G100M10M1M
100k
BANDWIDTH (dB)
FREQUENCY ( Hz )
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
12698-021
Figure 22. Bandwidth vs. Frequency
0.9
0.8
0.7
0.6
0.5 0120
100
80
60
4020
–20–40
THRESHOLD VOLTAGE, V
T
(V)
TEMPERATURE (°C)
12698-022
Figure 23. Threshold Voltage (VT) vs. Temperature
24
20
16
12
8
4
010010
1
SIGNAL VOLTAGE (V p-p)
FREQUENCY (MHz)
DISTORTIONLESS
OPERATING
REGION
T
A
= 25° C
V
DD
= +10V
V
SS
= –10V
12698-023
Figure 24. Large Voltage Signal Tracking vs. Frequency
CH1 5.00V CH2 5.00V
CH3 5.00V CH4 5.00V M2.00µs A CH1 11.0V
4
T
POSFV
SOURCE
VDD
DRAIN
12698-024
Figure 25. Drain Output Response to Positive Overvoltage
(DR = Floating or High)
CH1 5.00V CH2 5.00V
CH3 5.00V CH4 5.00V M2.00µs A CH1 11.0V
4
T
POSFV
SOURCE
VDD
DRAIN
12698-025
Figure 26. Drain Output Recovery from Positive Overvoltage
(DR = Floating or High)
CH1 5.00V CH2 5.00V
CH3 5.00V CH4 5.00V M2.00µs A CH1 11. 7V
4
T
POSFV
SOURCE
VDD
DRAIN
12698-026
Figure 27. Drain Output Response to Positive Overvoltage (DR = GND)
Data Sheet ADG5462F
Rev. C | Page 17 of 29
CH1 5.00V CH2 5.00V
CH3 5.00V CH4 5.00V M2.00µs A CH1 16.0V
4
T
POSFV
SOURCE
VDD
DRAIN
12698-027
Figure 28. Drain Output Recovery from Positive Overvoltage (DR = GND)
CH1 5.00V CH2 5.00V
CH3 5.00V CH4 5.00V M2.00µs A CH1 –10.4V
4
T
NEGFV
SOURCE
VSS
DRAIN
12698-028
Figure 29. Drain Output Response to Negative Overvoltage
(DR = Floating or High)
CH1 5.00V CH2 5.00V
CH3 5.00V CH4 5.00V M2.00µs A CH1 –10.4V
4
T
NEGFV
SOURCE
VSS
DRAIN
12698-029
Figure 30. Drain Output Recovery from Negative Overvoltage
(DR = Floating or High)
CH1 5.00V CH2 5.00V
CH3 5.00V CH4 5.00V M2.00µs A CH1 –10.4V
4
T
NEGFV
SOURCE
VSS
DRAIN
12698-030
Figure 31. Drain Output Response to Negative Overvoltage (DR = GND)
CH1 5.00V CH2 5.00V
CH3 5.00V CH4 5.00V M2.00µs A CH1 –10. 4V
4
T
NEGFV
SOURCE
VSS
DRAIN
12698-031
Figure 32. Drain Output Recovery from Negative Overvoltage (DR = GND)
CH1 5.00V CH2 5.00V
CH3 2.00V CH4 5.00V M1.00µs A CH3 1.12V
2
T
VDD = PO SF V
SOURCE
DRAIN
DR INP UT
12698-032
Figure 33. Drain Output Response to Positive Overvoltage (DR = High to Low)
ADG5462F Data Sheet
Rev. C | Page 18 of 29
CH1 5.00V CH2 5.00V
CH3 2.00V CH4 5.00V M1.00µs A CH3 1.12V
2
3
T
VSS = NEGFV SOURCE
DRAIN
DR INPUT
12698-033
Figure 34. Drain Output Response to Negative Overvoltage
(DR = High to Low)
Data Sheet ADG5462F
Rev. C | Page 19 of 29
TEST CIRCUITS
I
DS
Sx Dx
V
S
V
R
ON
= V/I
DS
12698-034
Figure 35. On Resistance
Sx Dx A
V
D
I
D
(ON)
NC
NC = NO CONNECT
12698-035
Figure 36. On Leakage
|V
S
| > |POSF V| O R |NEGF V|
DR = FLOATING OR V
DD
Sx Dx
A A
I
S
I
D
R
L
10kΩ
12698-037
Figure 37. Switch Overvoltage Leakage
ISID
RL
10kΩ
VS
VDD = VSS = PO SF V = NEGF V = G ND = 0V
Sx Dx
AA
12698-038
Figure 38. Switch Unpowered Leakage
CHANNEL- TO- CHANNE L CROS S TALK = 20 log V
OUT
GND
S1
D2 S2
NETWORK
ANALYZER
R
L
50Ω
R
L
50Ω
V
S
V
DD
V
SS
0.1µFV
DD
0.1µF
V
SS
V
S
V
OUT
12698-036
Figure 39. Channel-to-Channel Crosstalk
VOUT
50Ω
NETWORK
ANALYZER
RL
50Ω
Sx
Dx
INSERTION LOSS = 20 log VOUT WITH SWITCH
VOUT WITHOUT SWITCH
VS
VDD VSS
0.1µFVDD 0.1µF
VSS
GND
12698-039
Figure 40. Bandwidth
ADG5462F Data Sheet
Rev. C | Page 20 of 29
V
OUT
R
S
AUDIO
PRECISION
R
L
10kΩ
Sx
Dx
V
S
V p-p
V
DD
V
SS
0.1µFV
DD
0.1µF
V
SS
GND
12698-040
Figure 41. THD + N
V
D
ADG5462F
GND
S1
S2 TO S4
D1 C
L
*
2pF
V
S
POSFV + 0.5V
POSFV × 0.9
0V
0V
OUTPUT
(V
D
)
tRESPONSE
SOURCE
VOLTAGE
(V
S
)
R
L
1kΩ
*INCLUDES T RACK CAP ACITANCE
0.1µF
0.1µF V
DD
V
SS
V
DD
V
SS
0.1µF
0.1µF
POSFV NEGFV
POSFV
NEGFV
12698-041
Figure 42. Overvoltage Response Time, tRESPONSE
VD
ADG5462F
GND
S1
S2 TO S4
D1 CL*
2pF
VSRL
1kΩ
*INCLUDES T RACK CAP ACITANCE
0.1µF0.1µF VDD VSS
VDD VSS
0.1µF0.1µF
POSFV NEGFV
POSFV
NEGFV
POSFV + 0.5V
POSFV × 0.1
0V
0V
OUTPUT
(VD)
tRECOVERY
SOURCE
VOLTAGE
(VS)
12698-042
Figure 43. Overvoltage Recovery Time, tRECOVERY
Data Sheet ADG5462F
Rev. C | Page 21 of 29
V
DD
V
SS
V
DD
V
SS
OUTPUT
ADG5462F
GND
S1
FF
S2 TO S4
D1
C
L
*
12pF
V
S
POSFV + 0.5V
0V
0V
OUTPUT
(V
FF
)
tDIGRESP
0.1V
OUT
SOURCE
VOLTAGE
(V
S
)
*INCLUDES T RACK CAP ACITANCE
0.1µF
0.1µF
0.1µF0.1µF
POSFV NEGFV
POSFV
NEGFV
12698-043
Figure 44. Interrupt Flag Response Time, tDIGRESP
V
DD
V
SS
V
DD
V
SS
OUTPUT
ADG5462F
GND
S1
FF
S2 TO S4
D
C
L
*
V
S
POSFV + 0.5V
0V
0V
OUTPUT
(V
FF
)
t
DIGREC
0.9V
OUT
SOURCE
VOLTAGE
(V
S
)
12pF
*INCLUDES T RACK CAP ACITANCE
0.1µF0.1µF
0.1µF0.1µF
POSFV NEGFV
POSFV
NEGFV
12698-044
Figure 45. Interrupt Flag Recovery Time, tDIGREC
OUTPUT
ADG5462F
GND
S1
FF
S2 TO S4
D1
C
L
*
V
S
POSFV + 0.5V
0V
5V
0V
OUTPUT
(V
FF
)
tDIGREC
3V
SOURCE
VOLTAGE
(V
S
)
12pF
R
PULLUP
1kΩ
*INCLUDES T RACK CAP ACITANCE
5V
0.1µF0.1µF
0.1µF0.1µF
POSFV NEGFV
POSFV
NEGFV
V
DD
V
SS
V
DD
V
SS
12698-045
Figure 46. Interrupt Flag Recovery Time, tDIGREC, with a 1 kΩ Pull-Up Resistor
ADG5462F Data Sheet
Rev. C | Page 22 of 29
V
DD
V
SS
V
DD
V
SS
OUTPUT
ADG5462F
GND
S1
S2 TO S4
D
C
L
*
V
S
> POSFV + V
T
50%
0V
3V
0V
OUTPUT
(V
D
)
t
RESPONSE
(DR)
POSFV × 0.9
INPUT
VOLTAGE
(V
DR
)
DR
12pF
*INCL UDE S TRACK CAPACI TANCE
0.1µF0.1µF
0.1µF0.1µF
POSFV NEGFV
POSFV
NEGFV
12698-046
Figure 47. Drain Enable Time with Overvoltage, tRESPONSE (DR)
Data Sheet ADG5462F
Rev. C | Page 23 of 29
TERMINOLOGY
IDD
IDD represents the positive primary supply current.
ISS
ISS represents the negative primary supply current.
IPOSFV
IPOSFV represents the positive secondary supply current.
INEGFV
INEGFV represents the negative secondary supply current.
VD, VS
VD and VS represent the analog voltage on the Dx pins and the
Sx pins, respectively.
RON
RON represents the ohmic resistance between the Dx pins and
the Sx pins.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT(ON)
RFLAT(ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured
over the specified analog signal range.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (On), CS (On)
CD (On) and CS (On) represent the on switch capacitances,
which are measured with reference to ground.
CIN
CIN is the digital input capacitance.
tDIGRESP
tDIGRESP is the time required for the FF pin to go low (0.3 V),
measured with respect to voltage on the source pin exceeding
the supply voltage by 0.5 V.
tDIGREC
tDIGREC is the time required for the FF pin to return high, measured
with respect to voltage on the Sx pin falling below the supply
voltage plus 0.5 V.
tRESPONSE
tRESPONSE represents the delay between the source voltage
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 90% of the supply voltage.
tRECOVERY
tRECOVERY represents the delay between an overvoltage on the Sx
pin falling below the supply voltage plus 0.5 V and the drain
voltage rising from 0 V to 10% of the supply voltage.
tRESPONSE (DR)
tRESPONSE (DR) represents the delay between the voltage at the DR
pin falling from a high to low signal and the output of the drain
pin reaching 90% of either POSFV or NEGFV
Channel-to-Channel Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. ACPSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pin to the output of the switch.
The dc voltage on the device is modulated by a sine wave of
0.62 V p-p.
VT
VT is the voltage threshold at which the overvoltage protection
circuitry engages. See Figure 23
ADG5462F Data Sheet
Rev. C | Page 24 of 29
THEORY OF OPERATION
SWITCH ARCHITECTURE
Each channel of the ADG5462F consists of a parallel pair of
NDMOS and PDMOS transistors. This construction provides
excellent performance across the signal range. The ADG5462F
channels present only as a typical impedance of 10 Ω when input
signals with a voltage between POSFV and NEGFV are applied.
Additional internal circuitry enables the switch to detect
overvoltage inputs by comparing the voltage on the source
pin (Sx) with POSFV and NEGFV. A signal is considered
overvoltage if it exceeds the secondary supply voltages by the
voltage threshold (VT). The threshold voltage is typically 0.7 V,
but it ranges from 0.8 V at −40°C down to 0.6 V at +125°C. See
Figure 23 to see the change in VT with operating temperature.
The maximum voltage that can be applied to any source input
is −55 V or +55 V. When the device is powered using a single
supply of 25 V or greater, the maximum negative signal level is
reduced. It reduces from −55 V at VDD = +25 V to −40 V at VDD =
+40 V to remain within the 80 V maximum rating. Construction of
the silicon process allows the channel to withstand 80 V across
the switch when it is opened. These overvoltage limits apply
whether the power supplies are present or not.
LOGIC
BLOCK
ESD
PROTECTION
Sx Dx
DR
POSFV
NEGFV
ESD
ESD
FAULT
DETECTOR SWITCH
DRIVER
12698-047
Figure 48. Switch Channel and Control Function
When an overvoltage condition is detected on a source pin (Sx),
the switch automatically opens and the source pin (Sx) becomes
high impedance and ensures that no current flows through the
switch. If the DR pin is driven low, the drain pin (Dx) is pulled
to the supply that was exceeded. For example, if the source voltage
exceeds POSFV, the drain output pulls to POSFV. The same is
true for NEGFV. In Figure 27, the voltage on the drain pin (Dx)
clamps to the POSFV voltage when the source voltage exceeds
POSFV by VT. If the DR pin is allowed to float or is driven high,
the drain pin (Dx) also goes open circuit. In Figure 25, the voltage
on the drain pin (Dx) follows the voltage on the source pin
(Sx) until the switch turns off completely and the drain voltage
discharges through the load. The output response for each drain
pin configuration is shown in Figure 49. The maximum voltage
on the drain is limited by the internal ESD diodes and the rate
at which the output voltage discharges is dependent on the load at
the pin.
VIN
VOUT
VOUT
VPOSFV + VT
VPOSFV + VTVPOSFV + VT
OUTPUT
CLAMPED
AT VPOSFV
OUTPUT SHOWN FOR
DR = GND
OUTPUT
DRAINS
THROUGH
LOAD
OUTPUT SHOWN FOR
DR = FLOATING/HIGH
12698-148
Figure 49. Drain Output Response During Overvoltage Condition
During overvoltage conditions, the leakage current into and out
of the source pins (Sx) is limited to tens of microamperes. If the
DR pin is allowed to float or is driven high, only nanoamperes
of leakage are seen on the drain pins (Dx). If the DR pin is driven
low, the drain pin (Dx) is pulled to the rail. The device that pulls
the drain pin to the rail has an impedance of approximately 40 kΩ;
therefore, the Dx pin current is limited to about 1 mA during a
shorted load condition. This internal impedance also determines
the minimum external load resistance required to ensure that
the drain pin is pulled to the desired voltage level during a fault.
When an overvoltage event occurs, the channels undisturbed by
the overvoltage input continue to operate normally without
additional crosstalk.
ESD Performance
The ADG5462F has an ESD rating of 4 kV for the human body
model.
The drain pins (Dx) have ESD protection diodes to the secondary
supply rails, and the voltage at these pins must not exceed the
secondary supply voltage.
The source pins (Sx) have specialized ESD protection that allows
the signal voltage to reach ±55 V with a ±22 V dual supply, and
from −40 V to +55 V with a +40 V single supply. See Figure 48
for the switch channel overview. Exceeding ±55 V on any source
input may damage the ESD protection circuitry on the device.
Data Sheet ADG5462F
Rev. C | Page 25 of 29
Trench Isolation
In the ADG5462F, an insulating oxide layer (trench) is placed
between the NDMOS and the PDMOS transistors of each channel.
Parasitic junctions, which occur between the transistors in junction
isolated switches, are eliminated, and the result is a switch that
is latch-up immune under all circumstances. This device passes
a JESD78D latch-up test of ±500 mA for 1 sec, which is the
harshest test in the specification.
NDMOS PDMOS
P-WELL N-WELL
BURIED OXI DE LAYER
HANDLE WAFE R
TRENCH
12698-048
Figure 50. Trench Isolation
USER DEFINED FAULT PROTECTION
POSFV and NEGFV are required secondary power supplies
that set the level at which the overvoltage protection is engaged.
POSFV can be supplied from 4.5 V up to VDD, and NEGFV can
be supplied from VSS to 0 V. If a secondary supply is not available,
these pins (POSFV and NEGFV) must be connected to VDD
(POSFV) and VSS (NEGFV). The overvoltage protection then
engages at the primary supply voltages. When the voltages at
the source inputs exceed POSFV or NEGFV by VT, the channel
turns off or, if the device is unpowered, the channel remains off.
The source input remains high impedance, and if the DR pin is
driven low, the drain pulls to either POSFV or NEGFV. Signal
levels up to −55 V and +55 V are blocked in both the powered
and unpowered condition as long as the 80 V limitation between
the source and supply pins is met.
Power-On Protection
For the channel to be in the on condition, the following three
conditions must be satisfied:
• The primary supply must be VDD to VSS ≥ 8 V.
• For POSFV, the secondary supply must be between 4.5 V
and VDD, and for NEGFV, the secondary supply must be
between VSS and 0 V.
• The input signal must be between NEGFV − VT and
POSFV + VT.
When the channel is on, signal levels up to the secondary
supply rails are passed.
The channel responds to an analog input that exceeds POSFV
or NEGFV by a threshold voltage (VT) by turning off. The absolute
input voltage limits are −55 V and +55 V, while maintaining an
80 V limit between the source pin (Sx) and the supply rails. The
switch remains off until the voltage at the source pin (Sx) returns to
between POSFV and NEGFV.
The fault response time (tRESPONSE) when powered by a ±15 V dual
supply is typically 460 ns, and the fault recovery time (tRECOVERY) is
720 ns. These values vary with supply voltage and output load
conditions.
The maximum stress across the channel and between the source
pin (Sx) and any supply pin is 80 V; therefore, pay close attention
to this limit if using the device in a single-supply configuration and
a negative overvoltage is applied to the device.
For example, consider the case where the device is set up in a
single supply configuration, as shown in Figure 51.
• VDD = POSFV = 36 V, VSS = NEGFV = GND = 0 V
• S1 = +36 V, S2 = +5 V, and S3 = −40 V
• The voltage difference from S1 to VDD/POSFV = 0 V, and to
VSS/NEGFV = 36 V
• The voltage difference from S2 to VDD/POSFV = 31 V, and
to VSS/NEGFV = 5 V
• The voltage difference from S3 to VDD/POSFV = 76 V, and
to VSS/NEGFV = 40 V
These calculations are all within device specifications: 55 V
maximum fault on source inputs and a maximum of 80 V
across the channel or to a supply pin. The voltage on a source
pin (Sx) cannot go below −44 V to stay within +80 V maximum.
ADG5262F
GND
0V+36V
V
DD
POSFV
V
SS
NEGFV
D1
D2
D3
D4
S1
S2
S3
S4
+36V
+5V
–40V
FAULT
DETECTION
+ SWITCH
DRIVER
12698-049
Figure 51. ADG5462F in Single-Supply Configuration Under Overvoltage
Conditions
ADG5462F Data Sheet
Rev. C | Page 26 of 29
Power-Off Protection
When no power supplies are present, the channel remains in the
off condition, and the switch inputs are high impedance. This
state ensures that no current flows and prevents damage to the
switch or downstream circuitry. The switch output is a virtual
open circuit.
The switch remains off regardless of whether the primary and
secondary supplies are 0 V or floating. A GND reference must
always be present to ensure proper operation. Signal levels of up
to ±55 V are blocked in the unpowered condition.
Digital Input Protection
The ADG5462F can tolerate digital input signals being present
on the device without power. The digital input is protected against
positive faults up to 44 V. The digital input does not offer protection
against negative overvoltages. ESD protection diodes connected
to GND are present on the digital input.
Overvoltage Interrupt Flag
The voltages on the source inputs of the ADG5462F are
continuously monitored, and an active low digital output pin
(FF) indicates the state of the switches.
The voltage on the FF pin indicates if any of the source input pins
are experiencing a fault condition. The output of the FF pin is a
nominal 3 V when all source pins (Sx) are within normal operating
range. If any source pin (Sx) voltage exceeds the supply voltage
by VT, the FF output reduces to below 0.8 V.
Data Sheet ADG5462F
Rev. C | Page 27 of 29
APPLICATIONS INFORMATION
The overvoltage protected family of switches and multiplexers
provide robust solutions for instrumentation, industrial,
automotive, aerospace, and other harsh environments where
overvoltage signals can be present, and the system must remain
operational both during and after the overvoltage has occurred.
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 µF decoupling
capacitors are required on the primary and secondary supplies.
If they are driven from the same supply, then one set of 0.1 µF
decoupling capacitors is sufficient.
The secondary supplies (POSFV and NEGFV) provide the
current required to operate the fault protection and, therefore,
must be low impedance supplies. Therefore, they can be derived
from the primary supply by using a resistor divider and buffer.
The secondary supply rails (POSFV and NEGFV) must not exceed
the primary supply rails (VDD and VSS) because this can lead to a
signal passing through the switch unintentionally.
The ADG5462F can operate with bipolar supplies between ±5 V
and ±22 V. The supplies on VDD and VSS need not be symmetrical
but the VDD and VSS range must not exceed 44 V. The ADG5462F
can also operate with single supplies between 8 V and 44 V with
VSS connected to GND.
The ADG5462F is fully specified at ±15 V, ±20 V, +12 V, and
+36 V supply ranges.
POWER SUPPLY SEQUENCING PROTECTION
The channels remain open when the device is unpowered and
signals from −55 V to +55 V can be applied without damaging
the device. Only when the supplies are connected, and the signal
is within normal operating range, do the channels close. Placing
the ADG5462F between external connectors and sensitive
components offers protection in systems where a signal is
presented to the source pins (Sx) before the supply voltages
are available.
POWER SUPPLY RECOMMENDATIONS
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
An example of a bipolar power solution is shown in Figure 52.
The ADP7118 and ADP7182 can be used to generate clean
positive and negative rails from the dual switching regulator
output. These rails can power the ADG5462F, an amplifier,
and/or a precision converter in a typical signal chain.
12698-050
+15V
–15V
12V
INPUT ADP7182
LDO
DUAL
SWITCHING
REGULATOR
ADP7118
LDO
+16V
–16V
Figure 52. Bipolar Power Solution
Table 8. Recommended Power Management Devices
Product
Description
ADP7118 20 V, 200 mA, low noise, CMOS low dropout
regulator (LDO)
ADP7142 40 V, 200 mA, low noise, CMOS LDO
ADP7182 −28 V, −200 mA, low noise, linear regulator
USER DEFINED SIGNAL RANGE
The primary supplies define the on-resistance profile of the
channels, while the secondary supplies define the signal range.
Using voltages on POSFV and NEGFV that are lower than VDD
and VSS, the required signal can benefit from the flat on resistance
in the center of the full signal capabilities of the device.
LOW IMPEDANCE CHANNEL PROTECTION
The ADG5462F can be used as a protective element in signal
chains that are sensitive to both channel impedance and
overvoltage signals. Traditionally, series resistors are used to
limit the current during an overvoltage condition to protect
susceptible components.
These series resistors affect the performance of the signal chain
and reduce the precision that can be reached. A compromise
must be reached on the value of the series resistance that is high
enough to sufficiently protect sensitive components but low
enough that the precision performance of the signal chain is not
sacrificed.
The ADG5462F enables the designer to remove these resistors
and retain the precision performance without compromising
the protection of the circuit.
HIGH VOLTAGE SURGE SUPPRESSION
The ADG5462F is not intended for use in very high voltage
applications. The maximum operating voltage of the transistor
is 80 V. In applications where the inputs are likely to be subject
to overvoltages exceeding the breakdown voltage, use transient
voltage suppressors (TVSs) or similar.
ADG5462F Data Sheet
Rev. C | Page 28 of 29
INTELLIGENT FAULT DETECTION
The ADG5462F digital output pin (FF) can interface with a
microprocessor or control system and be used as an interrupt
flag. This feature provides real-time diagnostic information on
the state of the device and the system to which it connects.
The control system can use the digital interrupt to start a
variety of actions, such as
• Initiating investigation into the source of the overvoltage fault
• Shutting down critical systems in response to the overvoltage
• Signaling the data recorders to mark data during these
events as unreliable or out of specification
For systems that are sensitive during a start-up sequence, the
active low operation of the flag allows the system to ensure that
the ADG5462F is powered on and that all input voltages are
within normal operating range before initiating operation.
The FF pin is a weak pull-up, which allows the signals to be
combined into a single interrupt for larger modules that contain
multiple devices.
The interrupt flag recovery time, tDIGREC, can be decreased from
a typical 60 µs to 600 ns by using a 1 kΩ pull-up resistor.
The DR pin can also be used for diagnostic purposes. The FF
pin provides an interrupt that indicates one of the four channels
has a fault. The DR pin can then be pulled low to find which of
the channels has a fault as well as the polarity of the fault. For
example, if an ADC downstream is monitoring the channel, a
full-scale reading then indicates a positive fault, and a zero-scale
reading indicates a negative fault.
LARGE VOLTAGE, HIGH FREQUENCY SIGNALS
Figure 24 illustrates the voltage range and frequencies that the
ADG5462F can reliably convey. For signals that extend across
the full signal range from VSS to VDD, keep the frequency less
than 3 MHz. If the required frequency is greater than 3 MHz,
decrease the signal range appropriately to ensure signal integrity.
Data Sheet ADG5462F
Rev. C | Page 29 of 29
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 53. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
2.70
2.60 SQ
2.50
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGC.
1
0.65
BSC
16
5
8
9
12
13
4
4.10
4.00 SQ
3.90
0.45
0.40
0.35
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.35
0.30
0.25
BOTTOM VIEW
PKG-004828
SEATING
PLANE
TOP VIEW
SIDE VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-22-2017-C
1
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
EXPOSED
PAD
Figure 54. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG5462FBRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5462FBRUZ-RL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5462FBCPZ-RL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-17
EVAL-ADG5426FEBZ Evaluation Board
1 Z = RoHS Compliant Part.
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12698-0-10/17(C)