Marah 1991 Edition 2.0 MB86041A/MB86043 8- 0-BIT QUOTIENT Tha MBGS041A and MBGG043 ara high-speed CMOS plpedined divider fexiuting Inager dition or decimal division operating modes and 10-bet clvkdend, @-bat divipor, ered 10-6 quediant, The ramainder ts cited, Exiemal divide by zara and ovedflow sipnale ene peovicied. The devices operaia al upie 20 Me for high-apeed image algmal processing. The MBB6041 Als howted In.an 40-pin platiin dual in-ting package and MBSGOES heused In 46+pln quad flat package. Functions 5-ahage, pipelined, high-epead divider Operation apaed: 20 MHz (Maximum) = Operation Modes (1) Indeger division (2) Decimal division Gata Forma Dividend : 10bhs (TTL Level) Diver Bhis (TTL Level Quolient 1Obhs (TTL Level (Mote thal the recnaleder Is mitted, ) Detection Function (1) Divide by 0 ered dabection buncion 2) Ovediow ona? dotection luncion ABSOLUTE MAXIMUM RATINGS (See MOTE) [s athige | Spnbat [donations Vole lo +60 Mi, te Vpri5 Vie VWar=0.5 te Vf ho #88 =A ta +125 MWg am Wise, #40 (Maximum) Vow 0 40 (Maximum) HOTE #4) This B ihe outoud conreet par pintog Vee = 5 V and fer a maximum of 7 seca. Permanad device damage may eocur Ht the abewe Abeolule Meocinauna Ratings an exceeded, Functonel aporalion shoukt be restricted to the conditions 25 deladed inthe operaiional sections-of headate chest. Exposcine fo. abeolube maximum pring conditions for extended pediods may elect device naliability, Tera Outpul cunent +1) ke Copa yer ih ny F LATER TED DATA SHEET FUJITSU cmos PIPELINED DIVIDER WITH 10-BIT DIVIDEND, MBS60414 PLASTIC PACKAGE (DIP-40P- 601)T-4S5-213-Q | MBB60414 MBB6043 PIN ASSIGNMENT <MBBGO41 Aa <MBBGO43> (TOP VEW) (TOP WEW} ve ft a0b vee eseaeeeF Fan F ho ge ap co MA hos ab oF 48047 45 45 4d 43 42 41 4 30 38 aT pe ga a7h a2 a t}io 36) ino) mgs 60 O9 oa [2 as] mone tM OoT an os oe de aah on oi 33 |) CVET or oe azb oF oo Ly a2 [1] acy Vee 0 ap 08 Vu [] @ 31 [7] Ve wo 1 aD Vie m [|r 307] ho wo tp oo oi a [0] we He 13 mah (OPEN) we Ot 270 CLK oz Ls aT) wr M4 Die 25 Ge fh 18 #7] MG NE [48 BO MODE Co iW mT] NS MB O17 aap IDV wey Taz 26/7] Na NT 18 20 GFL 13 14 18 16 87 Wo PO Bi Be Ba oe Ne Gia Pn) L Voo O20 210) Ves Pega g I PRE RRE (DIP-40P-Mo1) (FPT-48P- Mog) PIN DESCRIPTIONS TERA ae Syma vO. we A, * Funotien Desoription - Shee otek 1 6 Ves" = Ground pin fo vy 2 7 te i Dikfaor Ingut pin (LSB) 3 8 Di i Divisor input pin 4 9 De i Divisor input pin E 10 ba I Divisar input pin 6 1 tu | Divisor ingiut pin 12, 13 (NG) = No connection ? 14 Ds i Divisor input pln 8 16 De I Civisor input pin a 16 oF Diviser input pin (SB)MBS6041A MBS6043 oe pI MOS ees Beet MbesvatA | MBogoss | Symbol | Wo: _ Funation Destripton .; - WT (NC) = No connection 1d 18 Ve = Ground pin (9 ) e 18 Veo * | - Supply voltage Input pin (98 ) 11 eo ho I Dividend input pin (LSB) iz 21 Hi I Dividend ingut pin 13 22 Ne i Dividend input pin 14 aa Ma I Dividend input pin = a4 {HG} = No connection 1S 25 Hal I Oivadend input pin +6 3 NS i Divdend input pin IF 7 Me I Dividend inaut pin 1B 28 Wi? | Diedand input pin 18 Fs] NB 1 Dividend input pin 20 = Ver = = Supply voltage inpet pin tS Vy zi a Via 7 = Ground pin (0 } aD a a 1 Dividend ingut pin (MSB) = BJ {NG} - No connectian Overflow meron Meg dudpul pin a a OVFL o Goas law on detection of an averfow in the decimal operation 2 4 | ZV | | Goon ton en dotctinn 9 die by 200 OQperalion mode salection pin 25 as | MODE | t |S MODE Hove: decimal persion mode Date is Leiched on the rising edge of clock, Guipud (O01o G8 pins) enable inpat pan 26 i] c= I DE eL lavel + 00 to 09 output enabled DE eH level : G09 09 eat to high impedance = af, 36 (We) = ie connection 1: Weeping : Gennect all Veo ping to network ground, a2 > Weeping : Connecd all Vox pine bo ihe power supply line, a T-45-23-dl MBG6047A MBS6043 Fin NO. feck ei a i MBSSU4iA | Mpasoas | Symbol Wo: = Function Deserisioa .; = i? (NG) = No connection 10 18 Va - Ground pir (0 ) = 18 Vou @ = Supply voltage input pin j+8 V7 11 a No | Dividend input pin (LSB) iz F 4 Mi | Dividend ingut pln 13 22 Ne | Dividend inqut pin 14 a Ka I Dividend iepul pin = ia (NC} = No connection is 5 Ha | Dividend ingut pin 18 3 NS | Dividend ingut pin 17 27 Na Dividend inaut pin 18 Ba i? | Dividend input pin 18 a NB 1 Dividend ingut pin 20 = Ver * = Supply voltage input pin tS V4) ai a Vou 1 = Ground pin (0 } #2 a Na Dividend input pin (MSB) = a (Ho) = No connection Ohverfiow: atrar flag cudaul pin Fx) a OVFL o Gots tow on detection of an cveriiow in the decimal oparation 2 4 | BV | | Sateen on datection a dda by seeo. Operaiion mode salecton pln 25 vs | Moe | | | NOOE Hove : decimal epersion mode Data |e leiched on the rising edge of clock, (Quiput (0016 G9 ping) enable inpart pin 26 oe k + OE eL loval : 0010 09 output enabled DE =H level : G0 00 09 eat to high impedance - aT, 36 (HC) = No connection els Veo ping : Gonnect all Vex ping to nebwork ground, 2 2 Weeping : Gorin all Vos piled ba ihe power supely line,T-45-23-al MBB6041A MBS6043 BLOCK DIAGRAM __~ 886 aie i aes Mee ages ol _<+ <+ Pipe reget ++ | tt - ["_Omyimr | ererrapar ed cur | ea Ne Y 1 vo -cove | *; Gatidsines === = Dei egrets Hote: Pin numbers conespond to thee MBSG04 1A.FUJITSU LTD SJE D MM 3749756 oo0ab9] ?T2 MMFCAJ T-45-A3-Q\ MB86041A MB86043 OPERATION DESCRIPTION Integer division mode or decimal! division mode Is selected using the MODE pin. In the integer division mode, the dividend, divisor, and quotient are operated on as positive integers. In this case, the remainder is omitted. In the decimal division mode, the decimal point is assumed to be at the left of the MSB. The dividend, divisor, and quotient are operated on as positive fixed-point decimal numbers smaller than 1. Remainder is also omitted in this mode. The dividend is 10 bits, the divisor 8 bits, and the quotient 10 bits. Data output status is controlled by the OE pin. Division by zero and overflow detection functions are provided for detection of operational errors. This device operates at a maximum speed of 20 MHz with a5-stage pipeline. The output delayed 6 cycles after input. The minimum output delay is 50 ns. (See Figure 1.) All outputs are unstable for a period of 5 clocks after the device is powered up. CLK N9 to NO D7 to Do D, = O* Overflow occurs. 8 0 QO as X Qs X Qu X as X ae K On f/f a Gur \ he DIV W L He Zero divide OVFL H" LW A Overflow occurs. OE = L" Figure 1 Timing charta S3E D Ml 3749756 OO02692 39 MBFCAU FUJITSU LTD MB86041A MB86043 SETTING OF CONTROL PINS 1. Selection @ Operation mode selection H-level Decimal division mode | Dataisa positive decimal smaller than 1. L-level Integer division mode Data is a positive integer greater than or equal to 1. @ Data output selection High impedance status The quotient is output. The remainder is omitted. 2. Precautions @ Error detection display When a divide by zero error is detected: All bits of the quotient = 1 ZDIV pin = L-level {for one cycle) When an overflow error is detected during decimal operation: All bits of the quotient = 1 OVFL pin = L-level (for one cycle) @ Precautions for decimal operation Values smaller than 1 are used forthe dividend (N), divisor (D), and quotient (Q). Therefore, if operation is performed undera condition other than N<D, the result is Q>1, causing an overtlow error.FUJITSU LTD SSE D MM 3749756 00026593 575 MFCAJ 7-45-33 MB86041A MB86043 DATA FORMAT The dividend is placed on pins NO to N9 and the divisor on pins DO to D7 in positive fixed-point format. The quotient is output on pins Q0 to Q9. Remainders are omitted. 1. Integer division mode data format Dividend (N) NO | N8 | N7 | N6 | NS | N4 | N3 | N2 | Nt | NO 2 2 2 2 2 2! 2 2 2' 2 . (Decimal point) Divisor (D) 07 | D6 | DS | D4 | D3 | D2 | Di | Do a2 | 2) 2) a] 2 | 2 | at] 2 Quotient (Q) Q9 | Q8 | Q7 | G6 | QS | Q4 | Q3 |] Q2 | Qt | Qo 2. Decimal division mode data format Dividend (N) NO | N8 | N7 | N6 | NS | N4 | N3 | N2 |] N1 | NO ef 2 | 2% 7) 2 7 2* | 2% | 2% | 27 | at | 2 | ae (Decimal point) Divisor (D) 07 | D6 | DS | D4 |] D3 | D2 } Di | Do Quotient (Q) Qa | Q8 | Q7 | G6 | O5 | Q4 | O3 | Q2 | QI | Qo Description of format: Q9g | Symbol % <@ Bit weightae DM 37H975b OOO HO) MMFCAd FUJITSU LTD T-45-23-21 MB86041A MB86043 RECOMMENDED OPERATING CONDITIONS Ves = OV Supply voltage Voo Input voltage Mi Operating temperature Ta H-level output current bon L-level output current ha INPUT AND OUTPUT CAPACITANCE Ta = +25C input pin f = 1 MHz, Voo = Viz OV Output pin f = 1 MHz, Voo = Vis OVFUJITSU LTD 5S3E D M@M@ 3749756 0002695 348 MMFCAJ T-45-23-2| MB86041A MB86043 ELECTRICAL CHARACTERISTICS 1. OC Characteristics Voo = V 45%, Ves = 0 V, Ta = +25C loos Static Vat = Voo, Via = Ves Operating H-level input voltage - Supply current L-fevel input voltage ~ H-level output voltage lou = -2 MA L-level output voltage fo. = 3.2 mA Input leakage current Vi = 0 V to Voo Output leakage current Vi = 0 V to Voo 2. AC Characteristics 1) Timing requirements Von = 5 V 5%, Ves = OV, Ta = 425C Clock cycle Clock pulse width Clock rise time - Clock fall time - Set-up time Pins NO to N9, DO to D7 Hold time Pins NO to N9, DO to.D7FUJITSU LTD. 53E D Ml 3749756 OO02b%b 284 WMFCAd T-45-Q3-al MB86041A MB86043 ELECTRICAL CHARACTERISTICS 2. AC Characteristics 2) Switching characteristics Voo = 5 V 45%, Vas = OV, Ta = +25C Time from CLK to tea - - 35 ns Q0 to Q9, ZDIV, and OVFL Valid status delay time tea Time from SE to Q0 te Q9 - - 30 ns Float status dalay time ter Time from GE to Q0 to Q9 - - 30 ns 1, Low-level to high impedance transition delay High impedance to low-level transition delay 2. High-level to high impedance transition delay High impedance to High-level transition delay Ri re Measurement pin Measurement pin rs Fs 3. Low- to High-level transition delay High- to Low-level transition delay Measurement pin o> I Cc Load conditions: Ri, = 2kQ __ CG. = 60 pF (Pins ZDIV and OVFL) 65 pF (Pins Q0 to Q9) 11FUJITSU LTD S3E ) MM 3749756 0002697 110 MMFCAd V-4S5-2Q3-2| MB86041A MB86043 TIMING CHART 1. AC characteristics (1) 24V CLK rsvp OO OWN sy y \ 04V 10% 10% tw oreO ogy kes SAKA XAXAAXAX 82 _XAXAXAAAXYAA ba tov . 42V Q9 to QO VALID VALID xX x VALID 04V o4V 2. AC characteristics (2) 24V al 04V 42V , Hi-Z Hi-Z Q9 to ao 2 {V 15V OUTPUT 37V I=, 04V ov 12FUJITSU LTD 53E D MM 374975 0002698 057 MMFCAJ T-45-23-21 MB86041A MB86043 DIP-40P-MO01 +.008 +0.20 re 2.063* 89852 400-20, AA AAAAAARAAAA AA AAR AA \ saa} 18 MAK 5432.010 ' (13.8040.25) INDEX 8 - ,600{15.24) L i Way ayyo i IT sos 020 aj (0.25+0.05) 2.277850 TF '.195(4.96) MAX .118(3.00) MIN ; 090{2.29) 1 | -100{2.54) | 018+.003 020051 MIN Dimensions in 1 MAX a TYP "(0.46 0.08) inches (millimeters) FPT-48P-M02 8772 O16 54 10612.70) MAX i 17.200.40 ee wane 012 ! ~ MOUNTING HEIGHT) pooFD30, | 002(0.05) MIN 00-910 a ; | ASTAND OFF HEIGHT) a a | , = oc oe x .535+.016 oo = (13.60+0.40) s oS 34618. 80) 7 REF J INDEX = i co ce = =a i) eo =. i] 0315(0 80), TYP +002 +0.05 ~~ .006 7 O6G4i0 1879-8 _4 UW ; 024(0.60) t ' ! ! t T ' l 7 ! 071+.012 1 i lt t ! 1 C t 1 ! ' "18020301 =| 00610 15) MAX 02010 50) Dd in MAX Inches (millimeters) 13