FUJITSU MICROELECTRONICS
DATA SHEET
Copyright©2006-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserv ed
2009.11
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system develop m en t an d the m inim al re qu ir em e nts to be checked to prevent pr ob le ms before the system
development. http://edevice.fujitsu.com/micom/en-support/
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95100AM Series
MB95108AM/F104AMS/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/
MB95F108AMS/F108ANS/F108AJS/F104AMW/F104ANW/F104AJW/F106AMW/
MB95F106ANW/F106AJW/F108AMW/F108ANW/F108AJW/FV100D-103
DESCRIPTION
The MB95100AM series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Mi crocontroller.
FEATURE
F2MC-8FX CPU core
Instruction set optimized for controllers
Multiplication and division instructions
16-bit arithmetic operations
Bit test branch instruction
Bit manipulation instructions etc.
Clock
Main clock
Main PLL clock
Sub clock (for dual clock product)
Sub PLL clock (for dual clock product) (Continued)
DS07-12614-6E
MB95100AM Series
2DS07-12614-6E
(Continued)
Timer
8/16-bit compound timer × 2 channels
16-bit reload timer
8/16-bit PPG × 2 ch annels
16-bit PPG × 2 channels
Timebase timer
Watch prescaler (for dual clock product)
LIN-UART
Full duplex double buffer
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
UART/SIO
Full duplex double buffer
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
I2C
Built-in wake-u p funct ion
External interrupt
Interrupt by edge detection (rising, falling, or both edges can be selected)
Can be used to recover from low-power consumption (standby) modes.
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected
Low-power consumption (standby) mode
Stop mode
Sleep mode
Watch mode (for dual clock product)
Timebase timer mode
I/O ports :
The number of maximum ports
Single clock pr oduct : 54 ports
Dual clock product : 52 ports
Port configuration
General-purpose I/O ports (N-ch open drain) : 6 ports
General-purpose I/O ports (CMOS) : Single cloc k product : 48 ports
Dual clock product : 46 ports
Programmable input volta ge levels of port
Automotive input level / CMOS input level / hysteresis input level
Flash memory security funct ion
Protects the content of Flash memory (Flash memory device only)
MB95100AM Series
DS07-12614-6E 3
MEMORY LINEUP
Flash RAM
MB95F104AMS/F104ANS/F104AJS 16K bytes 512 bytes
MB95F104AMW/F104ANW/F104AJW
MB95F106AMS/F106ANS/F106AJS 32K bytes 1K byte
MB95F106AMW/F106ANW/F106AJW
MB95F108AMS/F108ANS/F108AJS 60K bytes 2K bytes
MB95F108AMW/F108ANW/F108AJW
MB95100AM Series
4DS07-12614-6E
PRODUCT LINEUP
(Continued)
Part number
Parameter
MB95
108AM
MB95F
104AMS/
MB95F
106AMS/
MB95F
108AMS
MB95F
104ANS/
MB95F
106ANS/
MB95F
108ANS
MB95F
104AMW/
MB95F
106AMW/
MB95F
108AMW
MB95F
104ANW/
MB95F
106ANW/
MB95F
108ANW
MB95F
104AJS/
MB95F
106AJS/
MB95F
108AJS
MB95F
104AJW/
MB95F
106AJW/
MB95F
108AJW
Type MASK
ROM
product Flash memory product
ROM capacity*160 Kbytes (Max)
RAM capacity*12 Kbytes (Max)
Reset output Yes/No Yes No
Option*2
Clock system Selectable
single/dual
clock*3 Single clock Dual clock Single clock Dual clock
Low voltage
detection reset Yes/No No Yes No Yes
Clock supervisor No Yes
CPU functions Number of basic instructions : 136
Instruction bit length : 8 bits
Instruction length : 1 to 3 bytes
Data bit length : 1, 8, and 16 bits
Minimum instruction execution time : 61.5 ns (at machine clock freque ncy 16.25 MHz)
Interrupt processing time : 0.6 μs (at machine clock frequency 16.25 MHz)
Peripheral function s
General-purpose
I/O ports Single clock product : 54 ports (N-ch open drain : 6 ports, CMOS : 48 ports)
Dual clock product : 52 ports (N-ch open drain : 6 ports, CMOS : 46 ports)
Programmable input voltage levels of port :
Automotive input level / CMOS input level / hysteresis input level
Timebase timer Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Watchdog timer Reset generated cycle
At main oscillation clock 10 MHz : Min 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
Wild register Capable of replacing 3 bytes of ROM data
I2C Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
UART/SIO Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator
NRZ type transfe r form a t, er ro r de te cte d function
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
MB95100AM Series
DS07-12614-6E 5
(Continued)
Part number
Parameter
MB95
108AM
MB95F
104AMS/
MB95F
106AMS/
MB95F
108AMS
MB95F
104ANS/
MB95F
106ANS/
MB95F
108ANS
MB95F
104AMW/
MB95F
106AMW/
MB95F
108AMW
MB95F
104ANW/
MB95F
106ANW/
MB95F
108ANW
MB95F
104AJS/
MB95F
106AJS/
MB95F
108AJS
MB95F
104AJW/
MB95F
106AJW/
MB95F
108AJW
LIN-UART Dedicated reload timer allowing a wide ran g e of co mm u nic at ion spe ed s to be set .
Full duplex double buffer
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capa-
ble
LIN functions available as the LIN master or LIN slave.
8/10-bit A/D conve r te r
(12 channels) 8-bit or 10-bit resolution can be selected.
16-bit reload timer Two clock modes an d two cou nt er op er ating mod es can be se lected. Sq uare wa ve -
form output
Count clock : 7 internal clocks and external clock can be selected.
Counter operating mode : reload mode or one-shot mode can be selected.
8/16-bit compound
timer (2 channels) Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit t imer
× 1 channel”.
Built-in timer function, PWC function, PWM function, capture function, and square
waveform output
Count clock : 7 internal clocks and external clock can be selected
16-bit PPG
(2 channels) PWM mode or one-shot mode can be selected.
Counter operating clock : 8 selectable clock sources
Support for external trigger start
8/16-bit PPG
(2 channels) Each channel of the PPG can be us ed as 8-bit PPG × 2 channels or 16-bit PPG ×
1 channel.
Counter operating clock : Eight selectable clock sources
Watch counter
(for dual clock product) Count clock : 4 selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when
selecting clock source 1 second and setting counter value to 60)
Watch prescaler
(for dual clock product) 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
External interrupt
(12 channels) Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
Flash memory Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 1 0000 times
Data retention time : 20 years
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
(MB95F108AMS/F108ANS/F108AJS/F108AMW/F108ANW/F108AJW only)
Standby mode Sleep, stop, watch (for dual clock product) , and timebase timer
Peripheral functions
MB95100AM Series
6DS07-12614-6E
(Continued)
*1 : For ROM capacity and RAM capacity, refer to “ MEMO RY LINEUP”.
*2 : For details of option, refer to “MASK OPTION”.
*3 : Specify clock mode when ordering MASK ROM.
Note : P art number of the e valuation product in MB95100AM series is MB95FV100D-103. When using it, the MCU
board MB2146-303A-E is required.
OSCILLATION STABILIZATION WAIT TIME
The initial value of the main cloc k oscillation stabilization wait time is fix ed to the maximum v alue. The maxim um
v alue is shown as follows.
PACKAGES AND CORRESPONDING PRODUCTS
: Available
: Unavailable
Oscillation stabilization wait time Remarks
(214-2) /FCH Approx. 4.10 ms (at main oscillation clock 4 MHz)
MB95108AM
MB95F104AMS/F104ANS/
F104AJS
MB95F106AMS/F106ANS/
F106AJS
MB95F108AMS/F108ANS/
F108AJS
MB95F104AMW/F104ANW/
F104AJW
MB95F106AMW/F106ANW/
F106AJW
MB95F108AMW/F108ANW/
F108AJW
MB95FV100D-103
FPT-64P-M24
FPT-64P-M23
BGA-224P-
M08
Part
number
Parameter
MB95100AM Series
DS07-12614-6E 7
DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
Notes on Using Evaluation Products
The Evaluation product ha s not only the functions o f the MB95100AM ser ies but also those of other products
to support softw are dev elopment for multiple series and models of the F2MC-8FX f amily. The I/O addresses for
peripheral resources not used by the MB95100AM series are therefore access-barred. Read/write access to
these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting
in unexpected malfunctions of hardware or software.
P articularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or write unexpectedly) .
Also, as the read values of prohibited addresses on the evaluation product are different to the values on the
flash memory and MASK ROM products, do not use these values in the program.
The Ev alu ation p roduct do not su pport the functions of some bits in single-byte registers. Read/write access to
these bits does not cause hardware malfunctions. Since the Evaluation, Flash memory , and MASK ROM products
are designed to behave completely the same way in terms of hardware and software.
Difference of Memory Spaces
If the amount of memory on the Evaluation product is different from that of the Flash memor y or MASK ROM
product, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “ CPU CORE”.
Current Consumption
The current consumption of Flash memory product is typically greater than for MASK ROM product.
For details of current co ns um p tio n, re fer to “ ELECTRICAL CHARACTERISTICS”.
Package
F or details of information on each package, refer to “ PA CKAGES AND CORRESPONDING PRODUCTS” and
PACKAGE DIMENSIONS”.
Operating Voltage
The operating voltage are different among the Evaluation, Flash memory, and MASK ROM products.
For details of operating voltage, refer to “ ELECTRICAL CHARACTERISTICS”.
Difference between RST and MOD Pins
The RST and MOD pins are hysteresis inputs on the MASK ROM product. A pull-down resistor is provided for
the MOD pin of the MASK ROM product.
MB95100AM Series
8DS07-12614-6E
PIN ASSIGNMENT
(TOP VIEW)
(FPT-64P-M 24 , FPT-64P-M23 )
AVss
P30/AN00
P31/AN01
P32/AN02
P33/AN03
P34/AN04
P35/AN05
P36/AN06
P37/AN07
P40/AN08
P41/AN09
P42/AN10
P43/AN11
P67/SIN
P66/SOT
P65/SCK
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc 148 P64/EC1
AVR 247 P63/TO11
PE3/INT13 346 P62/TO10
PE2/INT12 445 P61/PPG11
PE1/INT11 544 P60/PPG10
PE0/INT10 643 P53/TRG1
P83 742 P52/PPG1
P82 841 P51/SDA0
P81 940 P50/SCL0
P80 10 39 P24/EC0
P71/TI0 11 38 P23/TO01
P70/TO0 12 37 P22/TO00
MOD 13 36 P21/PPG01
X0 14 35 P20/PPG00
X1 15 34 P14/PPG0
Vss 16 33 P13/TRG0/ADTG
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Vcc
C
PG2/X1A
PG1/X0A
RST
P00/INT00
P01/INT01
P02/INT02
P03/INT03
P04/INT04
P05/INT05
P06/INT06
P07/INT07
P10/UI0
P11/UO0
P12/UCK0
64
* : Single clock product is gener al-purpose port, and dual clock product is sub cloc k oscillation pin.
MB95100AM Series
DS07-12614-6E 9
PIN DESCRIPTION
(Continued)
Pin no. Pin name I/O
Circuit
type* Function
1AVccA/D converter power supply pin
2 AVR A/D converter reference input pin
3PE3/INT13
P
General-purpose I/O port.
The pins are shared with the external interrupt input.
4PE2/INT12
5PE1/INT11
6PE0/INT10
7P83
O
General-purpose I/O port
8P82
9P81
10 P80
11 P71/TI0 H
General-purpose I/O port.
The pin is shared with 16-bit reload timer ch.0 input.
12 P70/TO0 General-purpose I/O port.
The pin is shared with 16-bit reload timer ch.0 output.
13 MOD B An operating mode designation pin
14 X0 AMain clock input oscillation pin
15 X1 Main clock input/output oscillation pin
16 Vss Power supply pin (GND)
17 Vcc Power supply pin
18 C Capacitor connection pin
19 PG2/X1A H/A
Single clock product is general-purpose port (PG2) .
Dual clock product is sub clock input/output oscillation pin (32 kHz).
20 PG1/X0A Single clock product is general-purpose port (PG1) .
Dual clock product is sub clock input oscillation pin (32 kHz).
21 RST B’ Reset pin
22 P00/INT00
C
General-purpose I/O port.
The pins are shared with exter nal interrupt input. Lar ge current port.
23 P01/INT01
24 P02/INT02
25 P03/INT03
26 P04/INT04
27 P05/INT05
28 P06/INT06
29 P07/INT07
30 P10/UI0 G General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data inp ut.
MB95100AM Series
10 DS07-12614-6E
(Continued)
Pin no. Pin name I/O
Circuit
type* Function
31 P11/UO0
H
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data output.
32 P12/UCK0 General-purpose I/O port.
The pin is shared with UART/SIO ch.0 clock I/O.
33 P13/TRG0/
ADTG
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and
A/D trigger input (ADTG).
34 P14/PPG0 General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 output.
35 P20/PPG00
H
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch.0 output.
36 P21/PPG01
37 P22/TO00 General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch.0 output.
38 P23/TO01
39 P24/EC0 General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.0 clock input.
40 P50/SCL0 I
General-purpose I/O port.
The pin is shared with I2C ch.0 clock I/O.
41 P51/SDA0 General-purpose I/O port.
The pin is shared with I2C ch.0 data I/O.
42 P52/PPG1 H
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.1 output.
43 P53/TRG1 General-purpose I/O port.
The pin is shared with 16-bit PPG ch.1 trigger input.
44 P60/PPG10
K
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch.1 output.
45 P61/PPG11
46 P62/TO10 General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch.1 output.
47 P63/TO11
48 P64/EC1 General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.1 clock input.
49 P65/SCK General-purpose I/O port.
The pin is shared with LIN-UART clock I/O.
50 P66/SOT General-purpose I/O port.
The pin is shared with LIN-UART data output.
51 P67/SIN L General-purpose I/O port.
The pin is shared with LIN-UART data input.
52 P43/AN11
J
General-purpose I/O port.
The pins are shared with A/D converter analog input.
53 P42/AN10
54 P41/AN09
55 P40/AN08
MB95100AM Series
DS07-12614-6E 11
(Continued)
*: For the I/O circuit type, refer to “ I/O CIRCUIT TYPE”
Pin no. Pin name I/O
Circuit
type* Function
56 P37/AN07
J
General-purpose I/O port.
The pins are shar ed with A/D co nve r ter an alo g inp ut .
57 P36/AN06
58 P35/AN05
59 P34/AN04
60 P33/AN03
61 P32/AN02
62 P31/AN01
63 P30/AN00
64 AVss A/D converter power supply pin (GND)
MB95100AM Series
12 DS07-12614-6E
I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A
Oscillation circuit
High-speed side
Feedback resistance : approx. 1 MΩ
Low-speed side
Feedback resistance : approx. 10 MΩ
B
Only for input
Hysteresis input only for MASK ROM
product
With pull-down resistor only f or MASK
ROM product
B’
Hysteresis input only for MASK ROM
product
Reset output
C
CMOS outp ut
Hysteresis input
Automotiv e input
G
CMOS outp ut
•CMOS input
Hysteresis input
With pull-up control
Automotiv e input
X0 (X0A)
X1 (X1A)
N-ch
Standby cont rol
Clock input
R
Mode input
N-ch
P-ch
N-ch
Standby control
External interrupt
enable
Digital output
Digital output
Hysteresis input
Automotive input
R
P-ch
N-ch
P-ch
Pull-up control
Standby control
Digital output
Digital output
Hysteresis input
CMOS input
Automotive input
MB95100AM Series
DS07-12614-6E 13
(Continued)
Type Circuit Remarks
H
CMOS output
Hyster esis input
With pull-u p cont ro l
Automotive input
I
N-ch open drain output
•CMOS input
Hyster esis input
Automotive input
J
CMOS output
Hyster esis input
Analog input
With pull-u p cont ro l
Automotive input
K
CMOS output
Hyster esis input
Automotive input
P-ch
P-ch
N-ch
R
Pull-up control
Standby contr o l
Digital output
Digital output
Hysteresis input
Automotive input
N-ch
Standby control
Digital output
CMOS input
Hysteresis input
Automotive input
R
P-ch
P-ch
N-ch
Pull-up control
A/D control
Standby control
Analog input
Digital outpu t
Hysteresis input
Digital outpu t
Automotive input
P-ch
N-ch
Standby control
Hysteresis input
Digital output
Digital output
Automotive input
MB95100AM Series
14 DS07-12614-6E
(Continued)
Type Circuit Remarks
L
CMOS output
CMOS input
Hysteresis input
Automotive input
O
N-ch open drain output
Hysteresis input
Automotive input
P
CMOS output
Hysteresis input
With pull-up cont ro l
Automotive input
P-ch
N-ch
Standby control
Digital output
Hysteresis input
CMOS input
Digital output
Automotive input
N-ch
Standby control
Digital output
Hysteresis input
Automotive input
R
P-ch
P-ch
N-ch
Standby control
External
interrupt contr o l
Pull-up control
Hysteresis input
Digital output
Digital output
Automotive input
MB95100AM Series
DS07-12614-6E 15
HANDLING DEVICES
Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up ma y occur on CMOS ICs if v oltage higher than VCC or lower th an VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prev ent the analog power supply voltage (A VCC, AVR) and analog input voltage from exceeding
the digital power supply voltage (VCC) when the analog system power supply is turned on or off.
Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in po wer-supply v oltage may cause a malfunction even within the guar anteed operating range
of the Vcc power-supply volta ge.
For stabilization, in principle, keep the variation in Vcc ripple (p-p va lue) in a commercial frequency range
(50 Hz/60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the
transie nt variation rate do es n ot exceed 0.1 V/ms during a m ome ntary change such a s when the p ower supply
is switched.
Precautions for Use of External Clock
Even when an exter nal clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
Serial communicat ion
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
PIN CONNECTION
Treatment of Unused Input Pin
Lea ving unused input pins unconnect ed can cause abnormal oper ation or lat ch-up, lea ving to permanent dam-
age. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused
input/outpu t pins may be set to output mode and left open, or set to input mode and treate d the same as unused
input pins. If there is unused output pin, make it to open.
Treatment of Power Supply Pins on A/D Convert er
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 μF ceramic capacitor
as a bypass capacit or between AVCC and AVSS pins in the vicinity of this device.
MB95100AM Series
16 DS07-12614-6E
Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to a void abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lo w er the electro-ma gnetic emission le vel, to pre vent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output cu rrent rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS near
this device.
Mode Pin (MOD)
Connect the MOD pin directly to VCC or VSS pins.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance fro m th e MO D pin s to V CC or VSS pins and to provide a low-impedance connection.
Use a ceramic capacito r or a capacito r with equiv alen t f requency char acteristics. A b ypa ss capacito r of VCC pin
must have a capacitance value higher than CS. For conne ction of smooth in g ca p ac i to r CS, refer to the diagram
below.
Analog Power Supply
Always set th e s am e pote ntia l to AVCC and VCC pins. When VCC > AVCC, the c ur rent may flow through the AN00
to AN11 pins.
C
CS
C pin connection diagram
MB95100AM Series
DS07-12614-6E 17
PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL
PROGRAMMER
Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Note : For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group , Inc. TEL: +81-53-428-8380
Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming by
the parallel programmer as follows:
Programming Method
1) Set the type code of the parallel programmer to “17222”.
2) Load program data to programmer addresses 71000H to 7FFFFH.
3) Programmed by parallel progra mmer
Package Applicable adapter model Parallel programmers
FPT-64P-M24 TEF110-108F35AP AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
AF9723+AF9834 (Ver 02.08E or more)
FPT-64P-M23 TEF110-108F36AP
*: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs
data into Flash memory.
These programmer addresses are u sed for the parallel programmer to program or erase data in Flash
memory.
Flash memory CPU address Programmer address*
SA1 (4 Kbytes) 1000H71000H
1FFFH71FFFH
SA2 (4 Kbytes) 2000H72000H
2FFFH72FFFH
SA3 (4 Kbytes) 3000H73000H
3FFFH73FFFH
SA4 (16 Kbytes) 4000H74000H
7FFFH77FFFH
SA5 (16 Kbytes) 8000H78000H
BFFFH7BFFFH
SA6 (4 Kbytes) C000H7C000H
CFFFH7CFFFH
SA7 (4 Kbytes) D000H7D000H
DFFFH7DFFFH
SA8 (4 Kbytes) E000H7E000H
EFFFH7EFFFH
SA9 (4 Kbytes) F000H7F000H
FFFFH7FFFFH
Lower bankUpper bank
MB95F108AMS/F108ANS/F108AJS/F108AMW/F108ANW/F108AJW (60 Kbytes)
MB95100AM Series
18 DS07-12614-6E
Programming Method
1) Set the type code of the parallel programmer to "17222"
2) Load program data to programmer addresses 78000H to 7FFFFH.
3) Progr ammed by parallel pro grammer
Programming Method
1) Set the type code of the parallel programmer to "17222"
2) Load program data to programmer addresses 7C000H to 7FFFFH.
3) Progr ammed by parallel pro grammer
*: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs
data into Flash memory.
These programmer addresses are u sed for the parallel programmer to program or erase data in Flash
memory.
Flash memory CPU address Programmer address*
SA5 (16 Kbytes) 8000H78000H
BFFFH7BFFFH
SA6 (4 Kbytes) C000H7C000H
CFFFH7CFFFH
SA7 (4 Kbytes) D000H7D000H
DFFFH7DFFFH
SA8 (4 Kbytes) E000H7E000H
EFFFH7EFFFH
SA9 (4 Kbytes) F000H7F000H
FFFFH7FFFFH
MB95F106AMS/F106ANS/F106AJS/F106AMW/F106ANW/F106AJW (32 Kbytes)
*: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs
data into Flash memory.
These programmer addresses are u sed for the parallel programmer to program or erase data in Flash
memory.
Flash memory CPU address Programmer address*
SA6 (4 Kbytes) C000H7C000H
CFFFH7CFFFH
SA7 (4 Kbytes) D000H7D000H
DFFFH7DFFFH
SA8 (4 Kbytes) E000H7E000H
EFFFH7EFFFH
SA9 (4 Kbytes) F000H7F000H
FFFFH7FFFFH
MB95F104AMS/F104ANS/F104AJS/F104AMW/F104ANW/F104AJW (16 Kbytes)
MB95100AM Series
DS07-12614-6E 19
BLOCK DIAGRAM
P80 to P83
P14/PPG0
P53/TRG1
P65/SCK
P67/SIN
PE0/INT10 to PE3/INT13
AV
CC
AV
SS
AVR
P52/PPG1
P50/SCL0
P51/SDA0
P40/AN08 to P43/AN11
P30/AN00 to P37/AN07
P21/PPG01
P22/TO00
P23/TO01
P24/EC0
P12/UCK0 P62/TO10
P61/PPG11
P60/PPG10
P63/TO11
P00/INT00 to P07/INT07
P10/UI0
P64/EC1
P71/TI0
P66/SOT
P70/TO0
RST
X0,X1
PG2/X1A*
PG1/X0A*
MOD , V
CC
, V
SS
, C
P13/TRG0/ADTG
P20/PPG00
P11/UO0
I
2
C
F
2
MC-8FX CPU
UART/SIO
16-bit PPG ch.0
8/16-bit PPG ch.0
8/10-bit
A/D converter
C
16-bit PPG ch.1
LIN-UART
8/16-bit PPG ch.1
ROM
RAM
Port Port
External interrupt ch.8 to ch.11
8/16-bit compound
timer ch.0
16-bit reload timer
8/16-bit compound
timer ch.1
Interrupt control
Wild register
Reset control
Clock control
Watch prescaler
Watch counter
External interrupt ch.0 to ch.7
Internal bus
* : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
Other pins
MB95100AM Series
20 DS07-12614-6E
CPU CORE
1. Memory space
Memory space of the MB95100AM series is 64 Kbytes and consists of I/O area, data area, and program area.
The memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory map of the MB95100AM series is shown below.
Memory Map
0000H
0080H
0100H
0200H
0F80H
1000H
FFFFH
Extension I/O
Flash memory
60 Kbytes
RAM 3.75 Kbytes
MB95FV100D-103
I/O
0000H
0080H
0100H
0200H
Address #1
Address #2
FFFFH
Flash memory
MB95F104AMS/F104ANS/F104AJS
MB95F106AMS/F106ANS/F106AJS
MB95F108AMS/F108ANS/F108AJS
MB95F104AMW/F104ANW/F104AJW
MB95F106AMW/F106ANW/F106AJW
MB95F108AMW/F108ANW/F108AJW
I/O
RAM
Extension I/O
0000H
0080H
0100H
0200H
0880H
0F80H
1000H
FFFFH
MASK ROM
60 Kbytes
MB95108AM
I/O
RAM 2 Kbytes
Extension I/O
Register Register
Access
prohibited Access
prohibited
Register
0F80H
MB95100AM Series
DS07-12614-6E 21
Flash RAM Address #1 Address #2
MB95F104AMS/F104ANS/F104AJS 16 Kbytes 512 bytes 0280HC000H
MB95F104AMW/F104ANW/F104AJW
MB95F106AMS/F106ANS/F106AJS 32 Kbytes 1 Kbyte 0480H8000H
MB95F106AMW/F106ANW/F106AJW
MB95F108AMS/F108ANS/F108AJS 60 Kbytes 2 Kbytes 0880H1000H
MB95F108AMW/F108ANW/F108AJW
MB95100AM Series
22 DS07-12614-6E
2. Register
The MB95100AM series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
The PS can further be divided into higher 8 bit s for use as a reg ister bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits fo r use as a condition code regi st er (CCR) . (Refer to the diagram below.)
Program counter (PC) : A 16-bit register to indicate locations where instructions are stored.
Accumulator (A) : A 16-bit register for tem porary storage of arith metic operations. In the case of
an 8-bit data processing instruction, the lower one byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of a n 8-bit data p rocessin g instr uction, the lower one byte is used.
Index register (I X) : A 16-bit register for index modification.
Extra pointer (EP) : A 16-bit pointer to point to a memory address.
Stack pointer (SP) : A 16-bit register to indicate a stack area.
Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register.
PC
A
T
IX
EP
SP
PS
: Program counter
16-bit
: Accumulator
: Temporary accumulator
: Index register
: Extra pointer
: Stack pointer
: Program status
Initial Value
FFFDH
0000H
0000H
0000H
0000H
0000H
0030H
PS
RP CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
DP2 DP1 DP0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R4 R3 R2 R1 R0 H I IL1 IL0 N Z VC
DP
Structure of the Program Status
MB95100AM Series
DS07-12614-6E 23
The RP indica tes th e addres s of the regist er ban k curr ently being used . The relation ship be tween the conten t
of RP and the real address conforms to the conversion rule illustrated below:
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
Direct bank pointer (DP2 to DP0) Specified address area Mapping area
XXXB (no effect to mapping) 0000H to 007FH0000H to 007FH (without mapping)
000B (initial value)
0080H to 00FFH
0080H to 00FFH (without mapping)
001B0100H to 017FH
010B0180H to 01FFH
011B0200H to 027FH
100B0280H to 02FFH
101B0300H to 037FH
110B0380H to 03FFH
111B0400H to 047FH
H flag : Set to “1” when a carry or a borrow from bi t 3 to bit 4 occurs as a result of an arithmetic op eration.
Cleared to “0” othe rwise. This flag is for decim al ad justment ins tructions.
I flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is set to “0” when res et.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indi cated by this bit.
IL1 IL0 Interrupt level Priority
0 0 0 High
Low = no interruption
01 1
10 2
11 3
N flag : Set to “1” if the MSB is set to “1 ” as the result of an arithmetic operat ion. Cleared to “0” when the
bit is set to “0”.
Z flag : Set to “1” when an arithmetic ope ration results in “0”. Cleared to “0” otherwise.
V flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
C flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to t he shift-out value in the case of a shift instruction.
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1 b0
A7 A6 A5 A4 A3 A2 A1 A0
A15 A14 A13 A12 A11 A10 A9 A8
Rule for Conversion of Actual Addresses in the General-purpose Register Area
Generated address
RP upper OP code lower
MB95100AM Series
24 DS07-12614-6E
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8-
registers. Up to a total of 32 banks can be used on the MB95100AM series. The bank currently in use is specified
by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)
to general-purpose register 7 (R7) .
R0
R1
R2
R3
R4
R5
R6
R7
R0
This address = 0100
H
+ 8 × (RP)
R1
R2
R3
R4
R5
R6
R7
R0
R1
R2
R3
R4
R5
R6
R7
Address 100
H
107
H
1F8
H
1FF
H
Bank 31
Bank 0
8-bit
Register Bank Configuration
32 banks
Memory area
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
MB95100AM Series
DS07-12614-6E 25
I/O MAP
(Continued)
Address Register
abbreviation Register name R/W Initial value
0000HPDR0 Port 0 data register R/W 00000000B
0001HDDR0 Port 0 direction register R/W 00000000B
0002HPDR1 Port 1 data register R/W 00000000B
0003HDDR1 Port 1 direction register R/W 00000000B
0004H (Disabled) ⎯⎯
0005HWATR Oscillation stabilization wait time setting register R/W 11111111B
0006HPLLC PLL control register R/W 00000000B
0007HSYCC System clock control register R/W 1010X011B
0008HSTBC Standby control register R/W 00000000B
0009HRSRR Reset source register R/W XXXXXXXXB
000AHTBTC Timebase timer control register R/W 00000000B
000BHWPCR Watch prescaler control register R/W 00000000B
000CHWDTC Watchdog timer control register R/W 00000000B
000DH (Disabled) ⎯⎯
000EHPDR2 Port 2 data register R/W 00000000B
000FHDDR2 Port 2 direction register R/W 00000000B
0010HPDR3 Port 3 data register R/W 00000000B
0011HDDR3 Port 3 direction register R/W 00000000B
0012HPDR4 Port 4 data register R/W 00000000B
0013HDDR4 Port 4 direction register R/W 00000000B
0014HPDR5 Port 5 data register R/W 00000000B
0015HDDR5 Port 5 direction register R/W 00000000B
0016HPDR6 Port 6 data register R/W 00000000B
0017HDDR6 Port 6 direction register R/W 00000000B
0018HPDR7 Port 7 data register R/W 00000000B
0019HDDR7 Port 7 direction register R/W 00000000B
001AHPDR8 Port 8 data register R/W 00000000 B
001BHDDR8 Port 8 direction register R/W 00000000B
001CH to
0025H (Disabled) ⎯⎯
0026HPDRE Port E data register R/W 00000000B
0027HDDRE Port E direction register R/W 00000000B
0028H,
0029H (Disabled) ⎯⎯
002AHPDRG Port G data register R/W 00000000B
MB95100AM Series
26 DS07-12614-6E
(Continued)
Address Register
abbreviation Register name R/W Initial value
002BHDDRG Port G direction register R/W 00000000B
002CH (Disabled) ⎯⎯
002DHPUL1 Port 1 pull-up register R/W 00000000B
002EHPUL2 Port 2 pull-up register R/W 00000000B
002FHPUL3 Port 3 pull-up registe r R/W 00000000B
0030HPUL4 Port 4 pull-up register R/W 00000000B
0031HPUL5 Port 5 pull-up register R/W 00000000B
0032HPUL7 Port 7 pull-up register R/W 00000000B
0033H (Disabled) ⎯⎯
0034HPULE Port E pull-up register R/W 00000000B
0035HPULG Port G pull-up register R/W 00000000B
0036HT01CR1 8/16-bit compound timer 01 control status register 1 ch.0 R/W 00000000B
0037HT00CR1 8/16-bit compound timer 00 control status register 1 ch.0 R/W 00000000B
0038HT11CR1 8/16-bit compound timer 11 control status register 1 ch.1 R/W 00000000B
0039HT10CR1 8/16-bit compound timer 10 control status register 1 ch.1 R/W 00000000B
003AHPC01 8/16-bit PPG1 control register ch.0 R/W 00000000B
003BHPC00 8/16-bit PPG0 control register ch.0 R/W 00000000B
003CHPC11 8/16-bit PPG1 control register ch.1 R/W 00000000B
003DHPC10 8/16-bit PPG0 control register ch.1 R/W 00000000B
003EHTMCSRH0 16-bit reload timer control statu s register (Upper byte) ch.0 R/W 00000000B
003FHTMCSRL0 16-bit reload timer control status register (Lower byte) ch.0 R/W 00000000B
0040H,
0041H (Disabled) ⎯⎯
0042HPCNTH0 16-bit PPG status control register (Upper byte) ch.0 R/W 00000000B
0043HPCNTL0 16-bit PPG status control register ( Lower byte) ch.0 R/W 00000000B
0044HPCNTH1 16-bit PPG status control register (Upper byte) ch.1 R/W 00000000B
0045HPCNTL1 16-bit PPG status control register ( Lower byte) ch.1 R/W 00000000B
0046H,
0047H (Disabled) ⎯⎯
0048HEIC00 External interrupt circuit control register ch.0/ch.1 R/W 00000000B
0049HEIC10 External interrupt circuit control register ch.2/ch.3 R/W 00000000B
004AHEIC20 External interrupt circuit control register ch.4/ch.5 R/W 00000000B
004BHEIC30 External interrupt circuit control register ch.6/ch.7 R/W 00000000B
004CHEIC01 External interrupt circuit control register ch.8/ch.9 R/W 00000000B
004DHEIC11 External interrupt circuit control register ch.10/ch.11 R/W 00000000B
MB95100AM Series
DS07-12614-6E 27
(Continued)
Address Register
abbreviation Register name R/W Initial value
004EH,
004FH (Disabled) ⎯⎯
0050HSCR LIN-UART serial control register R/W 00000000B
0051HSMR LIN-UART serial mode register R/W 00000000B
0052HSSR LIN-UART serial status register R/W 00001000B
0053HRDR/TDR LIN-UART reception/transmission data register R/W 00000000B
0054HESCR LIN-UART extended status control register R/W 00000100B
0055HECCR LIN-UART extended communication control register R/W 000000XXB
0056HSMC10 UART/SIO serial mode control register 1 ch.0 R/W 00000000B
0057HSMC20 UART/SIO serial mode control register 2 ch.0 R/W 00100000B
0058HSSR0 UART/SIO serial status register ch.0 R/W 00000001B
0059HTDR0 UART/SIO serial output data register ch.0 R/W 00000000B
005AHRDR0 UART/SIO serial input data register ch.0 R 00000000B
005BH to
005FH (Disabled) ⎯⎯
0060HIBCR00 I2C bus control register 0 ch.0 R/W 00000000B
0061HIBCR10 I2C bus control register 1 ch.0 R/W 00000000B
0062HIBSR0 I2C bus status register ch.0 R 00000000B
0063HIDDR0 I2C data register ch.0 R/W 00000000B
0064HIAAR0 I2C address register ch.0 R/W 00000000B
0065HICCR0 I2C clock control register ch.0 R/W 00000000B
0066H to
006BH (Disabled) ⎯⎯
006CHADC1 8/10-bit A/D converter co ntrol register 1 R/W 00000000B
006DHADC2 8/10-bit A/D converter control register 2 R/W 00000000B
006EHADDH 8/10-bit A/D converter data register (Upper byte) R/W 00000000B
006FHADDL 8/10 -bit A/D converter data register (Lower byte) R/W 00000000B
0070HWCSR Watch counter status register R/W 00000000B
0071H (Disabled) ⎯⎯
0072HFSR Flash memory status register R/W 000X0000B
0073HSWRE0 Flash memory sector writing control register 0 R/W 00000000B
0074HSWRE1 Flash memory sector writing control register 1 R/W 00000000B
0075H (Disabled) ⎯⎯
0076HWREN Wild register address compare enable register R/W 00000000B
0077HWROR Wild register data test sett ing register R/W 00000000B
MB95100AM Series
28 DS07-12614-6E
(Continued)
Address Register
abbreviation Register name R/W Initial value
0078HMirror of register bank point er (RP) and dire ct bank pointer
(DP) ⎯⎯
0079HILR0 Interrupt level setting register 0 R/W 11111111B
007AHILR1 Interrupt level setting register 1 R/W 11111111B
007BHILR2 Interrupt level setting register 2 R/W 11111111B
007CHILR3 Interrupt level setting register 3 R/W 11111111B
007DHILR4 Interrupt level setting register 4 R/W 11111111B
007EHILR5 Interrupt level setting register 5 R/W 11111111B
007FH (Disabled) ⎯⎯
0F80HWRARH0 Wild register address setting register (Upper byte) ch.0 R/W 00000000B
0F81HWRARL0 Wild register address setting register (Lower byte) ch.0 R/W 00000000B
0F82HWRDR0 Wild register data setting register ch.0 R/W 00000000B
0F83HWRARH1 Wild register address setting register (Upper byte) ch.1 R/W 00000000B
0F84HWRARL1 Wild register address setting register (Lower byte) ch.1 R/W 00000000B
0F85HWRDR1 Wild register data setting register ch.1 R/W 00000000B
0F86HWRARH2 Wild register address setting register (Upper byte) ch.2 R/W 00000000B
0F87HWRARL2 Wild register address setting register (Lower byte) ch.2 R/W 00000000B
0F88HWRDR2 Wild register data setting register ch.2 R/W 00000000B
0F89H to
0F91H (Disabled) ⎯⎯
0F92HT01CR0 8/16-bit compound timer 01 control status register 0 ch.0 R/W 00000000B
0F93HT00CR0 8/16-bit compound timer 00 control status register 0 ch.0 R/W 00000000B
0F94HT01DR 8/16-bit compound timer 01 data register ch.0 R/W 00000000B
0F95HT00DR 8/16-bit compound timer 00 data register ch.0 R/W 00000000B
0F96HTMCR0 8/16-bit compound timer 00/01 timer mode control register
ch.0 R/W 00000000B
0F97HT11CR0 8/16-bit compound timer 11 control status register 0 ch.1 R/W 00000000B
0F98HT10CR0 8/16-bit compound timer 10 control status register 0 ch.1 R/W 00000000B
0F99HT11DR 8/16-bit compound timer 11 data register ch.1 R/W 00000000B
0F9AHT10DR 8/16-bit compound timer 10 data register ch.1 R/W 00000000B
0F9BHTMCR1 8/16-bit compound timer 10/11 timer mode control register
ch.1 R/W 00000000B
0F9CHPPS01 8/16-bit PPG1 cycle setting buffer register ch.0 R/W 1 1111111B
0F9DHPPS00 8/16-bit PPG0 cycle setting buffer register ch.0 R/W 1 1111111B
0F9EHPDS01 8/16-bit PPG1 duty setting buffer register ch.0 R/W 11111111B
0F9FHPDS00 8/16-bit PPG0 duty setting buffer register ch.0 R/W 11111111B
MB95100AM Series
DS07-12614-6E 29
(Continued)
Address Register
abbreviation Register name R/W Initial value
0FA0HPPS11 8/16-bit PPG1 cycle setting buffer register ch.1 R/W 11111111B
0FA1HPPS10 8/16-bit PPG0 cycle setting buffer register ch.1 R/W 11111111B
0FA2HPDS11 8/16-bit PPG1 duty setting buffer register ch.1 R/W 11111111B
0FA3HPDS10 8/16-bit PPG0 duty setting buffer register ch.1 R/W 11111111B
0FA4HPPGS 8/16-bit PPG start register R/W 00000000B
0FA5HREVC 8/16-bit PPG output inversion register R/W 00000000B
0FA6HTMRH0/
TMRLRH0 16-bit timer register (Upper byte) ch.0/
16-bit reload register (Upper byte) ch.0 R/W 00000000B
0FA7HTMRL0/
TMRLRL0 16-bit timer register (Lower byte) ch.0/
16-bit reload register (Lower byte) ch.0 R/W 00000000B
0FA8H,
0FA9H (Disabled) ⎯⎯
0FAAHPDCRH0 16-bit PPG down counter register (Upper byte) ch.0 R 00000000B
0FABHPDCRL0 16-bit PPG down counter regist er (Lower byte) ch.0 R 00000000B
0FACHPCSRH0 16-bit PPG cycle setting buffer register (Upper byte) ch.0 R/W 11111111B
0FADHPCSRL0 16-bit PPG cycle setting buffer register (Lower byte) ch.0 R/W 11111111B
0FAEHPDUTH0 16-bit PPG duty setting buffer register (Upper byte) ch.0 R/W 11111111B
0FAFHPDUTL0 16-bit PPG duty setting buffer register (Lower byte) ch.0 R/W 11111111B
0FB0HPDCRH1 16-bit PPG down counter register (Upper byte) ch.1 R 00000000B
0FB1HPDCRL1 16-bit PPG down counte r register (Lower byte) ch.1 R 00000000B
0FB2HPCSRH1 16-bit PPG cycle setting buffer register (Upper byte) ch.1 R/W 11111111B
0FB3HPCSRL1 16-bit PPG cycle setting buff er register (Lower byte) ch.1 R/W 11111111B
0FB4HPDUTH1 16-bit PPG duty setting buffer register (Upper byte) ch.1 R/W 11111111B
0FB5HPDUTL1 16-bit PPG duty setting buffer register (Lower byte) ch.1 R/W 11111111B
0FB6H to
0FBBH (Disabled) ⎯⎯
0FBCHBGR1 LIN- UART baud rate generator register 1 R/W 00000000B
0FBDHBGR0 LIN-UART baud rate generator register 0 R/W 00000000B
0FBEHPSSR0 UART/SIO dedicated baud rate generator
prescaler selection register ch.0 R/W 00000000B
0FBFHBRSR0 UART/SIO dedicated baud rate generator
baud rate setting register ch.0 R/W 00000000B
0FC0H,
0FC1H (Disabled) ⎯⎯
0FC2HAIDRH A/D input disable register (Upper byte) R/W 00000000B
0FC3HAIDRL A/D input disable register (Lower byte) R/W 00000000B
MB95100AM Series
30 DS07-12614-6E
(Continued)
R/W access symbols
Initial value symbols
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
Address Register
abbreviation Register name R/W Initial value
0FC4H to
0FE2H (Disabled) ⎯⎯
0FE3HWCDR Watch counter data register R/W 00111111B
0FE4H to
0FE6H (Disabled) ⎯⎯
0FE7HILSR2 Input level select register 2 R/W 00000000B
0FE8H,
0FE9H (Disabled) ⎯⎯
0FEAHCSVCR Clock supe rvisor control register R/W 00011100B
0FEBH to
0FEDH (Disabled) ⎯⎯
0FEEHILSR Input level select register R/W 00000000B
0FEFHWICR Interrupt pin control register R/W 01000000B
0FF0H to
0FFFH (Disabled) ⎯⎯
R/W : Readable/Writable
R : Read only
W : Write only
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
MB95100AM Series
DS07-12614-6E 31
INTERRUPT SOURCE TABLE
Interrupt source Interrupt
request
number
Vector table address Bit name of
interrupt level
setting register
Same level
priority order
(at simultaneous
occurrence)
Upper Lower
External interrupt ch.0 IRQ0 FFFAHFFFBHL00 [1 : 0] High
External interrupt ch.4
External interrupt ch.1 IRQ1 FFF8HFFF9HL01 [1 : 0]
External interrupt ch.5
External interrupt ch.2 IRQ2 FFF6HFFF7HL02 [1 : 0]
External interrupt ch.6
External interrupt ch.3 IRQ3 FFF4HFFF5HL03 [1 : 0]
External interrupt ch.7
UART/SIO ch.0 IRQ4 FFF2 HFFF3HL04 [1 : 0]
8/16-bit compound timer ch.0 (Lower) IRQ5 FFF0HFFF1HL05 [1 : 0]
8/16-bit compound timer ch.0 (Upper) IRQ6 FFEEHFFEFHL06 [1 : 0]
LIN-UART (reception) IRQ7 FFECHFFEDHL07 [1 : 0]
LIN-UART (transmission) IRQ8 FFEAHFFEBHL08 [1 : 0]
8/16-bit PPG ch.1 (Low er ) IRQ 9 FFE8HFFE9HL09 [1 : 0]
8/16-bit PPG ch.1 (Upp er ) IRQ10 FFE6HFFE7HL10 [1 : 0]
16-bit reload timer ch.0 IRQ11 FFE4HFFE5HL11 [1 : 0]
8/16-bit PPG ch.0 (Upp er ) IRQ12 FFE2HFFE3HL12 [1 : 0]
8/16-bit PPG ch.0 (Low er ) IRQ13 FFE0HFFE1HL13 [1 : 0]
8/16-bit compound timer ch.1 (Upper) IRQ14 FFDEHFFDFHL14 [1 : 0]
16-bit PPG ch.0 IRQ15 FFDCHFFDDHL15 [1 : 0]
I2C ch.0 IRQ16 FFDAHFFDBHL16 [1 : 0]
16-bit PPG ch.1 IRQ17 FFD8HFFD9HL17 [1 : 0]
8/10-bit A/D converter IRQ18 FFD6HFFD7HL18 [1 : 0]
Timebase timer IRQ19 FFD4HFFD5HL19 [1 : 0]
Watch prescaler/Watch counter IRQ20 FFD2HFFD3HL20 [1 : 0]
External interrupt ch.8
IRQ21 FFD0HFFD1HL21 [1 : 0]
External interrupt ch.9
External interrupt ch.10
External interrupt ch.11
8/16-bit compoun d ti me r ch.1 (L ower ) IRQ22 FFCEHFFCFHL22 [1 : 0]
Flash memory IRQ23 FFCCHFFCDHL23 [1 : 0] Low
MB95100AM Series
32 DS07-12614-6E
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(Continued)
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage*1Vcc
AVcc Vss 0.3 Vss + 6.0 V*2
AVR Vss 0.3 Vss + 6.0 *2
Input voltage*1VIVss 0.3 Vss + 6.0 *3
Output voltage*1VOVss 0.3 Vss + 6.0 V *3
Maximum clamp current ICLAMP 2.0 + 2.0 mA Applicable to pins*4
Total maximum clamp
current Σ|ICLAMP|20 mA Applicable to pins*4
“L” level maximum
output current IOL1 15 mA Other than P00 to P07
IOL2 15 P00 to P07
“L” level average
current IOLAV1
4
mA
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
IOLAV2 12
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
“L” level total maximum
output current ΣIOL 100 mA
“L” level total average
output current ΣIOLAV 50 mA Total average output current =
operating current × operating ratio
(Total of pins)
“H” level maximum
output current IOH1 15 mA Other than P00 to P07
IOH2 15 P00 to P07
“H” level average
current IOHAV1
4
mA
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
IOHAV2 8
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
“H” level total maximum
output current ΣIOH 100 mA
“H” level total average
output current ΣIOHAV 50 mA Total average output current =
operating current × operating ratio
(Total of pins)
MB95100AM Series
DS07-12614-6E 33
(Continued)
*1 : The parameter is based on AVSS = VSS = 0.0 V.
*2 : Apply equal potential to AVcc and Vcc. AVR should not exceed AVcc + 0.3 V.
*3 : VI and V o should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current
to/from an input is limit ed by some mean s with external components , the ICLAMP rating supersedes the VI rating.
*4 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P70, P71,
PE0 to PE3
Use within recomme nd e d operatin g co nd itio ns.
Use at DC voltage (curre nt ).
+B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcont roller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the pow er saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affect
other devices.
Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the + B input pin open.
Sample recommended circuits :
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Rating Unit
Min Max
Power consumption Pd 320 mW
Operating temperature TA 40 + 85 °C
Storage temperature Tstg 55 + 150 °C
P-ch
N-ch
Vcc
R
Input/Output Equivalent circuits
+ B input (0 V to 16 V)
Limiting
resistance
Protective diode
MB95100AM Series
34 DS07-12614-6E
2. Recommended Operating Conditions (AVss = Vss = 0.0 V)
*1 : When the low voltage detection reset is used, reset occurs while the low voltage is detected. For details on
Low voltage detection, see "(9) Low Voltage Detection" in "4. AC Characteristics".
*2 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC
pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the
diagram below.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sh eet. Users consider ing application outside th e listed conditio ns are advised to contact
their representatives beforehand.
Parameter Sym-
bol Pin name Conditions Value Unit Remarks
Min Max
Power
supply
voltage VCC,
AVCC ⎯⎯
2.42*15.5
V
At normal operating Other than
MB95FV100D-103
2.3 5.5 Retain status of
stop operation
2.7 5.5 At normal operating MB95F V100D-103
2.3 5.5 Retain status of
stop operation
A/D converter
reference
input voltage AVR ⎯⎯4.0 AVCC V
Smoothing
capacitor CS⎯⎯0.1 1.0 μF*2
Operating
temperature TA⎯⎯
40 + 85 °COther than MB95FV100D-103
+ 5 + 35 MB95FV100D-103
C
CS
C pin connec tio n dia gram
MB95100AM Series
DS07-12614-6E 35
3. DC Characteristics (Vcc = AVcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
(Continued)
Parameter Sym-
bol Pin name Conditions Value Unit Remarks
Min Typ Max
“H” level input
voltage VIH P10, P50, P51, P67 *1 0.7 Vcc Vcc +
0.3 VHysteresis
input of CMOS
input level
VIHA
P00 to P07, P10 to P14,
P20 to P24, P30 to P37,
P40 to P43, P50 to P53,
P60 to P67, P70, P71,
P80 to P83, PE0 to PE3,
PG1*2, PG2*2
0.8 VCC VCC + 0.3 V
Pin input at
selecting of
Automotive
input level
VIHS
P00 to P07, P10 to P14,
P20 to P24, P30 to P37,
P40 to P43, P50 to P53,
P60 to P67, P70, P71,
P80 to P83, PE0 to PE3,
PG1*2, PG2*2
*1 0.8 Vcc Vcc +
0.3 V
Hysteresis input
VIHM
RST, MOD
0.7 Vcc Vcc +
0.3 V
CMOS input
(MASK ROM
product is
hysteresis
input)
“L” level input
voltage VIL P10, P50, P51, P67 *1 Vss
0.3 0.3 Vcc V Hysteresis
input of CMOS
input level
VILA
P00 to P07, P10 to P14,
P20 to P24, P30 to P37,
P40 to P43, P50 to P53,
P60 to P67, P70, P71,
P80 to P83, PE0 to PE3,
PG1*2, PG2*2
VSS 0.3 0.5 VCC V
Pin input at
selecting of
Automotive
input level
VILS
P00 to P07, P10 to P14,
P20 to P24, P30 to P37,
P40 to P43, P50 to P53,
P60 to P67, P70, P71,
P80 to P83, PE0 to PE3,
PG1*2, PG2*2
*1 Vss
0.3 0.2 Vcc V
Hysteresis input
VILM
RST, MOD
Vss
0.3 0.3 Vcc V
CMOS input
(MASK ROM
product is
hysteresis
input)
MB95100AM Series
36 DS07-12614-6E
(Vcc = AVcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
(Continued)
Parameter Sym-
bol Pin name Conditions Value Unit Remarks
Min Typ Max
Open-drain
output
application
voltage
VD
P50, P51,
P80 to P83 Vss
0.3 Vss +
5.5 V
“H” level output
voltage VOH1 Output pin ot her than
P00 to P07 IOH =
4.0 mA VCC
0.5 ⎯⎯ V
VOH2 P00 to P07 IOH =
8.0 mA VCC
0.5 ⎯⎯ V
“L” level output
voltage VOL1 Output pin other than
P00 to P07, RST*3IOL = 4.0 mA ⎯⎯0.4 V
VOL2 P00 to P07 IOL = 12 mA ⎯⎯0.4 V
Input leakage
current (Hi-Z
output leakage
current)
ILI
Port other than
P50, P51, P80 to P83 0.0 V < VI <
Vcc 5 + 5 μA
When the pull-up
prohibition setting
Open-drain
output leakage
current ILIOD P50, P51,
P80 to P83 0.0 V < VI <
Vss + 5.5 V ⎯⎯ 5μA
Pull-up resistor
RPULL
P10 to P14,P20 to P24,
P30 to P37, P40 to P43,
P52, P53, P70, P71,
PE0 to PE3, PG1*2,
PG2*2
VI = 0.0 V
25 50 100 kΩ
When the pull-up
permission setting
Pull-down
resistor RMOD MOD VI = Vcc 25 50 100 kΩMASK ROM product
Input
capacitance CIN Other than AVcc, AVss,
AVR, Vcc, Vss f = 1 MHz 515pF
Power supply
current*4
ICC
Vcc
(External clock
operation)
VCC = 5.5 V
FCH = 20 MHz
FMP = 10 MHz
Main clock
mode
(divided by 2)
9.5 12.5 mA Flash memory product
(At other than writing
and erasing)
30 35 mA Flash memory product
(At writing and
erasing)
7.2 9.5 mA MASK ROM product
FCH = 32 MHz
FMP = 16 MHz
Main clock
mode
(divided by 2)
15.2 20.0 mA Flash memory prod uct
(At other than writing
and erasing)
35.7 42.5 mA Flash memory prod uct
(At writing and
erasing)
11.6 15.2 mA MASK ROM product
MB95100AM Series
DS07-12614-6E 37
(Vcc = AVcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C )
(Continued)
Parameter Sym-
bol Pin name Conditions Value Unit Remarks
Min Typ Max
Power supply
current*4
ICCS
Vcc
(External clock
operation)
VCC = 5.5 V
FCH = 20 MHz
FMP = 10 MHz
Main sleep mode
(divided by 2)
4.5 7.5 mA
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
7.2 12.0 mA
ICCL
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2) ,
TA = + 25 °C
45 100 μA
Dual clock
product only
ICCLS
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2) ,
TA = + 25 °C
10 81 μA
Dual clock
product only
ICCT
VCC = 5.5 V
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
4.6 27.0 μA
Dual clock
product only
ICCMPLL
VCC = 5.5 V
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
9.3 12.5 mA Flash memory
product
7.0 9.5 mA MASK ROM
product
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
14.9 20.0 mA Flash memory
product
11.2 15.2 mA MASK ROM
product
ICCSPLL
VCC = 5.5 V
FCL = 32 kHz
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
160 400 μA
Dual clock
product only
MB95100AM Series
38 DS07-12614-6E
(Continued) (Vcc = AVcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
*1 : P10, P50, P51, and P67 can s witch the inpu t le ve l to either the “CMOS input lev el” or “h ysteresis input lev el”.
The switching of the input level can be set by the input level selection re gis te r (ILS R) .
*2 : Single clock products only
*3 : Product without clock supervisor only
*4 : The power-supply current is determined by the external clock. Wh en the low voltage detection option is
selected, the power-supply current will be a value of adding current consumption of the low voltage detection
circuit (ILVD) to the specified value. Also, when both low voltage detection option and clock supervisor are
selected, the power-supply current will be a value of adding current consumption of the low voltage detection
circuit (ILVD) and current consumption of internal CR oscillator (ICSV) to the specified value.
Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL.
Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
Parameter Sym-
bol Pin name Conditions Value Unit Remarks
Min Typ Max
Power
supply
current*4ICTS
VCC
(External clock
operation)
VCC = 5.5 V
FCH = 10 MHz
Timebase timer mode
TA = + 25 °C
0.15 1.10 mA
ICCH VCC = 5.5 V
Sub stop mode
TA = + 25 °C3.5 20 μAMain stop
mode for single
clock product
ILVD VCC Current consumption for
low voltage detection
circuit only 38 50 μA
ICSV At oscillating 100 kHz
current consumption of
internal CR oscillator 20 36 μA
IA
AVcc VCC = 5.5 V
FCH = 16 MHz
At operating of A/D
conversion
2.4 4.7 mA
IAH
VCC = 5.5 V
FCH = 16 MHz
At stopping A/D
conversion
TA = + 25 °C
15μA
MB95100AM Series
DS07-12614-6E 39
4. AC Characteristics
(1) Clock Timing (Vcc = 2.42 V to 5.0 V, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
Parameter Sym-
bol Pin name Condi-
tions Value Unit Remarks
Min Typ Max
Clock frequency
FCH X0, X1
1.00 16.25 MHz When using main
oscillation circuit
1.00 32.50 MHz When using external clock
3.00 10.00 MHz Main PLL multiplied by 1
3.00 8.13 MHz Main PLL multiplied by 2
3.00 6.50 MHz Main PLL multiplied by 2.5
FCL X0A, X1A 32.768 kHz When using sub
oscillation circuit
32.768 kHz When using sub PLL
Clock cycle time tHCYL X0, X1 61.5 1000 ns When using oscillation
circuit
30.8 1000 ns When using external clock
tLCYL X0A, X1A 30.5 μs When using sub clock
Input clock pulse width tWH1
tWL1 X0 61.5 ⎯⎯ns When using external clock
Duty ratio is about 30% to
70%.
tWH2
tWL2 X0A 15.2 μs
Input clock rise time and
fall time tCR
tCF X0, X0A ⎯⎯ 5ns
When using external clock
MB95100AM Series
40 DS07-12614-6E
tHCYL
tWH1
tCR
0.2 VCC
X0
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tCF
tWL1
X0 X1
FCH
X0
FCH
X1
Figure of main clock input port external connection
When using a crystal or
ceramic oscillator When using exter nal clock
Open
MicrocontrollerMicrocontroller
tLCYL
tWH2
tCR
0.1 VCC
X0A 0.8 VCC 0.8 VCC
0.1 VCC 0.1 VCC
tCF
tWL2
X0A X1A
FCL
X0A
FCL
X1A
Figure of sub clock input port external connection
When using a crystal or
ceramic oscillator When using extern al clo ck
Open
MicrocontrollerMicrocontroller
MB95100AM Series
DS07-12614-6E 41
(2) Source Clock/Machine Clock (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Clock before settin g div i sion due to m ach in e cloc k division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
Main clock divided by 2
PLL multiplication of main clock (select from 1, 2, 2.5 multiplication)
Sub clock divided by 2
PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows .
Source clock (no division)
Source clock divided by 4
Source clock divided by 8
Source clock divided by 16
Parameter Sym-
bol Pin
name Value Unit Remarks
Min Typ Max
Source clock*1
(Clock before setting
division) tSCLK
61.5 2000 ns
When using main clock
Min : FCH = 16.25 MHz,
PLL multiplied by 1
Max : FCH = 1 MHz, divided by 2
7.6 61.0 μsWhen using sub cloc k
Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
Source clock frequency FSP 0.50 16.25 MHz When using main clock
FSPL 16.384 131.072 kHz When using sub clock
Machine clock*2
(Minimum instruction
execution time) tMCLK
61.5 32000 ns When using main clock
Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
7.6 976.5 μsWhen using su b cloc k
Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
Machine clock
frequency FMP 0.031 16.250 MHz When using main clock
FMPL 1.024 131.072 kHz When using sub clock
MB95100AM Series
42 DS07-12614-6E
FCH
(main oscillation)
FCL
(sub oscillation)
Divided by 2
Main PLL
× 1
× 2
× 2.5
Divided by 2
Sub PLL
× 2
× 3
× 4
SCLK
( source clock ) MCLK
( machine clock )
Clock mode select bit
( SYCC : SCS1, SCS0 )
Division
circuit
× 1
× 1/4
× 1/8
× 1/16
Outline of cloc k generation block
MB95100AM Series
DS07-12614-6E 43
16.25 MHz0.5 MHz
2.42
3 MHz
5.5
131.072 kHz16.384 kHz
2.42
32 kHz
5.5
10 MHz
3.5
Operating voltage (V)
Source clock frequency (FSPL) Main clock operating gua rantee range
Sub PLL, Sub clock mode, watch mode,
operating guarantee range Main clock mode, main PLL mode
operating guarantee rang e
PLL operating guarantee range
PLL operating guarantee range
Operating voltage (V)
Source clock frequency (FSP)
Operating voltage Operating frequency (TA = 40 °C to + 85 °C)
MB95F104AMS/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/F108AMS/F108ANS/F108AJS/F104AMW/
MB95F104ANW/F104AJW/F106AMW/F106ANW/F106AJW/F108AMW/F108ANW/F108AJW
Operating voltage Operating frequency (TA = + 5 °C to + 35 °C)
MB95FV100D-103
2.7
5.5
131.072 kHz16.384 kHz
2.7
32 kHz
5.5
16.25 MHz0.5 MHz 3 MHz 10 MHz
3.5
Source clock frequency (FSPL)
Operating voltage (V)
Sub PLL, sub clock mode and
watch mode operation guarantee range
PLL operati on guarantee range
Source clock frequency (FSP)
Operating voltage (V)
PLL operation guarantee range
Main clock operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
MB95100AM Series
44 DS07-12614-6E
10 MHz
9 MHz
8 MHz
7.5MHz
7 MHz
6 MHz
5 MHz
4 MHz
3 MHz
0 MHz 3 MHz 4 MHz 5 MHz 6.4 MHz 8 MHz 10 MHz
11 MHz
12 MHz
13 MHz
14 MHz
15 MHz
16 MHz
Main PLL operation frequency
Main clock frequency (FMP)
Source clock frequency (FSP)
× 2.5
× 2 × 1
MB95100AM Series
DS07-12614-6E 45
(3) External Reset (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Refer to “ (2) Source Clock/Machin e Clock” for tMCLK.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator , the oscillation
time is between sever al ms and tens of ms . In cer amic oscillators , the oscillation time is between hundreds of
μs and several ms. In the external clock, the oscillation time is 0 ms.
Parameter Symbol Value Unit Remarks
Min Max
RST “L” level
pulse width tRSTL
2 tMCLK*1ns At normal operating
Oscillation time of oscillator*2
+ 100 ⎯μsAt stop mode, sub clock mode,
sub sleep mode, and watch mode
100 ⎯μs At timebase timer mode
tRSTL
0.2 VCC
RST 0.2 VCC
tRSTL
0.2 VCC 0.2 VCC
100 μs
RST
X0
At normal operating
At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
Internal
operating
clock
Internal reset
90% of
amplitude
Oscillation time
of oscillator Oscillation stabilization wait time
Execute instruction
MB95100AM Series
46 DS07-12614-6E
(4) Power-on Reset (AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
Note : Sudden chang e of power supply voltage may activate the power-on reset fu nc tion . Wh en cha ng ing power
supply voltages during operation, set the slope of rising within 30 mV/ms as shown below
.
Parameter Symbol Conditions Value Unit Remarks
Min Max
Power supply rising time tR⎯⎯50 ms
Power supply cutoff time tOFF 1ms Waiting time until
power-on
0.2 V0.2 V
tOFFtR
2.5 V
0.2 V
VCC
VCC
2.3 V
VSS
Hold condition in STOP mode
Limiting the slope of rising within
30 mV/ms is recommended.
MB95100AM Series
DS07-12614-6E 47
(5) Peripheral Input Timing (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Value Unit
Min Max
Peripheral input “H” pulse
width tILIH INT00 to INT07,
INT10 to INT13,
EC0, EC1, TI0, TRG0/ADTG,
TRG1
2 tMCLK*ns
Peripheral input “L” pulse
width tIHIL 2 tMCLK*ns
tILIH
INT00 to INT07,
INT10 to INT13, EC0, EC1,
TI0, TRG0/ADTG, TRG1
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tIHIL
MB95100AM Series
48 DS07-12614-6E
(6) UART/SIO, Serial I/O Tim ing (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC UCK0 Internal
clock
operation
4 tMCLK*ns
UCK UO time tSLOV UCK0, UO0 190 + 190 ns
Valid UI UCK tIVSH UCK0, UI0 2 tMCLK*ns
UCK valid UI hold time tSHIX UCK0, UI0 2 tMCLK*ns
Serial clock “H” pulse width tSHSL UCK0
External
clock
operation
4 tMCLK*ns
Serial clock “L” pulse width tSLSH UCK0 4 tMCLK*ns
UCK UO time tSLOV UCK0, UO0 190 ns
Valid UI UCK tIVSH UCK0, UI0 2 tMCLK*ns
UCK valid UI hold time tSHIX UCK0, UI0 2 tMCLK*ns
t
SCYC
t
IVSH
0.8 V
CC
0.2 V
CC
0.8 V
CC
0.2 V
CC
t
SHIX
t
SLOV
0.8 V 2.4 V 0.8 V
2.4 V
UCK0
UO0
UI0
0.8 V
t
SLSH
t
IVSH
t
SHIX
t
SLOV
0.2 V
CC
0.2 V
CC
0.8 V
CC
0.8 V
CC
t
SHSL
2.4 V
UCK0
UO0
UI0
0.8 V
0.8 V
CC
0.2 V
CC
0.8 V
CC
0.2 V
CC
Internal shift clock mode
External shift clock mode
MB95100AM Series
DS07-12614-6E 49
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial cloc k delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial cloc k delay function is used to delay half clock for the output signal of se rial clock.
*3 : Refe r to “ (2) Source Clock/Machine Clock” for tMCLK.
Parameter Sym-
bol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK Intern al clock
operation output pin :
CL = 80 pF + 1 TTL.
5 tMCLK*3ns
SCK SOT delay time tSLOVI SCK, SOT 95 + 95 ns
Valid SIN SCK tIVSHI SCK, SIN tMCLK*3 + 190 ns
SCK valid SIN hold time tSHIXI SCK, SIN 0 ns
Serial clock “L” pulse width tSLSH SCK
External clock
operation outp ut pin :
CL = 80 pF + 1 TTL.
3 tMCLK*3 tRns
Serial clock “H” pulse width tSHSL SCK tMCLK*3 + 95 ns
SCK SOT delay time tSLOVE SCK, SOT 2 tMCLK*3 + 95 ns
Valid SIN SCK tIVSHE SCK, SIN 190 ns
SCK valid SIN hold time tSHIXE SCK, SIN tMCLK*3 + 95 ns
SCK fall time tFSCK 10 ns
SCK rise time tRSCK 10 ns
MB95100AM Series
50 DS07-12614-6E
0.8 V 0.8 V
2.4 V
tSLOVI
tIVSHI tSHIXI
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
2.4 V
0.8 V
SCK
SOT
SIN
tSCYC
tSLOVE
tIVSHE tSHIXE
0.8 VCC 0.8 VCC
0.8 VCC 0.8 VCC0.8 VCC
0.2 VCC
0.2 VCC 0.2 VCC
0.2 VCC
2.4 V
0.8 V
tR
tF
SCK
SOT
SIN
tSLSH tSHSL
Internal shift clock mode
External shift clock mode
MB95100AM Series
DS07-12614-6E 51
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refe r to “ (2) Sou rc e Clock/Machin e Clock” for tMCLK.
Parameter Sym-
bol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
5 tMCLK*3ns
SCK SOT delay time tSHOVI SCK, SOT 95 + 95 ns
Valid SIN SCK tIVSLI SCK, SIN tMCLK*3 + 190 ns
SCK valid SIN hold time tSLIXI SCK, SIN 0 ns
Serial clock “H” pulse width tSHSL SCK
External clock
operation output pin :
CL = 80 pF + 1 TTL.
3 tMCLK*3 tRns
Serial clock “L” pulse width tSLSH SCK tMCLK*3 + 95 ns
SCK SOT delay time tSHOVE SCK, SOT 2 tMCLK*3 + 95 ns
Valid SIN SCK tIVSLE SCK, SIN 190 ns
SCK valid SIN hold time tSLIXE SCK, SIN tMCLK*3 + 95 ns
SCK fall time tFSCK 10 ns
SCK rise time tRSCK 10 ns
MB95100AM Series
52 DS07-12614-6E
0.8 V
2.4 V 2.4 V
tSHOVI
tIVSLI tSLIXI
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
2.4 V
0.8 V
SCK
SOT
SIN
tSCYC
tSHOVE
tIVSLE tSLIXE
0.8 VCC
0.8 VCC 0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC 0.2 VCC0.2 VCC
0.2 VCC
2.4 V
0.8 V
tF
tR
SCK
SOT
SIN
tSHSL tSLSH
Internal shift clock mode
External shift clock mode
MB95100AM Series
DS07-12614-6E 53
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial cloc k delay function is used to delay half clock for the output signal of se rial clock.
*3 : Refe r to “ (2) Source Clock/Machine Clock” for tMCLK.
Parameter Sym-
bol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
5 tMCLK*3ns
SCK SOT delay time tSHOVI SCK, SOT 95 + 95 ns
Valid SIN SCK tIVSLI SCK, SIN tMCLK*3 + 190 ns
SCK valid SIN hold time tSLIXI SCK, SIN 0 ns
SOT SCK delay time tSOVLI SCK, SOT 4 tMCLK*3ns
SCK
SOT
SIN
2.4 V
0.8 V
0.8 V
t
SHOVI
2.4 V
0.8 V
0.8 V
CC
0.2 V
CC
0.8 V
CC
0.2 V
CC
2.4 V
0.8 V
t
SCYC
t
SOVLI
tIVSLI tSLIXI
MB95100AM Series
54 DS07-12614-6E
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refe r to “ (2) Sou rc e Clock/Machin e Clock” for tMCLK.
Parameter Sym-
bol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operating output pin :
CL = 80 pF + 1 TTL.
5 tMCLK*3ns
SCK SOT delay time tSLOVI SCK, SOT 95 + 95 ns
Valid SIN SCK tIVSHI SCK, SIN tMCLK*3 + 190 ns
SCK valid SIN hold time tSHIXI SCK, SIN 0 ns
SOT SCK delay time tSOVHI SCK, SOT 4 tMCLK*3ns
SCK
SOT
SIN
2.4 V 2.4 V
0.8 V tSLOVI
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
2.4 V
0.8 V
tSCYC
tSOVHI
tIVSHI tSHIXI
MB95100AM Series
DS07-12614-6E 55
(8) I2C Timing (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT ha ve only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSU;DAT 250 ns must then be met.
Parameter Symbol Pin
name Conditions
Value
Unit
Standard-
mode Fast-mode
Min Max Min Max
SCL clock frequency fSCL SCL0 R = 1.7 kΩ,
C = 50 pF*10 100 0 400 kHz
(Repeat) Start condition hold time
SDA SCL tHD;STA SCL0
SDA0 4.0 0.6 ⎯μs
SCL clock “L” width tLOW SCL0 4.7 1.3 ⎯μs
SCL clock “H” width tHIGH SCL0 4.0 0.6 ⎯μs
(Repeat) Start condition setup time
SCL SDA tSU;STA SCL0
SDA0 4.7 0.6 ⎯μs
Data hold time SCL SDA tHD;DAT SCL0
SDA0 03.45*
200.9*
3μs
Data setup time SDA SCL tSU;DAT SCL0
SDA0 0.25 0.1 ⎯μs
Stop condition setup time SC L
SDA tSU;STO SCL0
SDA0 40.6 ⎯μs
Bus free time between stop
condition and start condition tBUF SCL0
SDA0 4.7 1.3 ⎯μs
SDA0
SCL0
tWAKEUP
tHD;STA tSU;DAT
tHD;STA
tSU;STA
tLOW tHD;DAT tHIGH
tSU;STO
tBUF
MB95100AM Series
56 DS07-12614-6E
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
(Continued)
Parameter Sym-
bol Pin
name Condition Value*2Unit Remarks
Min Max
SCL clock “L” width tLOW SCL0 R = 1.7 kΩ,
C = 50 pF*1 (2 + nm / 2) tMCLK 20 ns Master mode
SCL clock “H” width tHIGH SCL0 (nm / 2) tMCLK 20 (nm / 2 ) tMCLK + 20 ns Master mode
Start condition hold
time tHD;STA SCL0
SDA0 (1 + nm / 2) tMCLK 20 (1 + nm) tMCLK + 20 ns
Master mode
Maximum value is
applied when m, n = 1, 8.
Otherwise, the minimum
value is applied.
Stop condition setup
time tSU;STO SCL0
SDA0 (1 + nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20 ns Master mode
Start condition setup
time tSU;STA SCL0
SDA0 (1 + nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20 ns Master mode
Bus free time between
stop condition and
start condition tBUF SCL0
SDA0 (2 nm + 4) tMCLK 20 ns
Data hold time tHD;DAT SCL0
SDA0 3 tMCLK 20 ns Master mode
Data setup time
tSU;DAT SCL0
SDA0 (2 + nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20 ns
Master mode
When assuming that “L”
of SCL is not extended,
the minimum value is
applied to first bit of
continuous data.
Otherwise, the maximum
value is applied.
Setup time between
clearing interrupt and
SCL rising tSU;INT SCL0 (nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20 ns
Minimum value is
applied to interrupt at 9th
SCL.
Maximum value is
applied to interrupt at 8th
SCL.
SCL clock “L” width tLOW SCL0 4 tMCLK 20 ns At reception
SCL clock “H” width tHIGH SCL0 4 tMCLK 20 ns At reception
Start condition
detection tHD;STA SCL0
SDA0 2 tMCLK 20 ns Undetected when 1 tMCLK
is used at reception
Stop conditi on
detection tSU;STO SCL0
SDA0 2 tMCLK 20 ns Undetected when 1 tMCLK
is used at reception
Restart detection
condition tSU;STA SCL0
SDA0 2 tMCLK 20 ns Undetected when 1 tMCLK
is used at reception
Bus free time tBUF SCL0
SDA0 2 tMCLK 20 ns At reception
Data hold time tHD;DAT SCL0
SDA0 2 tMCLK 20 ns At slave transmission
mode
Data setup time tSU;DAT SCL0
SDA0 tLOW 3 tMCLK 20 ns At slave transmission
mode
MB95100AM Series
DS07-12614-6E 57
(Continued) (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : Refe r to “ (2 ) S ourc e C lock/Machin e Clo ck” for tMCLK.
m is CS4 bit and CS3 bit (bit 4 and bit 3) of cloc k control register (ICCR0) .
n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR0) .
Actual timing of I2C is de termined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n limits the machine clock that can be used below.
(m, n) = (1, 8) : 0.9 MHz < tMCLK 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK 4 MHz
(m, n) = (1, 98) : 0.9 MHz < tMCLK 10 MHz
Fast-mode :
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n limits the machine clock that can be used below.
(m, n) = (1, 8) : 3.3 MHz < tMCLK 4 MHz
(m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK 8 MHz
(m, n) = (6, 4) : 3.3 MHz < tMCLK 10 MHz
Parameter Sym-
bol Pin
name Condition Value*2Unit Remarks
Min Max
Data hold time tHD;DAT SCL0
SDA0 R = 1.7 kΩ,
C = 50 pF*10ns At reception
Data setup time tSU;DAT SCL0
SDA0 tMCLK 20 ns At reception
SDA↓→SCL
(at wake-up function) tWAKEUP SCL0
SDA0
Oscillation stabilization
wait time
+ 2 tMCLK 20 ns
MB95100AM Series
58 DS07-12614-6E
(9) Low Voltage Detection (AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
Parameter Symbol Value Unit Remarks
Min Typ Max
Release voltage VDL+ 2.52 2.70 2.88 V At power-supply rise
Detection voltage VDL- 2.42 2.60 2.78 V At power-supply fall
Hysteresis width VHYS 70 100 mV
Power-supply start voltage Voff ⎯⎯2.3 V
Power-supply end voltage Von 4.9 ⎯⎯V
Power-supply voltage
change time
(at power supply rise) tr
0.3 ⎯⎯μs Slope of power supply that reset release
signal generates
3000 ⎯μs Slope of power supply that reset release
signal generates within rating (VDL+)
Power-supply voltage
change time
(at power supply fall) tf
300 ⎯⎯μs Slope of power supply that reset
detection signal generates
300 ⎯μs Slope of power supply that reset
detection signal generates within rating
(VDL-)
Reset release delay time td1 ⎯⎯400 μs
Reset detection delay time td2 ⎯⎯30 μs
Current consumpt ion ILVD 38 50 μA Current consumption for low voltage
detection circuit only
VHYS
td2 td1
tr
tf
VCC
VCC
Von
Voff
VDL+
VDL-
Internal reset signal
time
time
MB95100AM Series
DS07-12614-6E 59
(10) Clock Supervisor Clock (Vcc = AVcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
Parameter Symbol Value Unit Remarks
Min Typ Max
Oscillation frequency fOUT 50 100 200 kHz
Oscillation start time twk ⎯⎯10 μs
Current consumpt ion ICSV 20 36 μACurr ent consumption of built-in CR
oscillator, at oscillation of 100 kHz
MB95100AM Series
60 DS07-12614-6E
5. A/D Converter
(1) A/D Conver ter Electrical Characteristics
(AVcc = Vcc = 4.0 V to 5.5 V, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
Parameter Symbol Value Unit Remarks
Min Typ Max
Resolution
⎯⎯10 bit
Total error 3.0 + 3.0 LSB
Linearity error 2.5 + 2.5 LSB
Differential linear error 1.9 + 1.9 LSB
Zero transition voltage VOT AVss
1.5 LSB AVss +
0.5 LSB AVss +
2.5 LSB V
Full-scale transition
voltage VFST AVR
3.5 LSB AVR
1.5 LSB AVR +
0.5 LSB V
Compare time 0.9 16500 μs 4.5 V AVcc 5.5 V
1.8 16500 μs 4.0 V AVcc < 4.5 V
Sampling time
0.6 ⎯∞μs4.5 V AVcc 5.5 V,
At external impedance <
5.4 kΩ
1.2 ⎯∞μs4.0 V AVcc < 4.5 V,
At external impedance <
2.4 kΩ
Analog input current IAIN 0.3 + 0.3 μA
Analog input voltage VAIN AVss AVR V
Reference voltage AVss + 4.0 AVcc V AVR pin
Reference voltage
supply current IR600 900 μAAVR pin,
During A/D operation
IRH ⎯⎯ 5μAAVR pin,
At stop mode
MB95100AM Series
DS07-12614-6E 61
(2) Notes on Using A/D Converter
About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If th e external impedance is too high to keep sufficient sampling
time, the analog v oltage charged to th e internal sample and hold capacitor is insufficient, adv er sely aff ecting A/
D conver sion pr ecision. Therefore, to satisfy the A/D conversion precision stan dard, co nsider the re lationsh ip
between t he exte rnal impedance and minim um sampling time and either adjust the register v alue and operat ing
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
About errors
As |AVR AVSS| becomes smaller, values of relati ve errors grow larger.
R
C
Analog input
Note : The values are refe rence values.
Analog input equivalen t circuit
RC
4.5 V AVcc 5.5 V 2.0 kΩ (Max) 16 pF (Max)
4.0 V AVcc < 4.5 V 8 .2 kΩ (Max) 16 pF (Max)
Comparator
During sampling : ON
0246810 12 14
0
10
20
30
40
50
60
70
80
90
100
AV
CC
4.5 V
AV
CC
4.0 V
01234
0
2
4
6
8
10
12
14
16
18
20
AVCC 4.5 V
AVCC 4.0 V
(External impedance = 0 kΩ to 100 kΩ)(External impedance = 0 kΩ to 20 kΩ)
Minimum sampling time [μs]
External impedance [kΩ]
Minimum sampling time [μs]
External impedance [kΩ]
The relationship between external impedance and minimum sampling time
MB95100AM Series
62 DS07-12614-6E
(3) Definition of A/D Converter Te rms
Resolution
The level of analog variation that can be distinguished by the A/D converte r.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
Linearity error (unit : LSB)
The deviation between the value along a straight line co nn ectin g th e zero transition point (“00 00 00 00 00”
“00 0000 0001”) of a device and the full-scale transition point (“11 1111 1111” “11 1111 1110”)
compared with the actual conversion v alues obtained.
Differential linear error (Unit : LSB)
Deviation of input volt age, which is required for changing output code by 1 LSB, from an ideal value.
Total error (unit: LSB)
Diff e re nce b etw ee n a ctual and t heo retical values , caus ed by a zero tr a nsiti on err or, full-scale transition e rr or,
linearity error, quantum error, and noise.
(Continued)
VFST
1.5 LSB
3FFH
3FEH
3FDH
004H
003H
002H
001H
3FFH
3FEH
3FDH
004H
003H
002H
001H
1 LSB
0.5 LSB
VOT
AVSS AVR AVSS
VNT
AVR
{1 LSB × (N 1) + 0.5 LSB}
1 LSB =AVR AVss
1024 (V) Total error of
digital output N VNT {1 LSB × (N 1) + 0.5 LSB}
1 LSB
Ideal I/O characteristics To tal error
Digital output
Analog input Analog input
Digital output
[LSB]
Actual conversion
characteristic
Actual conversion
characteristic
Ideal characteristics
N : A/D converter digital outp u t valu e
VNT : A voltage at which digit al output transits from (N 1) to N.
=
MB95100AM Series
DS07-12614-6E 63
(Continued)
AVSS AVR
AVSS AVR AVSS AVR
VNT
AVSS AVR
001H
002H
003H
004H
3FCH
3FDH
3FEH
3FFH
001H
002H
003H
004H
3FDH
3FEH
3FFH
N-2H
N-1H
NH
N+1H
{1 LSB × N + VOT}
VNT
V (N+1)T
Full-scale transition error
Digital outpu t
Actual conversion
characteristic
Actual conversion
characteristic
Ideal
characteristics
Analog input
VFST
(measurement
value)
Zero transition error
Digital output
Actual conversion
characteristic
Actual conversion
characteristic
Analog input
VOT (measurement value)
1
Differential linear error
in digital output N V (N + 1) T VNT
1 LSB
Linearity error in
digital output N VNT {1 LSB × N + VOT}
1 LSB
Linearity error
Digital output
Actual conversion
characteristic
Actual conversion
characteristic
Analog input
Ideal characteristics
Differential linear error
Digital output
Actual conversion
characteristic
Actual conversion
characteristic
Analog input
Ideal characteristics
VFST
(measurement
value)
VOT (measurement value)
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N 1) to N.
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVR 1.5 LSB [V]
Ideal
characteristics
=
=
MB95100AM Series
64 DS07-12614-6E
6. Flash Memory Program/Erase Characteristics
*1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 4.5 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equati on to translate high temperature
measurements into normalized value at +85 °C) .
Parameter Value Unit Remarks
Min Typ Max
Sector erase time
(4 Kbytes sector) 0.2*10.5*2sExcludes 00H programming prior erasure.
Sector erase time
(16 Kbytes sector) 0.5*17.5*2sExclud es 00H programming prior erasure.
Byte programming time 32 3,600 μs Excludes system-level overhead.
Erase/program cycle 10000 ⎯⎯cycle
Power supply voltage at erase/
program 4.5 5.5 V
Flash memory data retention
time 20*3⎯⎯year Average TA = +85 °C
MB95100AM Series
DS07-12614-6E 65
MASK OPTION
* : Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset output.
No.
Part number MB95108AM
MB95F104AMS
MB95F104ANS
MB95F104AJS
MB95F106AMS
MB95F106ANS
MB95F106AJS
MB95F108AMS
MB95F108ANS
MB95F108AJS
MB95F104AMW
MB95F104ANW
MB95F104AJW
MB95F106AMW
MB95F106ANW
MB95F106AJW
MB95F108AMW
MB95F108ANW
MB95F108AJW
MB95FV100D-103
Specifying procedure Specify when
ordering
MASK
Setting
disabled Setting
disabled Setting
disabled
1Clock mode select
Single-system clock mode
Dual-system clock mode Selectable Single-system
clock mode Dual-system
clock mode Changing by the
switch on MCU board
2
Low voltage detection
reset*
With low voltage detection
reset
Without low voltage
detection reset
Specify when
ordering MASK Specified by
part number Specified by
part number Changing by the
switch on MCU board
3Clock supervisor*
With clock supervisor
Without clock supervisor
Specify when
ordering MASK Specified by
part number Specified by
part number Changing by the
switch on MCU board
4
Reset output*
With reset output
Without reset output Specify when
ordering MASK Specified by
part number Specified by
part number
MCU board switch set
as following ;
With superviso r :
Without reset
output
Without supervisor :
With reset output
5
Oscillation stabilization
wait time Fixed to
oscillation
stabilization wait
time of
(214-2) /FCH
Fixed to
oscillation
stabilization wait
time of
(214-2) /FCH
Fixed to
oscillation
stabilization wait
time of
(214-2) /FCH
Fixed to
oscillation
stabilization wait
time of
(214-2) /FCH
MB95100AM Series
66 DS07-12614-6E
Part number Clock mode select Low v olt age detection
reset Clock supervisor Reset output
MB95108AM
Single-system
No No Yes
Yes No Yes
Yes Yes No
Dual-system
No No Yes
Yes No Yes
Yes Yes No
MB95F104AMS
Single-system
No No Yes
MB95F104ANS Yes No Yes
MB95F104AJS Yes Yes No
MB95F106AMS No No Yes
MB95F106ANS Yes No Yes
MB95F106AJS Yes Yes No
MB95F108AMS No No Yes
MB95F108ANS Yes No Yes
MB95F108AJS Yes Yes No
MB95F104AMW
Dual-system
No No Yes
MB95F104ANW Yes No Yes
MB95F104AJW Yes Yes No
MB95F106AMW No No Yes
MB95F106ANW Yes No Yes
MB95F106AJW Yes Yes No
MB95F108AMW No No Yes
MB95F108ANW Yes No Yes
MB95F108AJW Yes Yes No
MB95FV100D-103
Single-system
No No Yes
Yes No Yes
Yes Yes No
Dual-system
No No Yes
Yes No Yes
Yes Yes No
MB95100AM Series
DS07-12614-6E 67
ORDERING INFORMATION
Part number Pa cka ge
MB95108AMPMC1
MB95F104AMSPMC1
MB95F104ANSPMC1
MB95F104AJSPMC1
MB95F104AMWPMC1
MB95F104ANWPMC1
MB95F104AJWPMC1
MB95F106AMSPMC1
MB95F106ANSPMC1
MB95F106AJSPMC1
MB95F106AMWPMC1
MB95F106ANWPMC1
MB95F106AJWPMC1
MB95F108AMSPMC1
MB95F108ANSPMC1
MB95F108AJSPMC1
MB95F108AMWPMC1
MB95F108ANWPMC1
MB95F108AJWPMC1
64-pin plastic LQFP
(FPT-64P-M24)
MB95108AMPMC
MB95F104AMSPMC
MB95F104ANSPMC
MB95F104AJSPMC
MB95F104AMWPMC
MB95F104ANWPMC
MB95F104AJWPMC
MB95F106AMSPMC
MB95F106ANSPMC
MB95F106AJSPMC
MB95F106AMWPMC
MB95F106ANWPMC
MB95F106AJWPMC
MB95F108AMSPMC
MB95F108ANSPMC
MB95F108AJSPMC
MB95F108AMWPMC
MB95F108ANWPMC
MB95F108AJWPMC
64-pin plastic LQFP
(FPT-64P-M23)
MB2146-303A-E (MB95FV100D-103PBT) MCU board
()
224-pin plastic PFBGA
(BGA-224P-M08)
MB95100AM Series
68 DS07-12614-6E
PACKAGE DIMENSIONS
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/ (Continued)
64-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 10.0 × 10.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 0.32 g
Code
(Reference) P-LFQFP64-10×10-0.50
64-pin plastic LQFP
(FPT-64P-M24)
(FPT-64P-M24)
LEAD No.
Details of "A" part
0.25(.010)
(Stand off)
(.004±.004)
0.10±0.10
(.024±.006)
0.60±0.15
(.020±.008)
0.50±0.20
1.50 +0.20
–0.10
+.008
–.004
.059
0˚~8˚
"A"
0.08(.003)
(.006±.002)
0.145±0.055
0.08(.003)M
(.008±.002)
0.20±0.05
0.50(.020)
12.00±0.20(.472±.008)SQ
10.00±0.10(.394±.004)SQ
INDEX
49
64
3348
17
32
161
2005 FUJITSU LIMITED F64036S-c-1-1
C
(Mounting height)
*
Dimensions in mm (inc hes).
Note: The values in parentheses are reference values
©2005-2008 FUJITSU MICROELECTRONICS LIMITED F64036S-c-1-2
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
MB95100AM Series
DS07-12614-6E 69
(Continued)
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
64-pin plastic LQFP Lead pitch 0.65 mm
Package width ×
package length 12.0 × 12.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference) P-LFQFP64-12×12-0.65
64-pin plastic LQFP
(FPT-64P-M23)
(FPT-64P-M23)
C
2003 FUJITSU LIMITED F64034S-c-1-1
0.65(.026)
0.10(.004)
116
17
3249
64
3348
*12.00±0.10(.472±.004)SQ
14.00±0.20(.551±.008)SQ
INDEX
0.32±0.05
(.013±.002) M
0.13(.005)
0.145±0.055
(.0057±.0022)
"A"
.059 .004
+.008
0.10
+0.20
1.50
0~8˚
0.25(.010)
(Mounting height)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
Dimensions in mm (inc hes).
Note: The values in parentheses are reference values
©2003-2008 FUJITSU MICROELECTRONICS LIMITED F64034S-c-1-2
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
MB95100AM Series
70 DS07-12614-6E
MAIN CHANGES IN THIS EDITION
The vertical lines marked in the left side of the page show the changes.
Page Section Chang e Re su lt s
4 PRODUCT LINEUP Corrected “Reset output” in MB95108AM t o “Yes/No”.
MB95100AM Series
DS07-12614-6E 71
MEMO
MB95100AM Series
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