FUJITSU MICROELECTRONICS DATA SHEET DS07-12614-6E 8-bit Proprietary Microcontrollers CMOS F2MC-8FX MB95100AM Series MB95108AM/F104AMS/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/ MB95F108AMS/F108ANS/F108AJS/F104AMW/F104ANW/F104AJW/F106AMW/ MB95F106ANW/F106AJW/F108AMW/F108ANW/F108AJW/FV100D-103 DESCRIPTION The MB95100AM series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. FEATURE * F2MC-8FX CPU core Instruction set optimized for controllers * Multiplication and division instructions * 16-bit arithmetic operations * Bit test branch instruction * Bit manipulation instructions etc. * Clock * Main clock * Main PLL clock * Sub clock (for dual clock product) * Sub PLL clock (for dual clock product) (Continued) For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ Copyright(c)2006-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.11 MB95100AM Series (Continued) * Timer * 8/16-bit compound timer x 2 channels * 16-bit reload timer * 8/16-bit PPG x 2 channels * 16-bit PPG x 2 channels * Timebase timer * Watch prescaler (for dual clock product) * LIN-UART * Full duplex double buffer * Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable * UART/SIO * Full duplex double buffer * Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable * I2C Built-in wake-up function * External interrupt * Interrupt by edge detection (rising, falling, or both edges can be selected) * Can be used to recover from low-power consumption (standby) modes. * 8/10-bit A/D converter * 8-bit or 10-bit resolution can be selected * Low-power consumption (standby) mode * Stop mode * Sleep mode * Watch mode (for dual clock product) * Timebase timer mode * I/O ports : * The number of maximum ports * Single clock product : 54 ports * Dual clock product : 52 ports * Port configuration * General-purpose I/O ports (N-ch open drain) : 6 ports * General-purpose I/O ports (CMOS) : Single clock product : 48 ports Dual clock product : 46 ports * Programmable input voltage levels of port Automotive input level / CMOS input level / hysteresis input level * Flash memory security function Protects the content of Flash memory (Flash memory device only) 2 DS07-12614-6E MB95100AM Series MEMORY LINEUP MB95F104AMS/F104ANS/F104AJS MB95F104AMW/F104ANW/F104AJW MB95F106AMS/F106ANS/F106AJS MB95F106AMW/F106ANW/F106AJW MB95F108AMS/F108ANS/F108AJS MB95F108AMW/F108ANW/F108AJW DS07-12614-6E Flash RAM 16K bytes 512 bytes 32K bytes 1K byte 60K bytes 2K bytes 3 MB95100AM Series PRODUCT LINEUP Part number MB95 108AM Parameter Type MB95F 104AMS/ MB95F 106AMS/ MB95F 108AMS MB95F 104ANS/ MB95F 106ANS/ MB95F 108ANS MB95F MB95F 104AMW/ 104ANW/ MB95F MB95F 106AMW/ 106ANW/ MB95F MB95F 108AMW 108ANW MASK ROM product Flash memory product ROM capacity*1 60 Kbytes (Max) RAM capacity*1 2 Kbytes (Max) Option*2 Reset output Selectable single/dual clock*3 Low voltage detection reset Yes/No Clock supervisor CPU functions Peripheral functions Yes/No Clock system MB95F 104AJW/ MB95F 106AJW/ MB95F 108AJW MB95F 104AJS/ MB95F 106AJS/ MB95F 108AJS No Yes Single clock No Yes Dual clock No Single clock Dual clock Yes No Yes Number of basic instructions : 136 Instruction bit length : 8 bits Instruction length : 1 to 3 bytes Data bit length : 1, 8, and 16 bits Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz) Interrupt processing time : 0.6 s (at machine clock frequency 16.25 MHz) General-purpose I/O ports * Single clock product : 54 ports (N-ch open drain : 6 ports, CMOS : 48 ports) * Dual clock product : 52 ports (N-ch open drain : 6 ports, CMOS : 46 ports) Programmable input voltage levels of port : Automotive input level / CMOS input level / hysteresis input level Timebase timer Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz) Watchdog timer Reset generated cycle At main oscillation clock 10 MHz : Min 105 ms At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms Wild register Capable of replacing 3 bytes of ROM data 2 IC Master/slave sending and receiving Bus error function and arbitration function Detecting transmitting direction function Start condition repeated generation and detection functions Built-in wake-up function UART/SIO Data transfer capable in UART/SIO Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator NRZ type transfer format, error detected function LSB-first or MSB-first can be selected. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable (Continued) 4 DS07-12614-6E MB95100AM Series Part number MB95 108AM Peripheral functions Parameter MB95F 104AMS/ MB95F 106AMS/ MB95F 108AMS MB95F MB95F MB95F 104ANS/ 104AMW/ 104ANW/ MB95F MB95F MB95F 106ANS/ 106AMW/ 106ANW/ MB95F MB95F MB95F 108ANS 108AMW 108ANW MB95F 104AJS/ MB95F 106AJS/ MB95F 108AJS MB95F 104AJW/ MB95F 106AJW/ MB95F 108AJW LIN-UART Dedicated reload timer allowing a wide range of communication speeds to be set. Full duplex double buffer Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable LIN functions available as the LIN master or LIN slave. 8/10-bit A/D converter (12 channels) 8-bit or 10-bit resolution can be selected. 16-bit reload timer Two clock modes and two counter operating modes can be selected. Square waveform output Count clock : 7 internal clocks and external clock can be selected. Counter operating mode : reload mode or one-shot mode can be selected. 8/16-bit compound timer (2 channels) Each channel of the timer can be used as "8-bit timer x 2 channels" or "16-bit timer x 1 channel". Built-in timer function, PWC function, PWM function, capture function, and square waveform output Count clock : 7 internal clocks and external clock can be selected 16-bit PPG (2 channels) PWM mode or one-shot mode can be selected. Counter operating clock : 8 selectable clock sources Support for external trigger start 8/16-bit PPG (2 channels) Each channel of the PPG can be used as "8-bit PPG x 2 channels" or "16-bit PPG x 1 channel". Counter operating clock : Eight selectable clock sources Watch counter Count clock : 4 selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s) (for dual clock product) Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting clock source 1 second and setting counter value to 60) Watch prescaler 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) (for dual clock product) External interrupt (12 channels) Interrupt by edge detection (rising, falling, or both edges can be selected.) Can be used to recover from standby modes. Flash memory Supports automatic programming, Embedded Algorithm Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of write/erase cycles (Minimum) : 10000 times Data retention time : 20 years Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash (MB95F108AMS/F108ANS/F108AJS/F108AMW/F108ANW/F108AJW only) Standby mode Sleep, stop, watch (for dual clock product) , and timebase timer (Continued) DS07-12614-6E 5 MB95100AM Series (Continued) *1 : For ROM capacity and RAM capacity, refer to " MEMORY LINEUP". *2 : For details of option, refer to " MASK OPTION". *3 : Specify clock mode when ordering MASK ROM. Note : Part number of the evaluation product in MB95100AM series is MB95FV100D-103. When using it, the MCU board MB2146-303A-E is required. OSCILLATION STABILIZATION WAIT TIME The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum value is shown as follows. Oscillation stabilization wait time Remarks (214-2) /FCH Approx. 4.10 ms (at main oscillation clock 4 MHz) PACKAGES AND CORRESPONDING PRODUCTS Part number Parameter MB95F104AMS/F104ANS/ F104AJS MB95F106AMS/F106ANS/ MB95108AM F106AJS MB95F108AMS/F108ANS/ F108AJS MB95F104AMW/F104ANW/ F104AJW MB95F106AMW/F106ANW/ MB95FV100D-103 F106AJW MB95F108AMW/F108ANW/ F108AJW FPT-64P-M24 FPT-64P-M23 BGA-224PM08 : Available : Unavailable 6 DS07-12614-6E MB95100AM Series DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS * Notes on Using Evaluation Products The Evaluation product has not only the functions of the MB95100AM series but also those of other products to support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for peripheral resources not used by the MB95100AM series are therefore access-barred. Read/write access to these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are used, the address may be read or write unexpectedly) . Also, as the read values of prohibited addresses on the evaluation product are different to the values on the flash memory and MASK ROM products, do not use these values in the program. The Evaluation product do not support the functions of some bits in single-byte registers. Read/write access to these bits does not cause hardware malfunctions. Since the Evaluation, Flash memory, and MASK ROM products are designed to behave completely the same way in terms of hardware and software. * Difference of Memory Spaces If the amount of memory on the Evaluation product is different from that of the Flash memory or MASK ROM product, carefully check the difference in the amount of memory from the model to be actually used when developing software. For details of memory space, refer to " CPU CORE". * Current Consumption The current consumption of Flash memory product is typically greater than for MASK ROM product. For details of current consumption, refer to " ELECTRICAL CHARACTERISTICS". * Package For details of information on each package, refer to " PACKAGES AND CORRESPONDING PRODUCTS" and " PACKAGE DIMENSIONS". * Operating Voltage The operating voltage are different among the Evaluation, Flash memory, and MASK ROM products. For details of operating voltage, refer to " ELECTRICAL CHARACTERISTICS". * Difference between RST and MOD Pins The RST and MOD pins are hysteresis inputs on the MASK ROM product. A pull-down resistor is provided for the MOD pin of the MASK ROM product. DS07-12614-6E 7 MB95100AM Series PIN ASSIGNMENT AVss P30/AN00 P31/AN01 P32/AN02 P33/AN03 P34/AN04 P35/AN05 P36/AN06 P37/AN07 P40/AN08 P41/AN09 P42/AN10 P43/AN11 P67/SIN P66/SOT P65/SCK (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVcc AVR PE3/INT13 PE2/INT12 PE1/INT11 PE0/INT10 P83 P82 P81 P80 P71/TI0 P70/TO0 MOD X0 X1 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P64/EC1 P63/TO11 P62/TO10 P61/PPG11 P60/PPG10 P53/TRG1 P52/PPG1 P51/SDA0 P50/SCL0 P24/EC0 P23/TO01 P22/TO00 P21/PPG01 P20/PPG00 P14/PPG0 P13/TRG0/ADTG Vcc C PG2/X1A PG1/X0A RST P00/INT00 P01/INT01 P02/INT02 P03/INT03 P04/INT04 P05/INT05 P06/INT06 P07/INT07 P10/UI0 P11/UO0 P12/UCK0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (FPT-64P-M24, FPT-64P-M23) * : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin. 8 DS07-12614-6E MB95100AM Series PIN DESCRIPTION Pin no. Pin name I/O Circuit type* 1 AVcc A/D converter power supply pin 2 AVR A/D converter reference input pin 3 PE3/INT13 4 PE2/INT12 5 PE1/INT11 6 PE0/INT10 7 P83 8 P82 9 P81 10 P80 11 P71/TI0 12 P70/TO0 13 MOD 14 X0 15 X1 16 Vss Power supply pin (GND) 17 Vcc Power supply pin 18 C Capacitor connection pin 19 PG2/X1A 20 PG1/X0A 21 RST 22 P00/INT00 23 P01/INT01 24 P02/INT02 25 P03/INT03 26 P04/INT04 27 P05/INT05 28 P06/INT06 29 P07/INT07 30 P10/UI0 Function General-purpose I/O port. The pins are shared with the external interrupt input. P General-purpose I/O port O H B A H/A B' General-purpose I/O port. The pin is shared with 16-bit reload timer ch.0 input. General-purpose I/O port. The pin is shared with 16-bit reload timer ch.0 output. An operating mode designation pin Main clock input oscillation pin Main clock input/output oscillation pin Single clock product is general-purpose port (PG2) . Dual clock product is sub clock input/output oscillation pin (32 kHz). Single clock product is general-purpose port (PG1) . Dual clock product is sub clock input oscillation pin (32 kHz). Reset pin General-purpose I/O port. The pins are shared with external interrupt input. Large current port. C G General-purpose I/O port. The pin is shared with UART/SIO ch.0 data input. (Continued) DS07-12614-6E 9 MB95100AM Series I/O Circuit type* Pin no. Pin name Function 31 P11/UO0 32 P12/UCK0 33 P13/TRG0/ ADTG 34 P14/PPG0 35 P20/PPG00 36 P21/PPG01 37 P22/TO00 38 P23/TO01 39 P24/EC0 General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.0 clock input. 40 P50/SCL0 General-purpose I/O port. The pin is shared with I2C ch.0 clock I/O. General-purpose I/O port. The pin is shared with UART/SIO ch.0 data output. General-purpose I/O port. The pin is shared with UART/SIO ch.0 clock I/O. H General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D trigger input (ADTG). General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 output. General-purpose I/O port. The pins are shared with 8/16-bit PPG ch.0 output. H I General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch.0 output. 41 P51/SDA0 General-purpose I/O port. The pin is shared with I2C ch.0 data I/O. 42 P52/PPG1 General-purpose I/O port. The pin is shared with 16-bit PPG ch.1 output. H General-purpose I/O port. The pin is shared with 16-bit PPG ch.1 trigger input. 43 P53/TRG1 44 P60/PPG10 45 P61/PPG11 46 P62/TO10 47 P63/TO11 48 P64/EC1 49 P65/SCK General-purpose I/O port. The pin is shared with LIN-UART clock I/O. 50 P66/SOT General-purpose I/O port. The pin is shared with LIN-UART data output. 51 P67/SIN 52 P43/AN11 53 P42/AN10 54 P41/AN09 55 P40/AN08 General-purpose I/O port. The pins are shared with 8/16-bit PPG ch.1 output. General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch.1 output. K L General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.1 clock input. General-purpose I/O port. The pin is shared with LIN-UART data input. General-purpose I/O port. The pins are shared with A/D converter analog input. J (Continued) 10 DS07-12614-6E MB95100AM Series (Continued) Pin no. Pin name 56 P37/AN07 57 P36/AN06 58 P35/AN05 59 P34/AN04 60 P33/AN03 61 P32/AN02 62 P31/AN01 63 P30/AN00 64 AVss I/O Circuit type* Function General-purpose I/O port. The pins are shared with A/D converter analog input. J A/D converter power supply pin (GND) *: For the I/O circuit type, refer to " I/O CIRCUIT TYPE" DS07-12614-6E 11 MB95100AM Series I/O CIRCUIT TYPE Type Circuit Remarks Clock input X1 (X1A) A N-ch X0 (X0A) * Oscillation circuit * High-speed side Feedback resistance : approx. 1 M * Low-speed side Feedback resistance : approx. 10 M Standby control Mode input B R * Hysteresis input only for MASK ROM product * Reset output Reset input B' N-ch Reset output P-ch * Only for input Hysteresis input only for MASK ROM product With pull-down resistor only for MASK ROM product Digital output Digital output * CMOS output * Hysteresis input * Automotive input N-ch C Hysteresis input Automotive input Standby control External interrupt enable R P-ch Pull-up control P-ch G N-ch Digital output Digital output * * * * * CMOS output CMOS input Hysteresis input With pull-up control Automotive input CMOS input Hysteresis input Standby control Automotive input (Continued) 12 DS07-12614-6E MB95100AM Series Type Circuit Remarks Pull-up control R P-ch P-ch H Digital output * * * * CMOS output Hysteresis input With pull-up control Automotive input * * * * N-ch open drain output CMOS input Hysteresis input Automotive input * * * * * CMOS output Hysteresis input Analog input With pull-up control Automotive input Digital output N-ch Hysteresis input Automotive input Standby control N-ch Digital output CMOS input I Hysteresis input Automotive input Standby control R P-ch Pull-up control P-ch N-ch J Digital output Digital output Analog input Hysteresis input A/D control Standby control Automotive input P-ch K N-ch Digital output Digital output * CMOS output * Hysteresis input * Automotive input Hysteresis input Standby control Automotive input (Continued) DS07-12614-6E 13 MB95100AM Series (Continued) Type Circuit P-ch N-ch Remarks Digital output Digital output * * * * CMOS output CMOS input Hysteresis input Automotive input L CMOS input Hysteresis input Automotive input Standby control N-ch Digital output * N-ch open drain output * Hysteresis input * Automotive input Hysteresis input O Automotive input Standby control Pull-up control R P-ch P-ch P N-ch Digital output * * * * CMOS output Hysteresis input With pull-up control Automotive input Digital output Hysteresis input Automotive input Standby control External interrupt control 14 DS07-12614-6E MB95100AM Series HANDLING DEVICES * Preventing Latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC pin and VSS pin. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. Also, take care to prevent the analog power supply voltage (AVCC, AVR) and analog input voltage from exceeding the digital power supply voltage (VCC) when the analog system power supply is turned on or off. * Stable Supply Voltage Supply voltage should be stabilized. A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the Vcc power-supply voltage. For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range (50 Hz/60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched. * Precautions for Use of External Clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from sub clock mode or stop mode. * Serial communication There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error occurs. PIN CONNECTION * Treatment of Unused Input Pin Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open. * Treatment of Power Supply Pins on A/D Converter Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use. Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 F ceramic capacitor as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device. DS07-12614-6E 15 MB95100AM Series * Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC and VSS near this device. * Mode Pin (MOD) Connect the MOD pin directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the MOD pins to VCC or VSS pins and to provide a low-impedance connection. Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram below. * C pin connection diagram C CS * Analog Power Supply Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00 to AN11 pins. 16 DS07-12614-6E MB95100AM Series PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER * Supported Parallel Programmers and Adapters The following table lists supported parallel programmers and adapters. Package Applicable adapter model FPT-64P-M24 TEF110-108F35AP FPT-64P-M23 TEF110-108F36AP Parallel programmers AF9708 (Ver 02.35G or more) AF9709/B (Ver 02.35G or more) AF9723+AF9834 (Ver 02.08E or more) Note : For information on applicable adapter models and parallel programmers, contact the following: Flash Support Group, Inc. TEL: +81-53-428-8380 * Sector Configuration The individual sectors of Flash memory correspond to addresses used for CPU access and programming by the parallel programmer as follows: * MB95F108AMS/F108ANS/F108AJS/F108AMW/F108ANW/F108AJW (60 Kbytes) Flash memory CPU address Programmer address* 1000H 71000H 1FFFH 2000H 71FFFH 72000H 2FFFH 3000H 72FFFH 73000H 3FFFH 4000H 73FFFH 74000H 7FFFH 8000H 77FFFH 78000H BFFFH C000H 7BFFFH 7C000H CFFFH D000H 7CFFFH 7D000H DFFFH E000H 7DFFFH 7E000H EFFFH F000H 7EFFFH 7F000H FFFFH 7FFFFH SA2 (4 Kbytes) Lower bank SA1 (4 Kbytes) SA3 (4 Kbytes) SA4 (16 Kbytes) SA6 (4 Kbytes) SA7 (4 Kbytes) Upper bank SA5 (16 Kbytes) SA8 (4 Kbytes) SA9 (4 Kbytes) *: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. * Programming Method 1) Set the type code of the parallel programmer to "17222". 2) Load program data to programmer addresses 71000H to 7FFFFH. 3) Programmed by parallel programmer DS07-12614-6E 17 MB95100AM Series * MB95F106AMS/F106ANS/F106AJS/F106AMW/F106ANW/F106AJW (32 Kbytes) Flash memory CPU address 8000H Programmer address* 78000H BFFFH C000H 7BFFFH 7C000H CFFFH D000H 7CFFFH 7D000H DFFFH E000H 7DFFFH 7E000H EFFFH F000H 7EFFFH 7F000H FFFFH 7FFFFH SA5 (16 Kbytes) SA6 (4 Kbytes) SA7 (4 Kbytes) SA8 (4 Kbytes) SA9 (4 Kbytes) *: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. * Programming Method 1) Set the type code of the parallel programmer to "17222" 2) Load program data to programmer addresses 78000H to 7FFFFH. 3) Programmed by parallel programmer * MB95F104AMS/F104ANS/F104AJS/F104AMW/F104ANW/F104AJW (16 Kbytes) Flash memory CPU address C000H Programmer address* 7C000H CFFFH D000H 7CFFFH 7D000H DFFFH E000H 7DFFFH 7E000H EFFFH F000H 7EFFFH 7F000H FFFFH 7FFFFH SA6 (4 Kbytes) SA7 (4 Kbytes) SA8 (4 Kbytes) SA9 (4 Kbytes) *: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. * Programming Method 1) Set the type code of the parallel programmer to "17222" 2) Load program data to programmer addresses 7C000H to 7FFFFH. 3) Programmed by parallel programmer 18 DS07-12614-6E MB95100AM Series BLOCK DIAGRAM 2 F MC-8FX CPU RST X0,X1 PG2/X1A* PG1/X0A* Reset control ROM RAM Clock control Interrupt control Watch prescaler Wild register Watch counter P00/INT00 to P07/INT07 External interrupt ch.0 to ch.7 8/16-bit PPG ch.1 P10/UI0 P11/UO0 8/16-bit compound timer ch.1 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 8/16-bit PPG ch.0 8/16-bit compound timer ch.0 Internal bus P14/PPG0 16-bit PPG ch.0 P61/PPG11 P62/TO10 UART/SIO P12/UCK0 P13/TRG0/ADTG P60/PPG10 P63/TO11 P64/EC1 P65/SCK LIN-UART P66/SOT P67/SIN 16-bit reload timer P70/TO0 P71/TI0 P80 to P83 P24/EC0 P30/AN00 to P37/AN07 External interrupt ch.8 to ch.11 PE0/INT10 to PE3/INT13 P40/AN08 to P43/AN11 AVCC AVSS 8/10-bit A/D converter AVR P50/SCL0 P51/SDA0 P52/PPG1 P53/TRG1 I 2C 16-bit PPG ch.1 Port Port Other pins MOD, VCC, VSS, C * : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin. DS07-12614-6E 19 MB95100AM Series CPU CORE 1. Memory space Memory space of the MB95100AM series is 64 Kbytes and consists of I/O area, data area, and program area. The memory space includes special-purpose areas such as the general-purpose registers and vector table. Memory map of the MB95100AM series is shown below. * Memory Map MB95108AM MB95F104AMS/F104ANS/F104AJS MB95F106AMS/F106ANS/F106AJS MB95F108AMS/F108ANS/F108AJS MB95F104AMW/F104ANW/F104AJW MB95F106AMW/F106ANW/F106AJW MB95F108AMW/F108ANW/F108AJW 0000H 0000H I/O I/O 0080H 0100H RAM 2 Kbytes Register 0200H 0880H 0F80H Access prohibited 0080H RAM 0100H Register 0200H Address #1 0F80H Extension I/O Extension I/O MASK ROM 60 Kbytes FFFFH 20 0000H I/O 0080H RAM 3.75 Kbytes 0100H Register 0200H Access prohibited Address #2 1000H MB95FV100D-103 0F80H 1000H Flash memory 60 Kbytes Flash memory FFFFH Extension I/O FFFFH DS07-12614-6E MB95100AM Series MB95F104AMS/F104ANS/F104AJS MB95F104AMW/F104ANW/F104AJW MB95F106AMS/F106ANS/F106AJS MB95F106AMW/F106ANW/F106AJW MB95F108AMS/F108ANS/F108AJS MB95F108AMW/F108ANW/F108AJW DS07-12614-6E Flash RAM Address #1 Address #2 16 Kbytes 512 bytes 0280H C000H 32 Kbytes 1 Kbyte 0480H 8000H 60 Kbytes 2 Kbytes 0880H 1000H 21 MB95100AM Series 2. Register The MB95100AM series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The dedicated registers are as follows: Program counter (PC) : A 16-bit register to indicate locations where instructions are stored. Accumulator (A) : A 16-bit register for temporary storage of arithmetic operations. In the case of an 8-bit data processing instruction, the lower one byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator. In the case of an 8-bit data processing instruction, the lower one byte is used. Index register (IX) : A 16-bit register for index modification. Extra pointer (EP) : A 16-bit pointer to point to a memory address. Stack pointer (SP) : A 16-bit register to indicate a stack area. Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register. Initial Value 16-bit : Program counter FFFDH A : Accumulator 0000H T : Temporary accumulator 0000H IX : Index register 0000H EP : Extra pointer 0000H SP : Stack pointer 0000H PS : Program status 0030H PC The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer (DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.) * Structure of the Program Status bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 PS R4 R3 R2 RP 22 R1 R0 DP2 DP1 DP bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DP0 H I IL1 IL0 N Z V C CCR DS07-12614-6E MB95100AM Series The RP indicates the address of the register bank currently being used. The relationship between the content of RP and the real address conforms to the conversion rule illustrated below: * Rule for Conversion of Actual Addresses in the General-purpose Register Area RP upper "0" Generated address "0" "0" "0" "0" "0" A15 A14 A13 A12 A11 A10 OP code lower "0" "1" R4 R3 R2 R1 R0 b2 b1 b0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct addresses to 0080H to 00FFH. Direct bank pointer (DP2 to DP0) Specified address area Mapping area XXXB (no effect to mapping) 0000H to 007FH 0000H to 007FH (without mapping) 000B (initial value) 0080H to 00FFH (without mapping) 001B 0100H to 017FH 010B 0180H to 01FFH 011B 0080H to 00FFH 100B 0200H to 027FH 0280H to 02FFH 101B 0300H to 037FH 110B 0380H to 03FFH 111B 0400H to 047FH The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at interrupt. H flag : Set to "1" when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to "0" otherwise. This flag is for decimal adjustment instructions. I flag : Interrupt is enabled when this flag is set to "1". Interrupt is disabled when this flag is set to "0". The flag is set to "0" when reset. IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level Priority 0 0 0 High 0 1 1 1 0 2 1 1 3 Low = no interruption N flag : Set to "1" if the MSB is set to "1" as the result of an arithmetic operation. Cleared to "0" when the Z flag V flag : Set to "1" when an arithmetic operation results in "0". Cleared to "0" otherwise. : Set to "1" if the complement on 2 overflows as a result of an arithmetic operation. Cleared to "0" C flag : Set to "1" when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared bit is set to "0". otherwise. to "0" otherwise. Set to the shift-out value in the case of a shift instruction. DS07-12614-6E 23 MB95100AM Series The following general-purpose registers are provided: General-purpose registers: 8-bit data storage registers The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8registers. Up to a total of 32 banks can be used on the MB95100AM series. The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0) to general-purpose register 7 (R7). * Register Bank Configuration 8-bit 1F8H This address = 0100H + 8 x (RP) Address 100H R0 R0 R0 R1 R2 R3 R4 R5 107H R6 R1 R2 R3 R4 R5 R6 R1 R2 R3 R4 R5 R6 1FFH R7 R7 R7 Bank 0 Memory area 24 Bank 31 32 banks 32 banks (RAM area) The number of banks is limited by the usable RAM capacitance. DS07-12614-6E MB95100AM Series I/O MAP Address Register abbreviation Register name R/W Initial value 0000H PDR0 Port 0 data register R/W 00000000B 0001H DDR0 Port 0 direction register R/W 00000000B 0002H PDR1 Port 1 data register R/W 00000000B 0003H DDR1 Port 1 direction register R/W 00000000B 0004H (Disabled) 0005H WATR Oscillation stabilization wait time setting register R/W 11111111B 0006H PLLC PLL control register R/W 00000000B 0007H SYCC System clock control register R/W 1010X011B 0008H STBC Standby control register R/W 00000000B 0009H RSRR Reset source register R/W XXXXXXXXB 000AH TBTC Timebase timer control register R/W 00000000B 000BH WPCR Watch prescaler control register R/W 00000000B 000CH WDTC Watchdog timer control register R/W 00000000B 000DH (Disabled) 000EH PDR2 Port 2 data register R/W 00000000B 000FH DDR2 Port 2 direction register R/W 00000000B 0010H PDR3 Port 3 data register R/W 00000000B 0011H DDR3 Port 3 direction register R/W 00000000B 0012H PDR4 Port 4 data register R/W 00000000B 0013H DDR4 Port 4 direction register R/W 00000000B 0014H PDR5 Port 5 data register R/W 00000000B 0015H DDR5 Port 5 direction register R/W 00000000B 0016H PDR6 Port 6 data register R/W 00000000B 0017H DDR6 Port 6 direction register R/W 00000000B 0018H PDR7 Port 7 data register R/W 00000000B 0019H DDR7 Port 7 direction register R/W 00000000B 001AH PDR8 Port 8 data register R/W 00000000B 001BH DDR8 Port 8 direction register R/W 00000000B 001CH to 0025H (Disabled) 0026H PDRE Port E data register R/W 00000000B 0027H DDRE Port E direction register R/W 00000000B 0028H, 0029H (Disabled) 002AH PDRG Port G data register R/W 00000000B (Continued) DS07-12614-6E 25 MB95100AM Series Address Register abbreviation Register name R/W Initial value 002BH DDRG Port G direction register R/W 00000000B 002CH (Disabled) 002DH PUL1 Port 1 pull-up register R/W 00000000B 002EH PUL2 Port 2 pull-up register R/W 00000000B 002FH PUL3 Port 3 pull-up register R/W 00000000B 0030H PUL4 Port 4 pull-up register R/W 00000000B 0031H PUL5 Port 5 pull-up register R/W 00000000B 0032H PUL7 Port 7 pull-up register R/W 00000000B 0033H (Disabled) 0034H PULE Port E pull-up register R/W 00000000B 0035H PULG Port G pull-up register R/W 00000000B 0036H T01CR1 8/16-bit compound timer 01 control status register 1 ch.0 R/W 00000000B 0037H T00CR1 8/16-bit compound timer 00 control status register 1 ch.0 R/W 00000000B 0038H T11CR1 8/16-bit compound timer 11 control status register 1 ch.1 R/W 00000000B 0039H T10CR1 8/16-bit compound timer 10 control status register 1 ch.1 R/W 00000000B 003AH PC01 8/16-bit PPG1 control register ch.0 R/W 00000000B 003BH PC00 8/16-bit PPG0 control register ch.0 R/W 00000000B 003CH PC11 8/16-bit PPG1 control register ch.1 R/W 00000000B 003DH PC10 8/16-bit PPG0 control register ch.1 R/W 00000000B 003EH TMCSRH0 16-bit reload timer control status register (Upper byte) ch.0 R/W 00000000B 003FH TMCSRL0 16-bit reload timer control status register (Lower byte) ch.0 R/W 00000000B 0040H, 0041H (Disabled) 0042H PCNTH0 16-bit PPG status control register (Upper byte) ch.0 R/W 00000000B 0043H PCNTL0 16-bit PPG status control register (Lower byte) ch.0 R/W 00000000B 0044H PCNTH1 16-bit PPG status control register (Upper byte) ch.1 R/W 00000000B 0045H PCNTL1 16-bit PPG status control register (Lower byte) ch.1 R/W 00000000B 0046H, 0047H (Disabled) 0048H EIC00 External interrupt circuit control register ch.0/ch.1 R/W 00000000B 0049H EIC10 External interrupt circuit control register ch.2/ch.3 R/W 00000000B 004AH EIC20 External interrupt circuit control register ch.4/ch.5 R/W 00000000B 004BH EIC30 External interrupt circuit control register ch.6/ch.7 R/W 00000000B 004CH EIC01 External interrupt circuit control register ch.8/ch.9 R/W 00000000B 004DH EIC11 External interrupt circuit control register ch.10/ch.11 R/W 00000000B (Continued) 26 DS07-12614-6E MB95100AM Series Address Register abbreviation Register name R/W Initial value 004EH, 004FH (Disabled) 0050H SCR LIN-UART serial control register R/W 00000000B 0051H SMR LIN-UART serial mode register R/W 00000000B 0052H SSR LIN-UART serial status register R/W 00001000B 0053H RDR/TDR LIN-UART reception/transmission data register R/W 00000000B 0054H ESCR LIN-UART extended status control register R/W 00000100B 0055H ECCR LIN-UART extended communication control register R/W 000000XXB 0056H SMC10 UART/SIO serial mode control register 1 ch.0 R/W 00000000B 0057H SMC20 UART/SIO serial mode control register 2 ch.0 R/W 00100000B 0058H SSR0 UART/SIO serial status register ch.0 R/W 00000001B 0059H TDR0 UART/SIO serial output data register ch.0 R/W 00000000B 005AH RDR0 UART/SIO serial input data register ch.0 R 00000000B 005BH to 005FH (Disabled) 0060H IBCR00 I2C bus control register 0 ch.0 R/W 00000000B 0061H IBCR10 I2C bus control register 1 ch.0 R/W 00000000B 0062H IBSR0 I2C bus status register ch.0 R 00000000B I C data register ch.0 R/W 00000000B 0063H 2 IDDR0 2 0064H IAAR0 I C address register ch.0 R/W 00000000B 0065H ICCR0 I2C clock control register ch.0 R/W 00000000B 0066H to 006BH (Disabled) 006CH ADC1 8/10-bit A/D converter control register 1 R/W 00000000B 006DH ADC2 8/10-bit A/D converter control register 2 R/W 00000000B 006EH ADDH 8/10-bit A/D converter data register (Upper byte) R/W 00000000B 006FH ADDL 8/10-bit A/D converter data register (Lower byte) R/W 00000000B 0070H WCSR Watch counter status register R/W 00000000B 0071H (Disabled) 0072H FSR Flash memory status register R/W 000X0000B 0073H SWRE0 Flash memory sector writing control register 0 R/W 00000000B 0074H SWRE1 Flash memory sector writing control register 1 R/W 00000000B 0075H (Disabled) 0076H WREN Wild register address compare enable register R/W 00000000B 0077H WROR Wild register data test setting register R/W 00000000B (Continued) DS07-12614-6E 27 MB95100AM Series Address Register abbreviation Register name R/W Initial value 0078H Mirror of register bank pointer (RP) and direct bank pointer (DP) 0079H ILR0 Interrupt level setting register 0 R/W 11111111B 007AH ILR1 Interrupt level setting register 1 R/W 11111111B 007BH ILR2 Interrupt level setting register 2 R/W 11111111B 007CH ILR3 Interrupt level setting register 3 R/W 11111111B 007DH ILR4 Interrupt level setting register 4 R/W 11111111B 007EH ILR5 Interrupt level setting register 5 R/W 11111111B 007FH (Disabled) 0F80H WRARH0 Wild register address setting register (Upper byte) ch.0 R/W 00000000B 0F81H WRARL0 Wild register address setting register (Lower byte) ch.0 R/W 00000000B 0F82H WRDR0 Wild register data setting register ch.0 R/W 00000000B 0F83H WRARH1 Wild register address setting register (Upper byte) ch.1 R/W 00000000B 0F84H WRARL1 Wild register address setting register (Lower byte) ch.1 R/W 00000000B 0F85H WRDR1 Wild register data setting register ch.1 R/W 00000000B 0F86H WRARH2 Wild register address setting register (Upper byte) ch.2 R/W 00000000B 0F87H WRARL2 Wild register address setting register (Lower byte) ch.2 R/W 00000000B 0F88H WRDR2 Wild register data setting register ch.2 R/W 00000000B 0F89H to 0F91H (Disabled) 0F92H T01CR0 8/16-bit compound timer 01 control status register 0 ch.0 R/W 00000000B 0F93H T00CR0 8/16-bit compound timer 00 control status register 0 ch.0 R/W 00000000B 0F94H T01DR 8/16-bit compound timer 01 data register ch.0 R/W 00000000B 0F95H T00DR 8/16-bit compound timer 00 data register ch.0 R/W 00000000B 0F96H TMCR0 8/16-bit compound timer 00/01 timer mode control register ch.0 R/W 00000000B 0F97H T11CR0 8/16-bit compound timer 11 control status register 0 ch.1 R/W 00000000B 0F98H T10CR0 8/16-bit compound timer 10 control status register 0 ch.1 R/W 00000000B 0F99H T11DR 8/16-bit compound timer 11 data register ch.1 R/W 00000000B 0F9AH T10DR 8/16-bit compound timer 10 data register ch.1 R/W 00000000B 0F9BH TMCR1 8/16-bit compound timer 10/11 timer mode control register ch.1 R/W 00000000B 0F9CH PPS01 8/16-bit PPG1 cycle setting buffer register ch.0 R/W 11111111B 0F9DH PPS00 8/16-bit PPG0 cycle setting buffer register ch.0 R/W 11111111B 0F9EH PDS01 8/16-bit PPG1 duty setting buffer register ch.0 R/W 11111111B 0F9FH PDS00 8/16-bit PPG0 duty setting buffer register ch.0 R/W 11111111B (Continued) 28 DS07-12614-6E MB95100AM Series Address Register abbreviation Register name R/W Initial value 0FA0H PPS11 8/16-bit PPG1 cycle setting buffer register ch.1 R/W 11111111B 0FA1H PPS10 8/16-bit PPG0 cycle setting buffer register ch.1 R/W 11111111B 0FA2H PDS11 8/16-bit PPG1 duty setting buffer register ch.1 R/W 11111111B 0FA3H PDS10 8/16-bit PPG0 duty setting buffer register ch.1 R/W 11111111B 0FA4H PPGS 8/16-bit PPG start register R/W 00000000B 0FA5H REVC 8/16-bit PPG output inversion register R/W 00000000B 0FA6H TMRH0/ TMRLRH0 16-bit timer register (Upper byte) ch.0/ 16-bit reload register (Upper byte) ch.0 R/W 00000000B 0FA7H TMRL0/ TMRLRL0 16-bit timer register (Lower byte) ch.0/ 16-bit reload register (Lower byte) ch.0 R/W 00000000B 0FA8H, 0FA9H (Disabled) 0FAAH PDCRH0 16-bit PPG down counter register (Upper byte) ch.0 R 00000000B 0FABH PDCRL0 16-bit PPG down counter register (Lower byte) ch.0 R 00000000B 0FACH PCSRH0 16-bit PPG cycle setting buffer register (Upper byte) ch.0 R/W 11111111B 0FADH PCSRL0 16-bit PPG cycle setting buffer register (Lower byte) ch.0 R/W 11111111B 0FAEH PDUTH0 16-bit PPG duty setting buffer register (Upper byte) ch.0 R/W 11111111B 0FAFH PDUTL0 16-bit PPG duty setting buffer register (Lower byte) ch.0 R/W 11111111B 0FB0H PDCRH1 16-bit PPG down counter register (Upper byte) ch.1 R 00000000B 0FB1H PDCRL1 16-bit PPG down counter register (Lower byte) ch.1 R 00000000B 0FB2H PCSRH1 16-bit PPG cycle setting buffer register (Upper byte) ch.1 R/W 11111111B 0FB3H PCSRL1 16-bit PPG cycle setting buffer register (Lower byte) ch.1 R/W 11111111B 0FB4H PDUTH1 16-bit PPG duty setting buffer register (Upper byte) ch.1 R/W 11111111B 0FB5H PDUTL1 16-bit PPG duty setting buffer register (Lower byte) ch.1 R/W 11111111B 0FB6H to 0FBBH (Disabled) 0FBCH BGR1 LIN-UART baud rate generator register 1 R/W 00000000B 0FBDH BGR0 LIN-UART baud rate generator register 0 R/W 00000000B 0FBEH PSSR0 UART/SIO dedicated baud rate generator prescaler selection register ch.0 R/W 00000000B 0FBFH BRSR0 UART/SIO dedicated baud rate generator baud rate setting register ch.0 R/W 00000000B 0FC0H, 0FC1H (Disabled) 0FC2H AIDRH A/D input disable register (Upper byte) R/W 00000000B 0FC3H AIDRL A/D input disable register (Lower byte) R/W 00000000B (Continued) DS07-12614-6E 29 MB95100AM Series (Continued) Address Register abbreviation Register name R/W Initial value 0FC4H to 0FE2H (Disabled) 0FE3H WCDR Watch counter data register R/W 00111111B 0FE4H to 0FE6H (Disabled) 0FE7H ILSR2 Input level select register 2 R/W 00000000B 0FE8H, 0FE9H (Disabled) 0FEAH CSVCR Clock supervisor control register R/W 00011100B 0FEBH to 0FEDH (Disabled) 0FEEH ILSR Input level select register R/W 00000000B 0FEFH WICR Interrupt pin control register R/W 01000000B 0FF0H to 0FFFH (Disabled) * R/W access symbols R/W : Readable/Writable R : Read only W : Write only * Initial value symbols 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is undefined. Note : Do not write to the " (Disabled) ". Reading the " (Disabled) " returns an undefined value. 30 DS07-12614-6E MB95100AM Series INTERRUPT SOURCE TABLE Interrupt source Interrupt request number Vector table address Same level Bit name of priority order interrupt level (at simultaneous setting register occurrence) Upper Lower IRQ0 FFFAH FFFBH L00 [1 : 0] IRQ1 FFF8H FFF9H L01 [1 : 0] IRQ2 FFF6H FFF7H L02 [1 : 0] IRQ3 FFF4H FFF5H L03 [1 : 0] UART/SIO ch.0 IRQ4 FFF2H FFF3H L04 [1 : 0] 8/16-bit compound timer ch.0 (Lower) IRQ5 FFF0H FFF1H L05 [1 : 0] 8/16-bit compound timer ch.0 (Upper) IRQ6 FFEEH FFEFH L06 [1 : 0] LIN-UART (reception) IRQ7 FFECH FFEDH L07 [1 : 0] LIN-UART (transmission) IRQ8 FFEAH FFEBH L08 [1 : 0] 8/16-bit PPG ch.1 (Lower) IRQ9 FFE8H FFE9H L09 [1 : 0] 8/16-bit PPG ch.1 (Upper) IRQ10 FFE6H FFE7H L10 [1 : 0] 16-bit reload timer ch.0 IRQ11 FFE4H FFE5H L11 [1 : 0] 8/16-bit PPG ch.0 (Upper) IRQ12 FFE2H FFE3H L12 [1 : 0] 8/16-bit PPG ch.0 (Lower) IRQ13 FFE0H FFE1H L13 [1 : 0] 8/16-bit compound timer ch.1 (Upper) IRQ14 FFDEH FFDFH L14 [1 : 0] 16-bit PPG ch.0 IRQ15 FFDCH FFDDH L15 [1 : 0] I2C ch.0 IRQ16 FFDAH FFDBH L16 [1 : 0] 16-bit PPG ch.1 IRQ17 FFD8H FFD9H L17 [1 : 0] 8/10-bit A/D converter IRQ18 FFD6H FFD7H L18 [1 : 0] Timebase timer IRQ19 FFD4H FFD5H L19 [1 : 0] Watch prescaler/Watch counter IRQ20 FFD2H FFD3H L20 [1 : 0] IRQ21 FFD0H FFD1H L21 [1 : 0] 8/16-bit compound timer ch.1 (Lower) IRQ22 FFCEH FFCFH L22 [1 : 0] Flash memory IRQ23 FFCCH FFCDH L23 [1 : 0] External interrupt ch.0 External interrupt ch.4 External interrupt ch.1 External interrupt ch.5 External interrupt ch.2 External interrupt ch.6 External interrupt ch.3 External interrupt ch.7 High External interrupt ch.8 External interrupt ch.9 External interrupt ch.10 External interrupt ch.11 DS07-12614-6E Low 31 MB95100AM Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Power supply voltage*1 1 Input voltage* Output voltage* 1 Maximum clamp current Total maximum clamp current "L" level maximum output current "L" level average current Rating Vcc AVcc Vss - 0.3 Vss + 6.0 AVR Vss - 0.3 Vss + 6.0 *2 VI Vss - 0.3 Vss + 6.0 *3 VO Vss - 0.3 Vss + 6.0 V ICLAMP - 2.0 + 2.0 mA |ICLAMP| 20 mA IOL1 IOL2 15 15 "H" level maximum output current "H" level average current mA 12 IOL 100 mA IOLAV 50 mA IOH1 IOH2 - 15 - 15 mA -4 IOHAV1 mA -8 IOHAV2 "H" level total average output current V mA "H" level total maximum output current *2 4 IOLAV1 IOLAV2 "L" level total average output current Remarks Max "L" level total maximum output current Unit Min IOH - 100 mA IOHAV - 50 mA *3 Applicable to pins*4 Applicable to pins*4 Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current x operating ratio (1 pin) P00 to P07 Average output current = operating current x operating ratio (1 pin) Total average output current = operating current x operating ratio (Total of pins) Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current x operating ratio (1 pin) P00 to P07 Average output current = operating current x operating ratio (1 pin) Total average output current = operating current x operating ratio (Total of pins) (Continued) 32 DS07-12614-6E MB95100AM Series (Continued) Parameter Symbol Rating Min Max Unit Power consumption Pd 320 mW Operating temperature TA - 40 + 85 C Tstg - 55 + 150 C Storage temperature *1 : The parameter is based on AVSS = VSS = 0.0 V. *2 : Apply equal potential to AVcc and Vcc. AVR should not exceed AVcc + 0.3 V. *3 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P70, P71, PE0 to PE3 * Use within recommended operating conditions. * Use at DC voltage (current). * +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller. * The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this affect other devices. * Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. * Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the + B input pin open. * Sample recommended circuits : * Input/Output Equivalent circuits Protective diode + B input (0 V to 16 V) Vcc Limiting resistance P-ch N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. DS07-12614-6E 33 MB95100AM Series 2. Recommended Operating Conditions (AVss = Vss = 0.0 V) Value SymPin name Conditions bol Parameter Power supply voltage VCC, AVCC A/D converter reference input voltage Min Max 2.42*1 5.5 2.3 5.5 2.7 5.5 2.3 5.5 Unit Remarks At normal operating Other than MB95FV100D-103 Retain status of V stop operation At normal operating MB95FV100D-103 Retain status of stop operation AVR 4.0 AVCC V Smoothing capacitor CS 0.1 1.0 F Operating temperature TA - 40 + 85 +5 + 35 C *2 Other than MB95FV100D-103 MB95FV100D-103 *1 : When the low voltage detection reset is used, reset occurs while the low voltage is detected. For details on Low voltage detection, see "(9) Low Voltage Detection" in "4. AC Characteristics". *2 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram below. * C pin connection diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 34 DS07-12614-6E MB95100AM Series 3. DC Characteristics (Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter "H" level input voltage Symbol Pin name Conditions Value Min Typ Max 0.7 Vcc Vcc + 0.3 P10, P50, P51, P67 VIH *1 VIHA P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, P60 to P67, P70, P71, P80 to P83, PE0 to PE3, PG1*2, PG2*2 VIHS P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, P60 to P67, P70, P71, P80 to P83, PE0 to PE3, PG1*2, PG2*2 0.8 VCC VCC + 0.3 Unit V V "L" level input voltage *1 VILA P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, P60 to P67, P70, P71, P80 to P83, PE0 to PE3, PG1*2, PG2*2 VILS P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, P60 to P67, P70, P71, P80 to P83, PE0 to PE3, PG1*2, PG2*2 0.8 Vcc Vcc + 0.3 V 0.7 Vcc Vcc + 0.3 V *1 Vss - 0.3 0.3 Vcc V Hysteresis input of CMOS input level VSS - 0.3 0.5 VCC V Pin input at selecting of Automotive input level Hysteresis input *1 Vss - 0.3 0.2 Vcc V RST, MOD VILM Pin input at selecting of Automotive input level CMOS input (MASK ROM product is hysteresis input) P10, P50, P51, P67 VIL Hysteresis input of CMOS input level Hysteresis input RST, MOD VIHM Remarks Vss - 0.3 0.3 Vcc V CMOS input (MASK ROM product is hysteresis input) (Continued) DS07-12614-6E 35 MB95100AM Series (Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Open-drain output application voltage Symbol VD Pin name P50, P51, P80 to P83 Output pin other than "H" level output VOH1 P00 to P07 voltage VOH2 P00 to P07 Output pin other than "L" level output VOL1 P00 to P07, RST*3 voltage VOL2 P00 to P07 Input leakage current (Hi-Z output leakage current) Open-drain output leakage current ILI P50, P51, ILIOD P80 to P83 Pull-up resistor RPULL Pull-down resistor Input capacitance Port other than P50, P51, P80 to P83 RMOD CIN Power supply current*4 MOD Value Unit Min Typ Max Vss - 0.3 Vss + 5.5 V IOH = - 4.0 mA VCC - 0.5 V IOH = - 8.0 mA VCC - 0.5 V 0.4 V 0.4 V IOL = 4.0 mA IOL = 12 mA 0.0 V < VI < Vcc 0.0 V < VI < Vss + 5.5 V P10 to P14,P20 to P24, VI = 0.0 V P30 to P37, P40 to P43, P52, P53, P70, P71, PE0 to PE3, PG1*2, PG2*2 VI = Vcc Other than AVcc, AVss, f = 1 MHz AVR, Vcc, Vss Vcc (External clock operation) ICC Conditions VCC = 5.5 V FCH = 20 MHz FMP = 10 MHz Main clock mode (divided by 2) FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) -5 +5 A 5 A Remarks When the pull-up prohibition setting When the pull-up permission setting 25 50 100 k 25 50 100 k 5 15 pF 9.5 12.5 Flash memory product mA (At other than writing and erasing) 30 35 Flash memory product mA (At writing and erasing) 7.2 9.5 mA MASK ROM product 15.2 20.0 Flash memory product mA (At other than writing and erasing) 35.7 42.5 Flash memory product mA (At writing and erasing) 11.6 15.2 mA MASK ROM product MASK ROM product (Continued) 36 DS07-12614-6E MB95100AM Series (Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C ) Parameter Symbol Power supply current*4 Pin name Vcc (External clock operation) ICCS Conditions Typ Max VCC = 5.5 V FCH = 20 MHz FMP = 10 MHz Main sleep mode (divided by 2) 4.5 7.5 mA FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) 7.2 12.0 mA ICCL ICCLS VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Sub sleep mode (divided by 2) , TA = + 25 C ICCT VCC = 5.5 V FCL = 32 kHz Watch mode Main stop mode TA = + 25 C VCC = 5.5 V FCH = 4 MHz FMP = 10 MHz Main PLL mode (multiplied by 2.5) FCH = 6.4 MHz FMP = 16 MHz Main PLL mode (multiplied by 2.5) ICCSPLL Unit Min VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Sub clock mode (divided by 2) , TA = + 25 C ICCMPLL Value VCC = 5.5 V FCL = 32 kHz FMPL = 128 kHz Sub PLL mode (multiplied by 4) , TA = + 25 C Remarks Dual clock product only 45 100 A Dual clock product only 10 81 A Dual clock product only 4.6 27.0 A 9.3 12.5 mA 7.0 9.5 MASK ROM mA product 14.9 20.0 mA Flash memory product 11.2 15.2 mA MASK ROM product Flash memory product Dual clock product only 160 400 A (Continued) DS07-12614-6E 37 MB95100AM Series (Continued) Parameter Power supply current*4 (Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Symbol Pin name Conditions Value Unit Min Typ Max VCC = 5.5 V FCH = 10 MHz Timebase timer mode TA = + 25 C 0.15 1.10 mA VCC = 5.5 V Sub stop mode TA = + 25 C 3.5 20 A ILVD Current consumption for low voltage detection circuit only 38 50 A ICSV At oscillating 100 kHz current consumption of internal CR oscillator 20 36 A IA VCC = 5.5 V FCH = 16 MHz At operating of A/D conversion 2.4 4.7 mA IAH VCC = 5.5 V FCH = 16 MHz At stopping A/D conversion TA = + 25 C 1 5 A ICTS VCC (External clock operation) ICCH VCC AVcc Remarks Main stop mode for single clock product *1 : P10, P50, P51, and P67 can switch the input level to either the "CMOS input level" or "hysteresis input level". The switching of the input level can be set by the input level selection register (ILSR). *2 : Single clock products only *3 : Product without clock supervisor only *4 : * The power-supply current is determined by the external clock. When the low voltage detection option is selected, the power-supply current will be a value of adding current consumption of the low voltage detection circuit (ILVD) to the specified value. Also, when both low voltage detection option and clock supervisor are selected, the power-supply current will be a value of adding current consumption of the low voltage detection circuit (ILVD) and current consumption of internal CR oscillator (ICSV) to the specified value. * Refer to "4. AC Characteristics (1) Clock Timing" for FCH and FCL. * Refer to "4. AC Characteristics (2) Source Clock/Machine Clock" for FMP and FMPL. 38 DS07-12614-6E MB95100AM Series 4. AC Characteristics (1) Clock Timing (Vcc = 2.42 V to 5.0 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter SymCondiPin name bol tions Clock frequency FCH FCL X0, X1 X0A, X1A Clock cycle time tHCYL Input clock pulse width Input clock rise time and fall time DS07-12614-6E X0, X1 Value Unit Remarks 16.25 MHz When using main oscillation circuit 32.50 MHz When using external clock 3.00 10.00 MHz Main PLL multiplied by 1 3.00 8.13 MHz Main PLL multiplied by 2 3.00 6.50 MHz Main PLL multiplied by 2.5 32.768 kHz When using sub oscillation circuit 32.768 kHz When using sub PLL 61.5 1000 ns When using oscillation circuit 30.8 1000 ns When using external clock When using sub clock Min Typ Max 1.00 1.00 tLCYL X0A, X1A 30.5 s tWH1 tWL1 X0 61.5 ns tWH2 tWL2 X0A 15.2 s tCR tCF X0, X0A 5 ns When using external clock Duty ratio is about 30% to 70%. When using external clock 39 MB95100AM Series tHCYL tWH1 tWL1 tCR tCF 0.8 VCC 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC * Figure of main clock input port external connection When using a crystal or ceramic oscillator When using external clock Microcontroller Microcontroller X0 X1 X0 X1 Open FCH FCH tLCYL tWH2 tCR tWL2 tCF 0.8 VCC 0.8 VCC X0A 0.1 VCC 0.1 VCC 0.1 VCC * Figure of sub clock input port external connection When using a crystal or ceramic oscillator When using external clock Microcontroller Microcontroller X0A X1A FCL X0A X1A Open FCL 40 DS07-12614-6E MB95100AM Series (2) Source Clock/Machine Clock (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Sym- Pin bol name Source clock*1 (Clock before setting division) tSCLK Source clock frequency Machine clock*2 (Minimum instruction execution time) Machine clock frequency Value Min Typ Max Unit Remarks 61.5 2000 ns When using main clock Min : FCH = 16.25 MHz, PLL multiplied by 1 Max : FCH = 1 MHz, divided by 2 7.6 61.0 s When using sub clock Min : FCL = 32 kHz, PLL multiplied by 4 Max : FCL = 32 kHz, divided by 2 FSP 0.50 FSPL 16.384 61.5 32000 ns When using main clock Min : FSP = 16.25 MHz, no division Max : FSP = 0.5 MHz, divided by 16 7.6 976.5 s When using sub clock Min : FSPL = 131 kHz, no division Max : FSPL = 16 kHz, divided by 16 0.031 16.250 1.024 131.072 kHz When using sub clock tMCLK FMP FMPL 16.25 MHz When using main clock 131.072 kHz When using sub clock MHz When using main clock *1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follows. * Main clock divided by 2 * PLL multiplication of main clock (select from 1, 2, 2.5 multiplication) * Sub clock divided by 2 * PLL multiplication of sub clock (select from 2, 3, 4 multiplication) *2 : Operation clock of the microcontroller. Machine clock can be selected as follows. * Source clock (no division) * Source clock divided by 4 * Source clock divided by 8 * Source clock divided by 16 DS07-12614-6E 41 MB95100AM Series * Outline of clock generation block FCH (main oscillation) Divided by 2 Main PLL x1 x2 x 2.5 SCLK ( source clock ) FCL (sub oscillation) Divided by 2 Sub PLL x2 x3 x4 42 Division circuit x1 x 1/4 x 1/8 x 1/16 MCLK ( machine clock ) Clock mode select bit ( SYCC : SCS1, SCS0 ) DS07-12614-6E MB95100AM Series * Operating voltage - Operating frequency (TA = - 40 C to + 85 C) * MB95F104AMS/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/F108AMS/F108ANS/F108AJS/F104AMW/ MB95F104ANW/F104AJW/F106AMW/F106ANW/F106AJW/F108AMW/F108ANW/F108AJW Main clock mode, main PLL mode operating guarantee range Sub PLL, Sub clock mode, watch mode, operating guarantee range 5.5 Operating voltage (V) Operating voltage (V) 5.5 2.42 16.384 kHz 32 kHz 3.5 2.42 0.5 MHz 3 MHz 131.072 kHz 10 MHz 16.25 MHz PLL operating guarantee range PLL operating guarantee range Main clock operating guarantee range Source clock frequency (FSP) Source clock frequency (FSPL) * Operating voltage - Operating frequency (TA = + 5 C to + 35 C) * MB95FV100D-103 Sub PLL, sub clock mode and watch mode operation guarantee range Main clock mode and main PLL mode operation guarantee range 5.5 2.7 16.384 kHz 32 kHz 131.072 kHz PLL operation guarantee range Source clock frequency (FSPL) DS07-12614-6E Operating voltage (V) Operating voltage (V) 5.5 3.5 2.7 0.5 MHz 3 MHz 10 MHz 16.25 MHz PLL operation guarantee range Main clock operation guarantee range Source clock frequency (FSP) 43 MB95100AM Series * Main PLL operation frequency 16 MHz 15 MHz 14 MHz Source clock frequency (FSP) 13 MHz 12 MHz 11 MHz 10 MHz x 2.5 x1 x2 9 MHz 8 MHz 7.5MHz 7 MHz 6 MHz 5 MHz 4 MHz 3 MHz 0 MHz 3 MHz 4 MHz 5 MHz 6.4 MHz 8 MHz 10 MHz Main clock frequency (FMP) 44 DS07-12614-6E MB95100AM Series (3) External Reset (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Value Symbol Min Max 2 tMCLK*1 RST "L" level pulse width tRSTL Oscillation time of oscillator* + 100 100 2 Unit Remarks ns At normal operating s At stop mode, sub clock mode, sub sleep mode, and watch mode s At timebase timer mode *1 : Refer to " (2) Source Clock/Machine Clock" for tMCLK. *2 : Oscillation time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of s and several ms. In the external clock, the oscillation time is 0 ms. * At normal operating tRSTL RST 0.2 VCC 0.2 VCC * At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on RST tRSTL 0.2 VCC 0.2 VCC 90% of amplitude X0 Internal operating clock 100 s Oscillation time Oscillation stabilization wait time of oscillator Execute instruction Internal reset DS07-12614-6E 45 MB95100AM Series (4) Power-on Reset (AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Power supply rising time Power supply cutoff time Symbol Conditions tR tOFF tR Value Unit Min Max 50 ms 1 ms Remarks Waiting time until power-on tOFF 2.5 V VCC 0.2 V 0.2 V 0.2 V Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 30 mV/ms as shown below . VCC Limiting the slope of rising within 30 mV/ms is recommended. 2.3 V Hold condition in STOP mode VSS 46 DS07-12614-6E MB95100AM Series (5) Peripheral Input Timing (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Value Symbol Pin name Peripheral input "H" pulse width tILIH Peripheral input "L" pulse width tIHIL INT00 to INT07, INT10 to INT13, EC0, EC1, TI0, TRG0/ADTG, TRG1 Unit Min Max 2 tMCLK* ns 2 tMCLK* ns * : Refer to " (2) Source Clock/Machine Clock" for tMCLK. tILIH INT00 to INT07, INT10 to INT13, EC0, EC1, TI0, TRG0/ADTG, TRG1 DS07-12614-6E tIHIL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 47 MB95100AM Series (6) UART/SIO, Serial I/O Timing (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol Pin name Conditions Serial clock cycle time tSCYC UCK0 UCK UO time tSLOV UCK0, UO0 Valid UI UCK tIVSH UCK0, UI0 UCK valid UI hold time tSHIX Serial clock "H" pulse width Value Unit Min Max 4 tMCLK* ns - 190 + 190 ns 2 tMCLK* ns UCK0, UI0 2 tMCLK* ns tSHSL UCK0 4 tMCLK* ns Serial clock "L" pulse width tSLSH UCK0 4 tMCLK* ns UCK UO time tSLOV UCK0, UO0 190 ns Valid UI UCK tIVSH UCK0, UI0 2 tMCLK* ns UCK valid UI hold time tSHIX UCK0, UI0 2 tMCLK* ns Internal clock operation External clock operation * : Refer to " (2) Source Clock/Machine Clock" for tMCLK. * Internal shift clock mode tSCYC 2.4 V UCK0 0.8 V 0.8 V tSLOV UO0 2.4 V 0.8 V UI0 tIVSH tSHIX 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC * External shift clock mode tSHSL tSLSH 0.8 VCC 0.8 VCC UCK0 0.2 VCC 0.2 VCC tSLOV UO0 UI0 48 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC DS07-12614-6E MB95100AM Series (7) LIN-UART Timing Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Serial clock cycle time SymPin name bol tSCYC SCK SOT delay time tSLOVI Valid SIN SCK tIVSHI SCK valid SIN hold time tSHIXI Serial clock "L" pulse width tSLSH SCK Max 5 tMCLK*3 ns + 95 ns ns ns * - tR ns * + 95 ns 2 tMCLK*3 + 95 ns 190 ns * + 95 ns MCLK 3 SCK 3t MCLK 3 SCK tSHSL SCK SOT delay time tSLOVE SCK, SOT Valid SIN SCK tIVSHE SCK, SIN t External clock operation output pin : CL = 80 pF + 1 TTL. t Unit Min Internal clock SCK, SOT - 95 operation output pin : SCK, SIN CL = 80 pF + 1 TTL. tMCLK*3 + 190 SCK, SIN 0 Serial clock "H" pulse width SCK valid SIN hold time Value Conditions MCLK 3 tSHIXE SCK, SIN SCK fall time tF SCK 10 ns SCK rise time tR SCK 10 ns *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK. DS07-12614-6E 49 MB95100AM Series * Internal shift clock mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOVI 2.4 V SOT 0.8 V tIVSHI tSHIXI 0.8 VCC 0.8 VCC SIN 0.2 VCC 0.2 VCC * External shift clock mode tSLSH SCK 0.8 VCC 0.8 VCC 0.2 VCC tF SOT tSHSL 0.8 VCC 0.2 VCC tR tSLOVE 2.4 V 0.8 V tIVSHE SIN tSHIXE 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 50 DS07-12614-6E MB95100AM Series Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Symbol Pin name tSCYC SCK tSHOVI Valid SIN SCK tIVSLI SCK valid SIN hold time tSLIXI Serial clock "H" pulse width tSHSL Serial clock "L" pulse width tSLSH Value Conditions Internal clock SCK, SOT operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK, SIN SCK SCK Unit Min Max 5 tMCLK*3 ns - 95 + 95 ns ns 0 ns 3 tMCLK*3 - tR ns * + 95 ns * + 190 MCLK 3 t t MCLK 3 * + 95 SCK SOT delay time tSHOVE SCK, SOT Valid SIN SCK tIVSLE SCK, SIN SCK valid SIN hold time tSLIXE SCK, SIN SCK fall time tF SCK 10 ns SCK rise time tR SCK 10 ns External clock operation output pin : CL = 80 pF + 1 TTL. MCLK 3 ns 190 ns tMCLK*3 + 95 ns 2t *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK. DS07-12614-6E 51 MB95100AM Series * Internal shift clock mode tSCYC 2.4 V SCK 2.4 V 0.8 V tSHOVI 2.4 V SOT 0.8 V tIVSLI tSLIXI 0.8 VCC 0.8 VCC SIN 0.2 VCC 0.2 VCC * External shift clock mode tSHSL SCK 0.8 VCC tSLSH 0.8 VCC 0.2 VCC tR SOT 0.2 VCC 0.2 VCC tF tSHOVE 2.4 V 0.8 V tIVSLE SIN tSLIXE 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 52 DS07-12614-6E MB95100AM Series Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Symbol Pin name Serial clock cycle time tSCYC SCK SCK SOT delay time tSHOVI SCK, SOT Parameter Valid SIN SCK tIVSLI SCK, SIN SCK valid SIN hold time tSLIXI SCK, SIN SOT SCK delay time tSOVLI SCK, SOT Value Conditions Internal clock operation output pin : CL = 80 pF + 1 TTL. t Unit Min Max 5 tMCLK*3 ns - 95 + 95 ns ns 0 ns 4 tMCLK*3 ns * + 190 MCLK 3 *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK. tSCYC 2.4 V SCK 0.8 V SOT 2.4 V 0.8 V 2.4 V 0.8 V tIVSLI SIN DS07-12614-6E 0.8 V tSHOVI tSOVLI tSLIXI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 53 MB95100AM Series Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Symbol Pin name Serial clock cycle time tSCYC SCK SOT delay time tSLOVI Parameter Value Conditions Unit Min Max SCK 5 tMCLK*3 ns SCK, SOT - 95 + 95 ns ns 0 ns 4 tMCLK*3 ns Valid SIN SCK tIVSHI SCK valid SIN hold time tSHIXI Internal clock SCK, SIN operating output pin : L = 80 pF + 1 TTL. SCK, SIN C SOT SCK delay time tSOVHI SCK, SOT t * + 190 MCLK 3 *1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK. tSCYC 2.4 V SCK 2.4 V 0.8 V tSOVHI SOT 2.4 V 0.8 V 2.4 V 0.8 V tIVSHI SIN 54 tSLOVI 0.8 VCC 0.2 VCC tSHIXI 0.8 VCC 0.2 VCC DS07-12614-6E MB95100AM Series (8) I2C Timing (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Value Parameter Symbol SCL clock frequency Pin name Conditions R = 1.7 k, C = 50 pF*1 Standardmode Fast-mode Unit Min Max Min Max 0 100 0 400 kHz 4.0 0.6 s fSCL SCL0 tHD;STA SCL0 SDA0 SCL clock "L" width tLOW SCL0 4.7 1.3 s SCL clock "H" width tHIGH SCL0 4.0 0.6 s tSU;STA SCL0 SDA0 4.7 0.6 s Data hold time SCL SDA tHD;DAT SCL0 SDA0 0 3.45*2 0 0.9*3 s Data setup time SDA SCL tSU;DAT SCL0 SDA0 0.25 0.1 s tSU;STO SCL0 SDA0 4 0.6 s tBUF SCL0 SDA0 4.7 1.3 s (Repeat) Start condition hold time SDA SCL (Repeat) Start condition setup time SCL SDA Stop condition setup time SCL SDA Bus free time between stop condition and start condition *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHD;DAT have only to be met if the device dose not stretch the "L" width (tLOW) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. tWAKEUP SDA0 tLOW tHD;DAT tHIGH tHD;STA tBUF SCL0 tHD;STA DS07-12614-6E tSU;DAT tSU;STA tSU;STO 55 MB95100AM Series (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter SCL clock "L" width SCL clock "H" width Sym- Pin Condition bol name tLOW tHIGH Start condition hold time Value*2 Min SCL0 R = 1.7 k, (2 + nm / 2) tMCLK - 20 SCL0 C = 50 pF* 1 (nm / 2) tMCLK - 20 Max Unit ns Master mode (nm / 2 ) tMCLK + 20 ns Master mode ns Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. tHD;STA SCL0 SDA0 (-1 + nm / 2) tMCLK - 20 Stop condition setup time tSU;STO SCL0 SDA0 (1 + nm / 2) tMCLK - 20 (1 + nm / 2) tMCLK + 20 ns Start condition setup time tSU;STA SCL0 SDA0 (1 + nm / 2) tMCLK - 20 (1 + nm / 2) tMCLK + 20 ns Bus free time between stop condition and start condition tBUF SCL0 SDA0 (2 nm + 4) tMCLK - 20 ns tHD;DAT SCL0 SDA0 3 tMCLK - 20 ns Data hold time (-1 + nm) tMCLK + 20 Setup time between clearing interrupt and SCL rising SCL0 SDA0 tSU;INT SCL0 (-2 + nm / 2) tMCLK - 20 (-1 + nm / 2) tMCLK + 20 Master mode Master mode Master mode ns Master mode When assuming that "L" of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Data setup time tSU;DAT Remarks (nm / 2) tMCLK - 20 (1 + nm / 2) tMCLK + 20 ns Minimum value is applied to interrupt at 9th SCL. Maximum value is applied to interrupt at 8th SCL. At reception SCL clock "L" width tLOW SCL0 4 tMCLK - 20 ns SCL clock "H" width 4 tMCLK - 20 ns At reception tHIGH SCL0 Start condition detection tHD;STA SCL0 SDA0 2 tMCLK - 20 ns Undetected when 1 tMCLK is used at reception Stop condition detection tSU;STO SCL0 SDA0 2 tMCLK - 20 ns Undetected when 1 tMCLK is used at reception Restart detection condition tSU;STA SCL0 SDA0 2 tMCLK - 20 ns Undetected when 1 tMCLK is used at reception tBUF SCL0 SDA0 2 tMCLK - 20 ns tHD;DAT SCL0 SDA0 2 tMCLK - 20 ns At slave transmission mode tSU;DAT SCL0 SDA0 tLOW - 3 tMCLK - 20 ns At slave transmission mode Bus free time Data hold time Data setup time At reception (Continued) 56 DS07-12614-6E MB95100AM Series (Continued) Parameter Data hold time Data setup time SDASCL (at wake-up function) (Vcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Value*2 Sym- Pin Condition bol name Unit Min Max 0 ns tHD;DAT SCL0 R = 1.7 k, SDA0 C = 50 pF*1 tSU;DAT SCL0 SDA0 tMCLK - 20 ns tWAKEUP SCL0 SDA0 Oscillation stabilization wait time + 2 tMCLK - 20 ns Remarks At reception At reception *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : * Refer to " (2) Source Clock/Machine Clock" for tMCLK. * m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR0) . * n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR0) . * Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of ICCR0 register. * Standard-mode : m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n limits the machine clock that can be used below. (m, n) = (1, 8) : 0.9 MHz < tMCLK 1 MHz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK 2 MHz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK 4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK 10 MHz * Fast-mode : m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n limits the machine clock that can be used below. (m, n) = (1, 8) : 3.3 MHz < tMCLK 4 MHz (m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK 8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK 10 MHz DS07-12614-6E 57 MB95100AM Series (9) Low Voltage Detection (AVss = Vss = 0.0 V, TA = -40 C to + 85 C) Parameter Symbol Value Min Typ Max Unit Remarks Release voltage VDL+ 2.52 2.70 2.88 V At power-supply rise Detection voltage VDL- 2.42 2.60 2.78 V At power-supply fall Hysteresis width VHYS 70 100 mV Power-supply start voltage Voff 2.3 V Power-supply end voltage Von 4.9 V 0.3 s Slope of power supply that reset release signal generates 3000 s Slope of power supply that reset release signal generates within rating (VDL+) 300 s Slope of power supply that reset detection signal generates 300 s Slope of power supply that reset detection signal generates within rating (VDL-) Power-supply voltage change time (at power supply rise) tr Power-supply voltage change time (at power supply fall) tf Reset release delay time td1 400 s Reset detection delay time td2 30 s ILVD 38 50 A Current consumption Current consumption for low voltage detection circuit only VCC Von Voff VCC VDL+ time tr tf VHYS VDL- Internal reset signal time td2 58 td1 DS07-12614-6E MB95100AM Series (10) Clock Supervisor Clock (Vcc = AVcc = 5.0 V 10%, AVss = Vss = 0.0 V, TA = -40 C to + 85 C) Parameter Symbol Value Min Typ Max Unit Oscillation frequency fOUT 50 100 200 kHz Oscillation start time twk 10 s ICSV 20 36 A Current consumption DS07-12614-6E Remarks Current consumption of built-in CR oscillator, at oscillation of 100 kHz 59 MB95100AM Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (AVcc = Vcc = 4.0 V to 5.5 V, AVss = Vss = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol Linearity error Full-scale transition voltage Compare time Remarks Typ Max 10 bit - 3.0 + 3.0 LSB - 2.5 + 2.5 LSB - 1.9 + 1.9 LSB VOT AVss - 1.5 LSB AVss + 0.5 LSB AVss + 2.5 LSB V VFST AVR - 3.5 LSB AVR - 1.5 LSB AVR + 0.5 LSB V 0.9 16500 s 4.5 V AVcc 5.5 V 1.8 16500 s 4.0 V AVcc < 4.5 V 0.6 s 4.5 V AVcc 5.5 V, At external impedance < 5.4 k 1.2 s 4.0 V AVcc < 4.5 V, At external impedance < 2.4 k Differential linear error Zero transition voltage Unit Min Resolution Total error Value Sampling time Analog input current IAIN - 0.3 + 0.3 A Analog input voltage VAIN AVss AVR V Reference voltage AVss + 4.0 AVcc V AVR pin Reference voltage supply current IR 600 900 A AVR pin, During A/D operation IRH 5 A AVR pin, At stop mode 60 DS07-12614-6E MB95100AM Series (2) Notes on Using A/D Converter * About the external impedance of analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/ D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * Analog input equivalent circuit R Analog input Comparator C During sampling : ON 4.5 V AVcc 5.5 V 4.0 V AVcc < 4.5 V R 2.0 k (Max) 8.2 k (Max) C 16 pF (Max) 16 pF (Max) Note : The values are reference values. * The relationship between external impedance and minimum sampling time (External impedance = 0 k to 20 k) 100 90 80 70 60 50 40 30 20 10 0 AVCC 4.5 V AVCC 4.0 V 0 2 4 6 8 10 12 Minimum sampling time [s] 14 External impedance [k] External impedance [k] (External impedance = 0 k to 100 k) 20 18 16 14 12 10 8 6 4 2 0 AVCC 4.5 V AVCC 4.0 V 0 1 2 3 4 Minimum sampling time [s] * About errors As |AVR - AVSS| becomes smaller, values of relative errors grow larger. DS07-12614-6E 61 MB95100AM Series (3) Definition of A/D Converter Terms * Resolution The level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. * Linearity error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") of a device and the full-scale transition point ("11 1111 1111" "11 1111 1110") compared with the actual conversion values obtained. * Differential linear error (Unit : LSB) Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. * Total error (unit: LSB) Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. Ideal I/O characteristics Total error VFST 3FFH 3FFH 3FEH 1.5 LSB 3FDH 004H 003H 002H VOT Digital output Digital output 3FEH 3FDH Actual conversion characteristic {1 LSB x (N - 1) + 0.5 LSB} 004H 003H 002H 1 LSB VNT Actual conversion characteristic Ideal characteristics 001H 001H 0.5 LSB AVSS AVR Analog input 1 LSB = AVR - AVss 1024 (V) AVSS AVR Analog input Total error of = VNT - {1 LSB x (N - 1) + 0.5 LSB} [LSB] digital output N 1 LSB N : A/D converter digital output value VNT : A voltage at which digital output transits from (N - 1) to N. (Continued) 62 DS07-12614-6E MB95100AM Series (Continued) Full-scale transition error Zero transition error Ideal characteristics 004H 3FFH Digital output Digital output Actual conversion characteristic 003H Ideal characteristics 002H Actual conversion characteristic Actual conversion characteristic 3FEH VFST (measurement value) 3FDH 001H Actual conversion characteristic 3FCH VOT (measurement value) AVSS AVR AVSS AVR Analog input Analog input Differential linear error Linearity error Actual conversion characteristic 3FFH 3FEH Actual conversion characteristic VFST (measurement value) VNT 004H Actual conversion characteristic 003H Digital output {1 LSB x N + VOT} 3FDH Digital output Ideal characteristics N+1H NH N-1H VNT Actual conversion characteristic Ideal characteristics 002H N-2H 001H V (N+1)T VOT (measurement value) AVR AVSS AVSS Analog input Linearity error in = VNT - {1 LSB x N + VOT} 1 LSB digital output N Analog input Differential linear error = in digital output N V (N + 1) T - VNT 1 LSB AVR -1 N : A/D converter digital output value VNT : A voltage at which digital output transits from (N - 1) to N. VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVR - 1.5 LSB [V] DS07-12614-6E 63 MB95100AM Series 6. Flash Memory Program/Erase Characteristics Parameter Value Unit Min Typ Max Sector erase time (4 Kbytes sector) 0.2*1 0.5*2 s Sector erase time (16 Kbytes sector) 0.5*1 7.5*2 s Byte programming time 32 3,600 s 10000 cycle Power supply voltage at erase/ program 4.5 5.5 V Flash memory data retention time 20*3 year Erase/program cycle Remarks Excludes 00H programming prior erasure. Excludes 00H programming prior erasure. Excludes system-level overhead. Average TA = +85 C *1 : TA = + 25 C, VCC = 5.0 V, 10000 cycles *2 : TA = + 85 C, VCC = 4.5 V, 10000 cycles *3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 C) . 64 DS07-12614-6E MB95100AM Series MASK OPTION MB95F104AMW MB95F104ANW MB95F104AJW MB95F106AMW MB95F106ANW MB95F106AJW MB95F108AMW MB95F108ANW MB95F108AJW MB95FV100D-103 Part number MB95108AM MB95F104AMS MB95F104ANS MB95F104AJS MB95F106AMS MB95F106ANS MB95F106AJS MB95F108AMS MB95F108ANS MB95F108AJS Specifying procedure Specify when ordering MASK Setting disabled Setting disabled Setting disabled 1 Clock mode select * Single-system clock mode * Dual-system clock mode Selectable Single-system clock mode Dual-system clock mode Changing by the switch on MCU board 2 Low voltage detection reset* * With low voltage detection reset * Without low voltage detection reset Specify when ordering MASK Specified by part number Specified by part number Changing by the switch on MCU board 3 Clock supervisor* * With clock supervisor * Without clock supervisor Specify when ordering MASK Specified by part number Specified by part number Changing by the switch on MCU board Specified by part number MCU board switch set as following ; * With supervisor : Without reset output * Without supervisor : With reset output No. Reset output* * With reset output * Without reset output 4 Oscillation stabilization wait time 5 Specify when ordering MASK Specified by part number Fixed to Fixed to Fixed to oscillation oscillation oscillation stabilization wait stabilization wait stabilization wait time of time of time of (214-2) /FCH (214-2) /FCH (214-2) /FCH Fixed to oscillation stabilization wait time of (214-2) /FCH * : Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset output. DS07-12614-6E 65 MB95100AM Series Low voltage detection reset Clock supervisor Reset output No No Yes Yes No Yes Yes Yes No No No Yes Yes No Yes Yes Yes No MB95F104AMS No No Yes MB95F104ANS Yes No Yes MB95F104AJS Yes Yes No MB95F106AMS No No Yes Yes No Yes MB95F106AJS Yes Yes No MB95F108AMS No No Yes MB95F108ANS Yes No Yes MB95F108AJS Yes Yes No MB95F104AMW No No Yes MB95F104ANW Yes No Yes MB95F104AJW Yes Yes No MB95F106AMW No No Yes Yes No Yes MB95F106AJW Yes Yes No MB95F108AMW No No Yes MB95F108ANW Yes No Yes MB95F108AJW Yes Yes No No No Yes Yes No Yes Yes Yes No No No Yes Yes No Yes Yes Yes No Part number Clock mode select Single-system MB95108AM Dual-system MB95F106ANS MB95F106ANW Single-system Dual-system Single-system MB95FV100D-103 Dual-system 66 DS07-12614-6E MB95100AM Series ORDERING INFORMATION Part number Package MB95108AMPMC1 MB95F104AMSPMC1 MB95F104ANSPMC1 MB95F104AJSPMC1 MB95F104AMWPMC1 MB95F104ANWPMC1 MB95F104AJWPMC1 MB95F106AMSPMC1 MB95F106ANSPMC1 MB95F106AJSPMC1 MB95F106AMWPMC1 MB95F106ANWPMC1 MB95F106AJWPMC1 MB95F108AMSPMC1 MB95F108ANSPMC1 MB95F108AJSPMC1 MB95F108AMWPMC1 MB95F108ANWPMC1 MB95F108AJWPMC1 64-pin plastic LQFP (FPT-64P-M24) MB95108AMPMC MB95F104AMSPMC MB95F104ANSPMC MB95F104AJSPMC MB95F104AMWPMC MB95F104ANWPMC MB95F104AJWPMC MB95F106AMSPMC MB95F106ANSPMC MB95F106AJSPMC MB95F106AMWPMC MB95F106ANWPMC MB95F106AJWPMC MB95F108AMSPMC MB95F108ANSPMC MB95F108AJSPMC MB95F108AMWPMC MB95F108ANWPMC MB95F108AJWPMC 64-pin plastic LQFP (FPT-64P-M23) MB2146-303A-E (MB95FV100D-103PBT) ( DS07-12614-6E MCU board 224-pin plastic PFBGA (BGA-224P-M08) ) 67 MB95100AM Series PACKAGE DIMENSIONS 64-pin plastic LQFP Lead pitch 0.50 mm Package width x package length 10.0 x 10.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g Code (Reference) P-LFQFP64-10x10-0.50 (FPT-64P-M24) 64-pin plastic LQFP (FPT-64P-M24) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.000.20(.472.008)SQ * 10.000.10(.394.004)SQ 48 0.1450.055 (.006.002) 33 49 32 Details of "A" part 0.08(.003) +0.20 1.50 -0.10 +.008 .059 -.004 INDEX 64 0~8 17 (Mounting height) 0.100.10 (.004.004) (Stand off) "A" LEAD No. 1 16 0.50(.020) 0.200.05 (.008.002) 0.08(.003) M (c)2005-2008 FUJITSU MICROELECTRONICS LIMITED F64036S-c-1-2 C 2005 FUJITSU LIMITED F64036S-c-1-1 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 68 DS07-12614-6E MB95100AM Series (Continued) 64-pin plastic LQFP Lead pitch 0.65 mm Package width x package length 12.0 x 12.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Code (Reference) P-LFQFP64-12x12-0.65 (FPT-64P-M23) 64-pin plastic LQFP (FPT-64P-M23) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.000.20(.551.008)SQ *12.000.10(.472.004)SQ 48 0.1450.055 (.0057.0022) 33 49 32 0.10(.004) Details of "A" part +0.20 1.50 -0.10 +.008 (Mounting height) .059 -.004 0.25(.010) INDEX 0~8 64 17 1 "A" 16 0.65(.026) 0.320.05 (.013.002) 0.13(.005) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) (Stand off) M (c)2003-2008 FUJITSU LIMITED F64034S-c-1-2 C 2003 FUJITSU LIMITEDMICROELECTRONICS F64034S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS07-12614-6E 69 MB95100AM Series MAIN CHANGES IN THIS EDITION Page 4 Section PRODUCT LINEUP Change Results Corrected "Reset output" in MB95108AM to "Yes/No". The vertical lines marked in the left side of the page show the changes. 70 DS07-12614-6E MB95100AM Series MEMO DS07-12614-6E 71 MB95100AM Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. 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