Page 1 of 11
Document No. DOC-22914-2 │www.psemi.com ©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 1. Functional Diagram
Figure 2. Package Photo
24-lead 4x4 mm QFN
Product Specification
SP5T Absorptive UltraCMOS®
High-Isolation RF Switch
450-4000 MHz, VssEXT option
PE42451
Features
HaRP™-enhanced UltraCMOS® device
Five symmetric, absorptive RF ports
High Isolation:
68 dB at 450 MHz
62 dB at 900 MHz
55 dB at 2100 MHz
53 dB at 2600 MHz
50 dB at 4000 MHz
IIP2 of 95 dBm, IIP3 of 58 dBm
High ESD tolerance of 3500 V HBM
Optional External Vss Control (VssEXT)
Three pin CMOS logic control
No blocking capacitors required
Small RoHS-Compliant 24-lead 4x4 mm
QFN package
The PE42451 is a HaRP™-enhanced Absorptive SP5T
RF Switch developed on the UltraCMOS® process
technology. This general purpose switch is comprised of
five symmetric RF ports and has very high isolation. An
on-chip CMOS decode logic facilitates a three-pin low
voltage CMOS control interface and an optional external
Vss feature (VssEXT). High ESD tolerance and no
blocking capacitor requirements make this the ultimate in
integration and ruggedness.
Peregrine’s HaRP™ technology enhancements deliver
high linearity and exceptional harmonics performance. It
is an innovative feature of the UltraCMOS® process,
providing performance superior to GaAs with the
economy and integration of conventional CMOS.
Product Description
RF2
RF5
RF4
CMOS Control/
Driver and ESD
V1 V2
RF1
V3
RF3
ESD
50
ESD
50
ESD
50
ESD
50
ESD
50
RFC
VssEXT (optional)VDD DOC-02114
Product Specification
PE42451
Page 2 of 11
Document No. DOC-22914-2 │ UltraCMOS® RFIC Solutions ©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Table 1. Electrical Specifications @ 25 °C, VDD = 3.0 V (ZS = ZL = 50 Ω )
Notes: 1. Please refer to Maximum Operating Power in Table 2
Electrical Parameter Path Condition Min Typ Max Unit
Operating Frequency 450 4000 MHz
Insertion Loss, IL
RFC - RFX
RFC - RFX
RFC - RFX
RFC - RFX
RFC - RFX
450 MHz
900 MHz
2100 MHz
2600 MHz
4000 MHz
1.6
1.65
1.95
2.05
2.25
1.95
2.05
2.30
2.40
2.75
dB
dB
dB
dB
dB
Isolation, Iso
RFC/RFX - RFX
RFC/RFX - RFX
RFC/RFX - RFX
RFC/RFX - RFX
RFC/RFX - RFX
450 MHz
900 MHz
2100 MHz
2600 MHz
4000 MHz
58.5
53.0
46.5
46.5
41.5
68
62
55
53
50
dB
dB
dB
dB
dB
Return Loss, Active Port RFX 450 - 4000 MHz 16 dB
Return Loss, Terminated Port RFX 450 - 4000 MHz 15 dB
Input 1 dB compression1, P1dB RFX - RFC All Bands,100% duty cycle 35 dBm
Input IP2 RFX - RFC All Bands, 100% duty cycle 95 dBm
Input IP3 RFX - RFC All Bands, 100% duty cycle 58 dBm
Switching Time, TSW "On"
"Off" 50% Control to 90% RF
50% Control to 10% RF 200
200 500
500 ns
ns
Table 2. Operating Ranges
Parameter Min Typ Max Units
VDD Supply Voltage 2.7 3.0 3.3 V
VssEXT Negative Power Supply
Voltage2 -3.3 -3.0 -2.7 V
IDD Max Power Supply Current
VDD = 3.3 V, PMAX= 33 dBm,
Temperature = -40°C 50 µA
Control Voltage High 0.7 x
VDD VDD V
Control Voltage Low 0 0.3 x
VDD V
ICTRL Control Current3 1 µA
Maximum Operating Power
(RFX-RFC, All Bands (50Ω),
100% duty cycle) 33 dBm
Maximum power into
termination (RFX, All Bands
(50Ω),100% duty cycle) 24 dBm
Operating temperature range -40 +85 °C
Symbol
VDD
VssEXT
IDD
(max)
VIH
VIL
ICTRL
PMAX
PMAX
TOP
IDD Power Supply Current
VDD = 3.0 V, PIN= 0 dBm IDD 14 µA
Note: 2. Applied only when external Vss power supply used.
Pin 20 must be grounded when using internal Vss supply.
3. Pull-down resistor in EVK schematic may increase
control current.
Product Specification
PE42451
Page 3 of 11
Document No. DOC-22914-2 │www.psemi.com ©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Table 3. Pin Descriptions
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS® de vice, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be take n to avoid exceeding the
specified rating.
Latch-Up Avoidance
Unlike conventional CMO S devices, UltraCMOS®
devices are immune to latch-up.
Table 4. Absolute Maximum Ratings
Exceeding ab solute maximum rati ngs may cau se
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table.
Symbol Parameter/Conditions Min Max Units
TST Storage temperature range -60 +150 °C
PMAX
Maximum Operating Power
(RFX-RFC, All Bands (50Ω),
100% duty cycle) 33 dBm
PMAX
Maximum power into
termination (RFX, All Bands
(50Ω),100% duty cycle) 24 dBm
VESD ESD Voltage HBM6, All Pins 3500 V
VESD ESD Voltage MM7, All Pins 150 V
Notes: 6. Human Body Model ESD Voltage (HBM, MIL_STD 883
Method 3015.7)
7. Machine Model ESD Voltage (JESD22-A115-A)
Mode V3 V2 V1
All off 0 0 0
RF1 on 0 0 1
RF2 on 0 1 0
RF3 on 0 1 1
RF4 on 1 0 0
RF5 on 1 0 1
All off 1 1 0
Unsupported 1 1 1
Table 5. Truth Table
Exposed
Ground
Paddle
GND
RF5
GND
GND GND
Vdd
V1
V2
GND
RFC
GND
GND
Vss
EXT
/
GND
RF4
24
23
22
21
20
19
18
17
16
15
14
13
2
3
4
5
6
1
V3
RF1
GND GND
GND
RF3
GND
GND
RF2
GND
7
8
9
10
11
12
Figure 3. Pin Configuration (Top View)
Moisture Sensitivity Level
The Moisture Sensitivity Le vel rating for the PE42451 in
the 24-lead 4x4 QFN package is MSL 1.
Note: 4. Blocking capacitors needed only when non-zero DC
voltage present.
5. Pin 20 must be grounded when using internal Vss supply
Switching Frequency
The PE42451 has a maxim um 25 kHz switching rate
when the internal negative voltage generator is used
(pin 20=GND). The rate at which the PE4245 1 can be
switched is only limited to the switching time if an
external -3 V supply is provided (pin 20 =VssEXT ).
Pin # Name Description
1, 3, 4, 6, 7, 9, 10,
12, 13, 15, 21, 23, 24 GND Ground
2 RF54 RF I/O
5 RF44 RF I/O
8 RF34 RF I/O
11 RF24 RF I/O
14 RF14 RF I/O
16 VDD Supply
17 V1 Switch control input, CMOS logic level
18 V2 Switch control input, CMOS logic level
19 V3 Switch control input, CMOS logic level
20 VssEXT /
GND5 External Vss Control / Ground
22 RFC4 RF Common
Paddle GND Ground for proper device operation
Optional External Vss Control (VssEXT)
For proper operation, the V ssEXT control must be
grounded or at the Vss vol t age specified in the
Operating Ranges table (Table 2). When the Vss EXT
control pin on the package is grounded the switch
FET’s are biased with an internal low sp ur negative
voltage generator. For appl ications that require the
lowest possib le spur performance, VssEXT can be
applied to bypass the internal negative voltage
generator to eliminate the spurs.
Product Specification
PE42451
Page 4 of 11
Document No. DOC-22914-2 │ UltraCMOS® RFIC Solutions ©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The SP5T switch EK Board was designed to ease
customer evaluation of Peregrine’s PE42451. The RF
common port is conne cted through a 50 Ω transmission
line via the top SMA connector. RF1, RF2, RF3 and
RF4 are connected through 50 Ω transmission lines via
side SMA connectors. A through 50 Ω transmission is
available via SMA connectors RFCAL1 and RFCAL2.
This transmission line can be used to estimate the loss
of the PCB over the environmental conditions bei ng
evaluated.
The EVK board is constructed with four metal layers on
dielectric materials of Rogers 4003C and 4450 with a
total thickness of 32 mils. Layer 1 and layer 3 provide
ground for the 50 ohm transmi ssion lines. The 50 ohm
transmission lines are designed in layer 2 for high
isolation purpose and use a stripline waveguide d esign
with a trace width of 9.4 mils and trace metal thickness
of 1.8 mils. The board stack up for 50 ohm transmission
lines has 8 mil thickness of Rog ers 4003C between
layer 1 and layer 2, and 10 mil thickness of Rogers
4450 between layer 2 and layer 3. Please consult
manufacturer's guidelines for proper board material
properties in your applicati on. The PCB should be
designed in such a wa y that RF transmission lines and
sensitive DC i/o traces such as VssEXT are heavily
isolated from one another, otherwise the true
performance of the PE42451 will not be yield ed.
Figure 4. Evaluation Board Layouts
Figure 5. Evaluation Board Schematic
Peregrine Specification DOC-44837
Peregrine Specification PRT-50444
RF CAL
USE PCB 101-0479-03
STRIPLINE
11
33
55
77
2
24
46
68
810
10 12
12 14
14
13 13
99
11 11
J1
HEADER 14
1
2
RFCAL1
1
2
RFC
1
2
RFCAL2
1
2
RF1
R2
1M
1
2
RF4
1
2
RF5
C6
1µF
1GND
2RF5
3GND
4GND
5RF4
6GND
7GND
8RF3
9GND
10 GND
11 RF2
12 GND
13
GND
14
RF1
15
GND
16
VDD
17
V1
18
V2
19
V3
20
VSS
21
GND
22
RFC
23
GND
24
GND
U1
PE4245x_24L_QFN
1
2
RF3
1
2
RF2
C1
DNI
R1
0OHM
R3
0OHM
C2
100pF R4
1M
R5
0OHM
C3
100pF R6
1M
R7
0OHM
C4
100pF R8
1M
R9
0OHM
C5
100pF
RF
RF5
RF4
RFC
RF1
RF2RF3
V1
V2
V3
VDD
VSS
Product Specification
PE42451
Page 5 of 11
Document No. DOC-22914-2 │www.psemi.com ©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 8. Insertion Loss: All Paths
Performance Plots @ 25 °C and 3.0 V unless otherwise specified
Figure 6. Insertion Loss: RFC-RFX @ 25 °C Figure 7. Insertion Loss: RFC-RFX @ 3.0 V
Product Specification
PE42451
Page 6 of 11
Document No. DOC-22914-2 │ UltraCMOS® RFIC Solutions ©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 11. Isolation: RFX-RFX @ 25 °C
Performance Plots @ 25 °C and 3.0 V unless otherwise specified
Figure 9. Isolation: RFC-RFX @ 25 °C Figure 10. Isolation: RFC-RFX @ 3.0 V
Figure 12. Isolation: RFX-RFX @ 3.0 V
Product Specification
PE42451
Page 7 of 11
Document No. DOC-22914-2 │www.psemi.com ©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 15. Return Loss: RFC @ 25 °C
Figure 13. Return Loss at active port @ 25 °C Figure 14. Return Loss at active port @ 3.0 V
Performance Plots @ 25 °C and 3.0 V unless otherwise specified (Continued)
Figure 17. Return Loss: All Paths, Terminated
Figure 16. Return Loss: RFC @ 3.0 V
Product Specification
PE42451
Page 8 of 11
Document No. DOC-22914-2 │ UltraCMOS® RFIC Solutions ©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
0
20
40
60
80
100
120
0 1000 2000 3000 4000 5000 6000
Frequency [MHz]
IIP2 [dBm]
TX1
TX2
TX3
TX4
TX5
0
10
20
30
40
50
60
70
0 1000 2000 3000 4000 5000 6000
Frequency [MHz]
IIP3 [dBm]
TX1
TX2
TX3
TX4
TX5
Figure 19. Nominal Linearity Performance (IIP2) Figure 18. Nominal Linearity Performance (IIP3)
Performance Plots @ 25 °C and 3.0 V unless otherwise specified (Continued)
Product Specification
PE42451
Page 9 of 11
Document No. DOC-22914-2 │www.psemi.com ©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 20. Package Drawing
24-lead 4x4 mm QFN
DOC-58197
Product Specification
PE42451
Page 10 of 11
Document No. DOC-22914-2 │ UltraCMOS® RFIC Solutions ©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 21. Tape and Reel Drawing
Device Orientation in Tape
To p of
Device
Pin 1
Tape Feed Direction
A0 = 4.35
B0 = 4.35
K0 = 1.1
Figure 22. Marking Specifications
42451
YYWW
ZZZZZ YYWW = Date Code
ZZZZZ = Last five digits of Lot Number
Table 6. Ordering Information
Order Code Part Marking Description Package Shipping Method
PE42451MLIAA 42451 PE42451G-24QFN 4x4mm-cut off tape and reel Green 24-lead 4x4mm QFN Bulk or tape cut from reel
PE42451MLIAA-Z 42451 PE42451G-24QFN 4x4mm-3000C Green 24-lead 4x4mm QFN 3000 units / T&R
EK42451-01 PE42451 -EK PE42451-24QFN 4x4mm-EK Evaluation Kit 1 / Box
DOC-51207
Product Specification
PE42451
Page 11 of 11
Document No. DOC-22914-2 │www.psemi.com ©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Advance Information:
The product is in a formative or design stage. The datasheet contains design target
specifications for product development. Specifications and features may change in any m anner without notice.
Preliminary Specification:
The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best
possible product.
Product Specification:
The datasheet contains final dat a. In the event Peregrine decides to
change the specifications, Peregrine will notif y customers of the intended changes by issuing a CNF (Customer
Notification Form).
The information in this data sheet is believed to b e reliable. However, P eregrine assume s no liability for the use
of this inf o r m ati o n. U s e s hal l b e ent i rel y at th e u se r’ s o w n ri sk.
No patent rights or licenses t o any circuits described in this datasheet are im plied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a sit uation in which personal injury or death might occur. Peregrine assumes no
liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, l ogo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the
following U.S. Patents: http://patents.psemi.com.
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
