fax id: 7038 1CY 54/ CY74FCT2652T 8-Bit Registered Transceiver Features Functional Description * Function and pinout compatible with FCT and F logic The FCT2652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. GAB and GBA control pins are provided to control the transceiver functions. SAB and SBA control pins are provided to select either real-time or stored data transfer. * FCT-C speed at 5.4 ns max. (Com'l) FCT-A speed at 6.3 ns max. (Com'l) * 25 output series resistors to reduce transmission line reflection noise The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during transition between stored and real-time data. A LOW input level selects real-time data and a HIGH selects stored data. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CPAB or CPBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. * Reduced VOH (typically = 3.3V) versions of equivalent FCT functions * Edge-rate control circuitry for significantly improved noise characteristics * Power-off disable feature * Matched rise and fall times * Fully compatible with TTL input and output logic levels * Sink current Source current 12 mA 15 mA * ESD > 2000V On-chip termination resistors are added to the outputs to reduce system noise caused by reflections. The FCT2652T can replace the FCT652T to reduce noise in existing designs. * Independent register for A and B buses * Multiplexed real-time and stored data transfer * Extended commercial temp. range of -40C to +85C The outputs are designed with a power-off disable feature to allow for live insertion of boards LogicBlockDiagram Pin Configurations CPBA GAB SBA SAB SOIC/QSOP Top View GBA CPAB B REG 1 OF8 CHANNELS D C A1 AREG B1 D C CPAB 1 24 SAB 2 23 VCC CPBA GAB 3 22 SBA A1 4 21 GBA A2 5 20 B1 A3 6 19 B2 A4 7 18 B3 A5 8 17 B4 A6 9 16 B5 A7 10 B6 A8 11 15 14 GND 12 13 B8 B7 FCT2652T-3 TO 7 OTHERCHANNELS Cypress Semiconductor Corporation * FCT2652T-1 3901 North First Street * San Jose * CA 95134 * 408-943-2600 May 1994 - Revised October 1996 CY74FCT2652T BUS A GAB L BUS B GBA L CPAB X CPBA X SAB X BUS A SBA L GAB H BUS B GBA H BUS A BUS B GBA H X H CPAB CPBA X SAB X X X X CPBA X SAB L SBA X Real-Time Transfer Bus A to Bus B Real-Time Transfer Bus B to Bus A GAB X L L CPAB X BUS A SBA X X X GAB H BUS B GBA L CPAB H or L CPBA H or L SAB H SBA H Transferred Stored Data to A and/or B Store Data from A and/or B Function Table[1] Inputs Data I/O GAB GBA CPAB CPBA SAB SBA A1 thru A8 B1 thru B8 Operation or Function L L H H H or L H or L X X X X Input Input X H H H H or L X X[1 ] X X Input Input Unspecified[2] Output Store A, Hold B Store A in both registers L L X L H or L X X X X[1] Unspecified[2] Output Input Input Hold A, Store B Store B in both registers L L L L X X X H or L X X L H Output Input Real-Time B Data to A Bus Stored B Data to A Bus H H H H X H or L X X L H X X Input Output Real-Time A Data to B Bus Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus and Stored B Data to A Bus Isolation Store A and B Data Notes: 1. Select control=L: clocks can occur simultaneously. Select control=H: clocks must be staggered in order to load both registers. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care. 2 CY74FCT2652T Maximum Ratings[3, 4] DC Output Current (Maximum Sink Current/Pin ...... )120 mA Power Dissipation.......................................................... 0.5W (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied............................................. -65C to +135C Operating Range Supply Voltage to Ground Potential ............... -0.5V to +7.0V Range DC Input Voltage............................................ -0.5V to +7.0V Commercial DC Output Voltage ......................................... -0.5V to +7.0V Ambient Temperature VCC -40C to +85C 5V 5% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Typ.[5] 2.4 3.3 VOH Output HIGH Voltage VCC=Min., IOH=-15 mA VOL Output LOW Voltage VCC=Min., IOL=12 mA ROUT Output Resistance VCC=Min., IOL=12 mA VIH Input HIGH Voltage VIL Input LOW Voltage VH Hysteresis[6] All inputs 0.2 VIK Input Clamp Diode Voltage VCC=Min., IIN=-18 mA -0.7 IIH Input HIGH Current IIH IIL 20 Max. Unit V 0.3 0.55 V 25 40 2.0 V 0.8 V V -1.2 V VCC=Max., VIN=VCC 5 A Input HIGH Current VCC=Max., VIN=2.7V 1 A Input LOW Current VCC=Max., VIN=0.5V 1 A IOZH Off State HIGH-Level Output Current VCC=Max., VOUT=2.7V 10 A IOZL Off State LOW-Level Output Current VCC=Max., VOUT=0.5V -10 A IOS Output Short Circuit Current[7] VCC=Max., VOUT=0.0V -225 mA IOFF Power-Off Disable VCC=0V, VOUT=4.5V 1 A Typ.[5] Max. Unit -60 -120 Capacitance[6] Parameter Description Test Conditions CIN Input Capacitance 5 10 pF COUT Output Capacitance 9 12 pF Notes: 2. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. 3. Unless otherwise noted, these limits are over the operating free-air temperature range. 4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V CC or ground. 5. Typical values are at V CC=5.0V, TA=+25C ambient. 6. This parameter is guaranteed but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 3 CY74FCT2652T Power Supply Characteristics Parameter Typ.[5] Max. Unit VCC=Max., VIN 0.2V, VIN VCC-0.2V VCC=Max., VIN=3.4V,[8] f1=0, Outputs Open 0.1 0.2 mA 0.5 2.0 mA Description Test Conditions ICC Quiescent Power Supply Current ICC Quiescent Power Supply Current (TTL inputs HIGH) ICCD Dynamic Power Supply Current[9] VCC=Max., One Input Toggling, 50% Duty Cycle, Outputs Open, GAB=GND, GBA=GND, VIN 0.2V or VIN VCC-0.2V 0.06 0.12 mA/M Hz IC Total Power Supply Current[10] VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=5 MHz, GAB=GND, GBA=GND, SAB=CPAB=GND SBA=VCC, VIN 0.2V or VINVCC-0.2V 0.7 1.4 mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=5 MHz, GAB=GND, GBA=GND, SAB=CPAB=GND SBA=VCC, VIN =3.4V or VIN =GND 1.2 3.4 mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f 1=5 MHz, GAB=GBA=GND, SAB=CPAB=GND SBA=VCC, VIN 0.2V or VIN VCC-0.2V 2.8 5.6[11] mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f 1=5 MHz, GAB=GBA=GND, SAB=CPAB=GND SBA= VCC, VIN= 3.4V or VIN = GND 5.1 14.6[11] mA Notes: 8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 10. IC IC = ICC+ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 f1 = Input signal frequency = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 11. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 4 CY74FCT2652T Switching Characteristics[12] Over the Operating Range[13 ] CY74FCT2652T CY74FCT2652AT CY74FCT2652CT Description Min. Max. Min. Max. Min. Max. Unit Fig. No.[14] tPLH tPHL Propagation Delay Bus to Bus 1.5 9.0 1.5 6.3 1.5 5.4 ns 1, 3 tPZH tPZL Output Enable Time Enable to Bus 1.5 14.0 1.5 9.8 1.5 7.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time Enable to Bus 1.5 9.0 1.5 6.3 1.5 6.3 ns 1, 7, 8 tPLH tPHL Propagation Delay Clock to Bus 1.5 9.0 1.5 6.3 1.5 5.7 ns 1, 5 tPLH tPHL Propagation Delay SBA or SAB to A or B 1.5 11.0 1.5 7.7 1.5 6.2 ns 1, 5 tS Set-Up Time HIGH or LOW Bus to Clock 4.0 2.0 2.0 ns 4 tH Hold Time HIGH or LOW Bus to Clock 2.0 1.5 1.5 ns 4 tW Clock Pulse Width,[15] HIGH or LOW 6.0 5.0 5.0 ns 5 Parameter Ordering Information Speed (ns) 5.4 6.3 9.0 Ordering Code CY74FCT2652CTQC Package Name Package Type Q13 24-Lead (150-Mil) QSOP CY74FCT2652CTSOC S13 24-Lead (300-Mil) Molded SOIC CY74FCT2652ATQC Q13 24-Lead (150-Mil) QSOP CY74FCT2652ATSOC S13 24-Lead (300-Mil) Molded SOIC CY74FCT2652TQC Q13 24-Lead (150-Mil) QSOP CY74FCT2652TSOC S13 24-Lead (300-Mil) Molded SOIC Operating Range Commercial Commercial Commercial Notes: 12. AC Characteristics guaranteed with CL=50 pF as shown in Figure 1 in "Parameter Measurement Information" in the General Information section. 13. Minimum limits are guaranteed but not tested on Propagation Delays. 14. See "Parameter Measurement Information" in the General Information section. 15. With one data channel toggling, tW(L)=tW(H)=4.0 ns and tr=tf=1.0 ns. Document #: 38-00344-B 5 CY74FCT2652T Package Diagrams 24-Lead Quarter Size Outline Q13 24-Lead (300-Mil) Molded SOIC S13 (c) Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.