8-Bit Registered Transceiver
fax id: 7038
CY74FCT2652T
Cypress Semiconductor Corporation • 3 901 North First Str eet • San Jose • CA 95134 • 408-943-2600
May 1994 – Revised October 1996
1CY54/
Features
•Function and pinout compatible with FCT and F logic
•FCT- C speed at 5.4 ns max. (Com’l)
FCT- A speed at 6.3 ns max. (Com’l)
•25Ω output series resistors to reduce transmission line
ref lecti on nois e
•Reduced VOH (typically = 3.3V) ver sions of equi vale nt
FCT functions
•Edge-rate con trol circuitry for significantly improv ed
noise c h aracteristics
•Power-off disable feature
•Matched rise and fall times
•Fully compatible with TTL input and output logic le vels
•Sink current 12 mA
Source current 15 mA
•ESD > 2000V
•Independent register for A and B buses
•Multiplexed re al-time and stored data transfer
•Extended commerci al temp. range of –40°C to +85°C
Functional Description
The FCT2652T consists of bus transceiver circuits, D-type
flip- flops, and contr ol cir c uitry arr anged for mul tiplexed tran s-
mission of data directly from the input bus or from the internal
stora ge registers. GAB and G BA control pins are pro vided to
control the transceiver fun ction s. SAB an d SB A con t rol p i n s a re
pro vi ded to sel ec t ei th er rea l -ti me or s tor e d da ta t ran sf er.
The circuitry used for select control w ill eliminate the typical
decoding glitch that occurs in a multiplexer during transition
between stored and real-time data. A LOW input level selects
re al-time data and a HIGH selects stored data. Data on the A
or B data b us, or both, can be stored in the internal D flip-flops
by LOW-to-HIGH transitions at the appropriate clock pins
(CPAB or CPBA), regardless of the select or enable control
pins. Wh en SAB and SBA are in the real-tim e transfer mode,
it is also possible to store data without using the internal D-type
flip-flops by simultaneously enabling GAB and G BA . In this con-
figuration, each output reinforces its input. Thus, when all other data
sources to the two sets of bus lines are at high impedance, each set
of bus lines will remain at its last state.
On-chip termination resistors are added to the outputs to
reduce system noise caused by reflections. The FCT2652T
can replace the FCT652T to reduce noise in existing designs.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards
LogicBlockDiagram Pin Configurations
FCT2652T–1
C
D
B1
C
D
A1
TO 7 OTHERCHANNELS
CPAB
SAB
SBA
GBA
GAB
CPBA
BREG
AREG
1OF8CHANNELS
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
VCC
FCT2652T–3
15
Top View
CPAB
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
CPBA
SAB SBAGAB GBA
GND
SOIC/QSOP
CY74FCT2652T
2
Function Table[1]
Inputs Data I/O Operation or FunctionGAB GBA CPAB CPBA SAB SBA A1 thr u A8B1 thru B8
L
LH
HH or L H or L X
XX
XInput Input Isolation
Store A and B Data
X
HH
HH or L X
X[1 ] X
XInput
Input Unspecified[2]
Output Store A, Hold B
Store A in both registers
L
LX
LH or L X
XX
X[1] Unspecified[2]
Output Input
Input Hold A, St ore B
Store B in both registers
L
LL
LX
XX
H or L X
XL
HOutput Input Real-Time B Data to A Bus
Stored B Data to A Bus
H
HH
HX
H or L X
XL
HX
XInput Output Real-Time A Data to B Bus
Stored A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus
and Stored B Data to A Bus
Notes:
1. Select control=L: clocks can occur simultaneously.
Select control=H: clocks must be staggered in order to load both registers. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.
BUS BBUS A
GAB
LGBA
LCPAB
XCPBA
XSAB
XSBA
L
BUS BBUS A
GAB
X
L
L
GBA
H
X
H
CPAB
X
CPBA
XSAB
X
X
X
SBA
X
X
X
BUS BBUS A
GAB
HGBA
HCPAB
XCPBA
XSAB
LSBA
X
BUS BBUS A
GAB
HGBA
LCPAB
HorL CPBA
HorL SAB
HSBA
H
Real-Time Transfer
Bus B to Bus A Real-TimeTransfer
Bus A to Bus B
StoreDatafrom A and/or B Transferred Stored Data
to A and/or B
CY74FCT2652T
3
Maximum Ratings[3, 4]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ............................ .....–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–65°C to +135°C
Supply Voltage to Gro und Potential............... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
DC Output Voltage......................................... –0.5V to +7.0V
DC Output Current (Maximum Sink Current/ Pin .. ... .)120 mA
Power Dissipation. .........................................................0.5W
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015 )
Operating Range
Range Ambient
Temperature VCC
Commercial –40°C to +85°C 5V ± 5%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.[5] Max. Unit
VOH Output HIGH Volt ag e VCC=Min., IOH=−15 mA 2.4 3.3 V
VOL Output LOW Voltag e VCC=Min., IOL=12 mA 0.3 0.55 V
ROUT Output Resista nce VCC=Min., IOL=12 mA 20 25 40 Ω
VIH Input HIGH Volt a ge 2.0 V
VIL Input LOW Voltage 0.8 V
VHHysteresis[6] All inputs 0.2 V
VIK Input Clamp Diode Volt age V CC=Min., IIN=−18 mA –0.7 –1.2 V
IIH Input HIGH Current VCC=Max ., VIN=VCC 5µA
IIH Input HIGH Current VCC=Max ., VIN=2.7V ±1µA
IIL Input LOW Current VCC=Max ., VIN=0.5V ±1µA
IOZH Off State HIGH-Level Output
Current VCC=Max ., VOUT=2.7V 10 µA
IOZL Off State LOW-Level Output
Current VCC=Max ., VOUT=0.5V –10 µA
IOS Output Sh ort Circuit Current[7] VCC=Max., VOUT=0.0V –60 –120 –225 mA
IOFF Power-Off Disable VCC=0V, VOUT=4.5V ±1µA
Capacitance[6]
Parameter Description Test Conditions Typ.[5] Max. Unit
CIN Input Capacitance 5 10 pF
COUT Output Capacitance 9 12 pF
Notes:
2. The data output functions may be enabled or disabled by various signals at the G AB or GBA inputs. Data input functions are always enabled, i.e., data at the
bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
3. Unless otherwise noted, these limits are over the operating free-air temperature range.
4. Unused inputs must always be connected to an appropriate logic voltage leve l, preferably either VCC o r gro und.
5. Typical values are at VCC=5.0V, TA=+25°C ambient.
6. This parameter is guaranteed but not tested.
7. Not more than one output should be shorted at a ti me. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of par ameter
tests, IOS tests should be performed last.
CY74FCT2652T
4
Power Supply Characteristics
Parameter Description Test Condit ions Typ.[5] Max. Unit
ICC Quiescent Power Su pply Current VCC=Max., VIN ≤ 0.2V, VIN ≥ VCC-0.2V 0.1 0.2 mA
∆ICC Quiescent Power Supply Current
(TT L inputs HIGH) VCC=Max., V IN=3.4V,[8]
f1=0, Outp uts Open 0.5 2.0 mA
ICCD Dynamic Power Su pply Curr ent[9] VCC=Max., One Input To ggling,
50% Duty Cycle, Outputs Open,
GAB=GND, GBA=GND,
VIN ≤ 0.2V or VIN ≥ VCC-0.2V
0.06 0.12 mA/M
Hz
ICTotal Power Supply Current[10] VCC=Max., f0=1 0 MHz,
50% Duty Cycle, Outputs Open,
One Bit Toggling at f1=5 MHz,
GAB=GND, GBA=GND, SAB=CPAB=GND
SBA=VCC, V IN ≤ 0.2V or VIN≥VCC-0.2V
0.7 1.4 mA
VCC=Max., f0= 10 MHz,
50% Duty Cycle, Outputs Open,
One Bit Toggling at f1=5 MHz,
GAB=GND, GBA=GND, SAB=CPAB=GND
SBA=VCC, V IN =3.4V or VIN =GND
1.2 3.4 mA
VCC=Max., f0= 10 MHz,
50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f1=5 MHz,
GAB=GBA=GND, SAB=CPAB=GND
SBA=VCC, V IN ≤ 0.2V or VIN ≥ VCC-0.2V
2.8 5.6[11] mA
VCC=Max., f0= 10 MHz, 50% Duty Cycle,
Outputs Open,
Eight Bits Toggling at f1=5 MHz,
GAB=GBA=GND, SAB=CPAB=GND
SBA= VCC, VIN= 3.4V or VIN = GND
5.1 14.6[11] mA
Notes:
8. Per TTL dr iven input (VIN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Suppl y calculatio n s.
10. IC=I
QUIESCENT + IINPUTS + IDYNAMIC
IC=I
CC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH = Duty Cycle fo r TTL i nput s HIGH
NT= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0= Clock frequency f o r registered devices, otherwi se zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
CY74FCT2652T
5
Document #: 38-00344-B
Switching Characteristics[12] Over the Operating Range[13 ]
Parameter Description CY74FCT2652T CY74FCT2652AT CY74FCT2652CT Fig. No.[14]
Min. Max. Min. Max. Min. Max. Unit
tPLH
tPHL Propagation Delay
Bus to Bus 1.5 9.0 1.5 6.3 1.5 5.4 ns 1, 3
tPZH
tPZL Output Enable Time En-
able to Bus 1.5 14.0 1.5 9.8 1.5 7.8 ns 1, 7, 8
tPHZ
tPLZ Output Disable Ti me En-
able to Bus 1.5 9.0 1.5 6.3 1.5 6.3 ns 1, 7, 8
tPLH
tPHL Propagation Delay
Clock to Bus 1.5 9.0 1.5 6.3 1.5 5.7 ns 1, 5
tPLH
tPHL Propagation Delay
SBA or SAB to A or B 1.5 11.0 1.5 7.7 1.5 6.2 ns 1, 5
tSSet-U p Time
HIGH or L OW
Bus to Clock
4.0 2.0 2.0 ns 4
tHHold Time HI GH or LOW
Bus to Clock 2.0 1.5 1.5 ns 4
tWClock Pulse Width,[15]
HIGH or L OW 6.0 5.0 5.0 ns 5
Orde rin g Inf orm a tio n
Speed
(ns) Order ing Code Package
Name Package Type Operating
Range
5.4 CY74FCT2652CTQC Q13 24-Lead ( 150-Mil) QSOP Commercial
CY74FCT2652CTSOC S13 24-Lead ( 300-Mil) Molded SOIC
6.3 CY74FCT2652ATQC Q13 24-Lead (150-Mil) QSOP Commercial
CY74FCT2652ATSOC S13 24-Lead (300-Mil) Molded SOIC
9.0 CY74FCT2652TQC Q13 24-Lead ( 150-Mil) QSOP Commercial
CY74FCT2652TSOC S13 24-Lead ( 300-Mil) Molded SOIC
Notes:
12. AC Characteristics guaranteed with CL=50 pF as shown in Figure 1 in “Parameter Measurement Information” in the General Information section.
13. Minimum limits are guaranteed but not tested on Propagation Delays.
14. See “Parameter Measurement Information” in the General Information section.
15. With one data channel toggling, tW(L)=tW(H)=4.0 ns and tr=tf=1.0 ns.
CY74FCT2652T
© Cypress Semiconductor Corporation, 1996. The informati on contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry othe r than circui try embodi ed in a Cypress Semi conductor prod uct. Nor do es it convey or im ply an y li cens e under p atent or other rights . Cy press Semi conductor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
24-Lead Quarter Size Outline Q13
24-Lead (300-Mil) Molded SOIC S13
