Features
•Fast Read Access Time – 70 ns
•Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
•Fast Write Cycle Times
– Page Write Cycle Time: 3 ms or 10 ms Maximum
– 1 to 64-byte Page Write Operation
•Low Power Dissipation
– 80 mA Active Current
– 3 mA Standby Current
•Hardware and Software Data Protection
•DATA Polling for End of Write Detection
•High Reliability CMOS Technology
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
•Single 5V ± 10% Supply
•CMOS and TTL Compatible Inputs and Outputs
•JEDEC Approved Byte-wide Pinout
•Full Military and Industrial Temperature Ranges
•Green (Pb/Halide-free) Packaging Option
1. Description
The AT28HC256 is a high-performance electrically erasable and programmable read-
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256 offers
access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256
is deselected, the standby current is less than 5 mA.
The AT28HC256 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64
bytes of data are internally latched, freeing the addresses and data bus for other oper-
ations. Following the initiation of a write cycle, the device will automatically write the
latched data using an internal control timer. The end of a write cycle can be detected
by DATA Polling of I/O7. Once the end of a write cycle has been detected a new
access for a read or write can begin.
Atmel’s 28HC256 has additional features to ensure high quality and manufacturability.
The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra
64 bytes of EEPROM for device identification or tracking.
256K (32K x 8)
High-speed
Parallel
EEPROM
AT28HC256
0007N–PEEPR–9/09
2
0007N–PEEPR–9/09
AT28HC256
2.1 28-lead TSOP Top View
2.2 28-lead PGA Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
2.3 32-pad LCC, 32-lead PLCC Top View
Note: PLCC package pins 1 and 17 are Don’t Connect.
2.4 28-lead Cerdip/Flatpack/SOIC –
Top View
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
A7
A12
A14
DC
VCC
WE
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
2. Pin Configurations
Pin Name Function
A0 - A14 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
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0007N–PEEPR–9/09
AT28HC256
3. Block Diagram
4. Device Operation
4.1 Read
The AT28HC256 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their system.
4.2 Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a
write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Once a byte write has been started it
will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of tWC, a read operation will effectively be a polling operation.
4.3 Page Write
The page write operation of the AT28HC256 allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 63 additional
bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the
tBLC limit is exceeded the AT28C256 will cease accepting data and commence the internal
programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A6 - A14 inputs. That is, for each WE high to low transition dur-
ing the page write operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within the page are to be written. The
bytes may be loaded in any order and may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary cycling of other bytes within the
page does not occur.
4.4 DATA Polling
The AT28HC256 features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is
valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime
during the write cycle.
4
0007N–PEEPR–9/09
AT28HC256
4.5 Toggle Bit
In addition to DATA Polling the AT28HC256 provides another method for determining the end
of a write cycle. During the write operation, successive attempts to read data from the device
will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop
toggling and valid data will be read. Testing the toggle bit may begin at any time during the
write cycle.
4.6 Data Protection
If precautions are not taken, inadvertent writes to any 5-volt-only nonvolatile memory may
occur during transition of the host system power supply. Atmel® has incorporated both hard-
ware and software features that will protect the memory against inadvertent writes.
4.6.1 Hardware Protection
Hardware features protect against inadvertent writes to the AT28HC256 in the following ways:
(a) VCC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on
delay – once VCC has reached 3.8V the device will automatically time out 5 ms typical) before
allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write
cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not
initiate a write cycle.
4.6.2 Software Data Protection
A software controlled data protection feature has been implemented on the AT28HC256.
When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP
feature may be enabled or disabled by the user; the AT28HC256 is shipped from Atmel with
SDP disabled.
SDP is enabled by the host system issuing a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to “Software Data Protection” algo-
rithm). After writing the 3-byte command sequence and after tWC the entire AT28HC256 will be
protected against inadvertent write operations. It should be noted, that once protected the host
may still perform a byte or page write to the AT28HC256. This is done by preceding the data to
be written by the same 3-byte command sequence.
Once set, SDP will remain active unless the disable command sequence is issued. Power
transitions do not disable SDP and SDP will protect the AT28HC256 during power-up and
power-down conditions. All command sequences must conform to the page write timing spec-
ifications. It should also be noted that the data in the enable and disable command sequences
is not written to the device and the memory addresses used in the sequence may be written
with data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the three byte command
sequence will start the internal write timers. No data will be written to the device; however, for
the duration of tWC, read operations will effectively be polling operations.
4.7 Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes
may be written to or read from in the same manner as the regular memory array.
4.8 Optional Chip Erase Mode
The entire device can be erased using a 6-byte software code. Please see “Software Chip
Erase” application note for details.
5
0007N–PEEPR–9/09
AT28HC256
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
3. VH = 12.0V ± 0.5V.
5. DC and AC Operating Range
AT28HC256-70 AT28HC256-90 AT28HC256-12
Operating
Temperature (Case)
Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C
Mil. -55°C - 125°C -55°C - 125°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10%
6. Operating Modes
Mode CE OE WE I/O
Read VIL VIL VIH DOUT
Write(2) VIL VIH VIL DIN
Standby/Write Inhibit VIH X(1) X High Z
Write Inhibit X X VIH
Write Inhibit X VIL X
Output Disable X VIH X High Z
Chip Erase VIL VH(3) VIL High Z
7. Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
8. DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC + 1V 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
ISB1 VCC Standby Current TTL CE = 2.0V to VCC
AT28HC256-90, -12 3 mA
AT28HC256-70 60 mA
ISB2 VCC Standby Current CMOS CE = VCC - 0.3V to VCC AT28HC256-90, -12 300 µA
ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 80 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 6.0 mA 0.45 V
VOH Output High Voltage IOH = -4 mA 2.4 V
6
0007N–PEEPR–9/09
AT28HC256
10. AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
9. AC Read Characteristics
Symbol Parameter
AT28HC256-70 AT28C256-90 AT28HC256-12
UnitsMin Max Min Max Min Max
tACC Address to Output Delay 70 90 120 ns
tCE(1) CE to Output Delay 70 90 120 ns
tOE(2) OE to Output Delay 0 35 0 40 0 50 ns
tDF(3)(4) CE or OE to Output Float 035040050ns
tOH
Output Hold from OE, CE or Address,
whichever occurred first 000ns
7
0007N–PEEPR–9/09
AT28HC256
11. Input Test Waveforms and Measurement Level
12. Output Test Load
Note: 1. This parameter is characterized and is not 100% tested.
tR, tF < 5 ns
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 46pFV
IN = 0V
COUT 812pFV
OUT = 0V
8
0007N–PEEPR–9/09
AT28HC256
Note: 1. NR = No Restriction.
15. AC Write Waveforms
15.1 WE Controlled
15.2 CE Controlled
14. AC Write Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Setup Time 0 ns
tAH Address Hold Time 50 ns
tCS Chip Select Setup Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE)100ns
tDS Data Setup Time 50 ns
tDH, tOEH Data, OE Hold Time 0 ns
tDV Time to Data Valid NR(1)
9
0007N–PEEPR–9/09
AT28HC256
17. Page Mode Write Waveforms(1)(2)
Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
18. Chip Erase Waveforms
16. Page Mode Write Characteristics
Symbol Parameter Min Typ Max Units
tWC Write Cycle Time (option available) AT28HC256 5 10 ms
AT28HC256F 2 3 ms
tAS Address Setup Time 0 ns
tAH Address Hold Time 50 ns
tDS Data Setup Time 50 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Width 100 ns
tBLC Byte Load Cycle Time 150 µs
tWPH Write Pulse Width High 50 ns
tS = tH = 5 µsec (min.)
tW = 10 msec (min.)
VH = 12.0V ± 0.5V
10
0007N–PEEPR–9/09
AT28HC256
19. Software Data Protection
Enable Algorithm(1)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Write Protect state will be activated at end of write
even if no other data is loaded.
3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.
4. 1 to 64 bytes of data are loaded.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS
(4)
LOAD LAST BYTE
TO
LAST ADDRESS ENTER DATA
PROTECT STATE
WRITES ENABLED
(2)
20. Software Data Protection
Disable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS
(4)
LOAD LAST BYTE
TO
LAST ADDRESS
LOAD DATA 55
TO
ADDRESS 2AAA
EXIT DATA
PROTECT STATE
(3)
21. Software Protected Write Cycle Waveforms(1)(2)
Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
2. OE must be high only when WE and CE are both low.
11
0007N–PEEPR–9/09
AT28HC256
Notes: 1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics” on page 6.
23. Data Polling Waveforms
Notes: 1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics” on page 6.
25. Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
22. Data Polling Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 0 ns
tOEH OE Hold Time 0 ns
tOE OE to Output Delay(2) ns
tWR Write Recovery Time 0 ns
24. Toggle Bit Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
12
0007N–PEEPR–9/09
AT28HC256
26. Normalized ICC Graphs
13
0007N–PEEPR–9/09
AT28HC256
27. Ordering Information
27.1 Military Dual Marked Package
27.1.1 AT28HC256
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
90 80 0.3
AT28HC256-90DM/883
5962-88634 03 XX 28D6
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
AT28HC256-90FM/883
5962-88634 03 ZX 28F
AT28HC256-90LM/883
5962-88634 03 YX 32L
AT28HC256-90UM/883
5962-88634 03 UX 28U
120 80 0.3
AT28HC256-12DM/883
5962-88634 01 XX 28D6
AT28HC256-12FM/883
5962-88634 01 ZX 28F
AT28HC256-12LM/883
5962-88634 01 YX 32L
AT28HC256-12UM/883
5962-88634 01 UX 28U
Package Type
28D6 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip)
28F 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack)
32L 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC)
28U 28-pin, Ceramic Pin Grid Array (PGA)
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
EHigh Endurance Option: Endurance = 100K Write Cycles
FFast Write Option: Write Time = 3 ms
14
0007N–PEEPR–9/09
AT28HC256
Note: 1. No dual marking for this device.
27.1.2 AT28HC256E(1)
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
90 80 0.3
AT28HC256E-90DM/883 28D6
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
AT28HC256E-90FM/883 28F
AT28HC256E-90LM/883 32L
AT28HC256E-90UM/883 28U
120 80 0.3
AT28HC256E-12DM/883 28D6
AT28HC256E-12FM/883 28F
AT28HC256E-12LM/883 32L
AT28HC256E-12UM/883 28U
27.1.3 AT28HC256F
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
90 80 0.3
AT28HC256F-90DM/883
5962-88634 04 XX 28D6
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
AT28HC256F-90FM/883
5962-88634 04 ZX 28F
AT28HC256F-90LM/883
5962-88634 04 YX 32L
AT28HC256F-90UM/883
5962-88634 04 UX 28U
120 80 0.3
AT28HC256F-12DM/883
5962-88634 02 XX 28D6
AT28HC256F-12FM/883
5962-88634 02 ZX 28F
AT28HC256F-12LM/883
5962-88634 02 YX 32L
AT28HC256F-12UM/883
5962-88634 02 UX 28U
Package Type
28D6 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip)
28F 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack)
32L 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC)
28U 28-pin, Ceramic Pin Grid Array (PGA)
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
EHigh Endurance Option: Endurance = 100K Write Cycles
FFast Write Option: Write Time = 3 ms
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0007N–PEEPR–9/09
AT28HC256
27.2 Industrial Green Package Option (Pb/Halide-free)
27.3 Ordering Information Note
Previous datasheets included the low power suffixes L, LE and LF on the AT28HC256 for 120 ns and 90 ns speeds.
The low power parameters are now standard; therefore, the L, LE and LF suffixes are no longer required.
27.2.1 AT28HC256
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
70 80 0.3
AT28HC256-70JU 32J
Industrial
(-40°C to 85°C)
AT28HC256-70SU 28S
AT28HC256-70TU 28T
90 80 0.3
AT28HC256-90JU 32J
AT28HC256-90SU 28S
AT28HC256-90TU 28T
120 80 0.3
AT28HC256-12JU 32J
AT28HC256-12SU 28S
AT28HC256-12TU 28T
27.2.2 AT28HC256E
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
90 80 0.3
AT28HC256E-90JU 32J
Industrial
(-40°C to 85°C)
AT28HC256E-90SU 28S
AT28HC256E-90TU 28T
120 80 0.3
AT28HC256E-12JU 32J
AT28HC256E-12SU 28S
AT28HC256E-12TU 28T
27.2.3 AT28HC256F
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
90 80 0.3
AT28HC256F-90JU 32J Industrial
(-40°C to 85°C)
AT28HC256F-90SU 28S
AT28HC256F-90TU 28T
Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28T 28-lead, Plastic Thin Small Outline Package (TSOP)
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
EHigh Endurance Option: Endurance = 100K Write Cycles
FFast Write Option: Write Time = 3 ms
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0007N–PEEPR–9/09
AT28HC256
27.4 Die Products
Contact Atmel Sales for die sales options.
17
0007N–PEEPR–9/09
AT28HC256
28. Packaging Information
28.1 28D6 – Cerdip
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
28D6, 28-lead, 0.600" Wide, Non-windowed,
Ceramic Dual Inline Package (Cerdip) B
28D6
10/23/03
37.85(1.490)
36.58(1.440) PIN
1
15.49(0.610)
12.95(0.510)
0.127(0.005)MIN
1.52(0.060)
0.38(0.015)
0.66(0.026)
0.36(0.014)
1.65(0.065)
1.14(0.045)
15.70(0.620)
15.00(0.590)
17.80(0.700) MAX
0.46(0.018)
0.20(0.008)
2.54(0.100)BSC
5.08(0.200)
3.18(0.125)
SEATING
PLANE
5.72(0.225)
MAX
33.02(1.300) REF
0º~ 15º REF
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
MIL-STD 1835 D-10 Config A (Glass Sealed)
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0007N–PEEPR–9/09
AT28HC256
28.2 28F – Flatpack
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
28F, 28-lead, Non-windowed, Ceramic Bottom-brazed
Flat Package (FlatPack) B
28F
10/21/03
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
MIL-STD 1835 F-12 Config B
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0007N–PEEPR–9/09
AT28HC256
28.3 32J – PLCC
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
R
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B
32J
10/04/01
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 E2
B
e
E1 E
D1
D
D2
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
E 14.859 – 15.113
E1 13.894 – 14.046 Note 2
E2 12.471 – 13.487
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
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0007N–PEEPR–9/09
AT28HC256
28.4 32L – LCC
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32L, 32-pad, Non-windowed, Ceramic Lid, Leadless Chip
Carrier (LCC) B
32L
10/21/03
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
MIL-STD 1835 C-12
11.63(0.458)
11.23(0.442)
14.22(0.560)
13.72(0.540)
2.54(0.100)
2.16(0.085)
1.91(0.075)
1.40(0.055)
INDEX CORNER
0.635(0.025)
0.381(0.015) X 45˚
0.305(0.012)
0.178(0.007)RADIUS
0.737(0.029)
0.533(0.021)
1.02(0.040) X 45˚
PIN 1
1.40(0.055)
1.14(0.045)
2.41(0.095)
1.91(0.075)
2.16(0.085)
1.65(0.065)
7.62(0.300) BSC
1.27(0.050) TYP
10.16(0.400) BSC
21
0007N–PEEPR–9/09
AT28HC256
28.5 28S – SOIC
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC)
JEDEC Standard MS-013 B
28S
8/4/03
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
TOP VIEW
SIDE VIEWS
0.51(0.020)
0.33(0.013)
7.60(0.2992)
7.40(0.2914)
10.65(0.419)
10.00(0.394)
1.27(0.50) BSC
2.65(0.1043)
2.35(0.0926)
18.10(0.7125)
17.70(0.6969)
0.30(0.0118)
0.10(0.0040)
0.32(0.0125)
0.23(0.0091)
1.27(0.050)
0.40(0.016)
0º ~ 8º
PIN 1
22
0007N–PEEPR–9/09
AT28HC256
28.6 28T – TSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP) C
28T
12/06/02
PIN 1 0º ~ 5º
D1 D
Pin 1 Identifier Area
b
e
EA
A1
A2
c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.90 1.00 1.05
D 13.20 13.40 13.60
D1 11.70 11.80 11.90 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.55 BASIC
23
0007N–PEEPR–9/09
AT28HC256
28.7 28U – PGA
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
28U, 28-pin, Ceramic Pin Grid Array (PGA) B
28U
10/21/03
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
13.74(0.540)
13.36(0.526)
15.24(0.600)
14.88(0.586)
2.57(0.101)
2.06(0.081)
7.26(0.286)
6.50(0.256)
1.40(0.055)
1.14(0.045)
0.58(0.023)
0.43(0.017)
3.12(0.123)
2.62(0.103)
1.83(0.072)
1.57(0.062)
14.17(0.558)
13.77(0.542)
12.70(0.500) TYP
2.54(0.100) TYP
16.71(0.658)
16.31(0.642)
2.54(0.100) TYP
10.41(0.410)
9.91(0.390)
0007N–PEEPR–9/09
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