SCBS190F - JANUARY 1991 - REVISED SEPTEMBER 2003 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE 1D 2D 3D 4D 5D 6D 7D 8D 20 2D 1D OE VCC 1 SN54ABT573 . . . FK PACKAGE (TOP VIEW) 19 1Q 18 2Q 2 3 3D 4D 5D 6D 7D 17 3Q 16 4Q 4 5 15 5Q 14 6Q 6 7 13 7Q 12 8Q 8 9 10 11 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2Q 3Q 4Q 5Q 6Q 8D GND LE 8Q 7Q 20 VCC 1 LE OE 1D 2D 3D 4D 5D 6D 7D 8D GND JEDEC Standard JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) SN74ABT573A . . . RGY PACKAGE (TOP VIEW) OE SN54ABT573 . . . J OR W PACKAGE SN74ABT573A . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) D GND D D D Latch-Up Performance Exceeds 500 mA Per <1 V at VCC = 5 V, TA = 25C High-Drive Outputs (-32-mA IOH, 64-mA IOL) Ioff Supports Partial-Power-Down Mode Operation 1Q D Typical VOLP (Output Ground Bounce) description/ordering information These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. ORDERING INFORMATION Tube SN74ABT573AN SN74ABT573AN QFN - RGY Tape and reel SN74ABT573ARGYR AB573A Tube SN74ABT573ADW Tape and reel SN74ABT573ADWR SOP - NS Tape and reel SN74ABT573ANSR ABT573A SSOP - DB Tape and reel SN74ABT573ADBR AB573A Tube SN74ABT573APW Tape and reel SN74ABT573APWR TSSOP - PW VFBGA - GQN VFBGA - ZQN (Pb-free) -55C -55 C to 125 125C C TOP-SIDE MARKING PDIP - N SOIC - DW -40C to 85C ORDERABLE PART NUMBER PACKAGE TA ABT573A AB573A SN74ABT573AGQNR Tape and reel SN74ABT573AZQNR AB573A CDIP - J Tube SNJ54ABT573J SNJ54ABT573J CFP - W Tube SNJ54ABT573W SNJ54ABT573W LCCC - FK Tube SNJ54ABT573FK SNJ54ABT573FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) %(#"! "%' / 0 1 '' %$$! $ $!$( #'$!! *$,!$ $() '' *$ %(#"! %(#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCBS190F - JANUARY 1991 - REVISED SEPTEMBER 2003 description/ordering information (continued) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. SN74ABT573A . . . GQN OR ZQN PACKAGE (TOP VIEW) 1 2 3 terminal assignments 4 1 2 3 4 A A 1D OE B 3D 3Q VCC 2D 1Q B C C 5D 4D 5Q 4Q D D 7D 7Q 6D 6Q E E GND 8D LE 8Q 2Q FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 2 19 1D To Seven Other Channels Pin numbers shown are for the DB, DW, FK, J, N, NS, PW, RGY, and W packages. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1Q SCBS190F - JANUARY 1991 - REVISED SEPTEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT573 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT573A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W (see Note 2): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78C/W (see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 4) SN54ABT573 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC -24 Low-level output current t/v Input transition rise or fall rate High-level input voltage SN74ABT573A MIN 2 2 0.8 Input voltage 0 Outputs enabled V V 0.8 0 UNIT V VCC -32 mA V 48 64 mA 5 5 ns/V TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCBS190F - JANUARY 1991 - REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = -18 mA IOH = -3 mA VCC = 5 V, VCC = 4.5 V VOL VCC = 4.5 V Vhys II TA = 25C TYP MAX SN54ABT573 MIN MAX -1.2 SN74ABT573A MIN -1.2 MAX -1.2 2.5 2.5 2.5 IOH = -3 mA IOH = -24 mA 3 3 3 2 2 IOH = -32 mA IOL = 48 mA 2* IOL = 64 mA 0.55 0.55* Ioff ICEX IO VI = VCC or GND VO = 2.7 V VCC = 5.5 V, VCC = 0, VO = 0.5 V VI or VO 4.5 V VCC = 5.5 V, VCC = 5.5 V, VO = 5.5 V VO = 2.5 V 0.55 ICC ICC VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 1 10 -10 100 Outputs high VCC = 5.5 V, IO = 0, VI = VCC or GND V mV 1 10 -10 50 -50 V 2 0.55 VCC = 5.5 V, VCC = 5.5 V, UNIT V 100 IOZH IOZL Co MIN 50 -50 -180 -50 1 10 -10 A 100 A 50 A -180 mA A A -100 -180 Outputs high 1 250 250 250 A Outputs low 24 30 30 30 mA Outputs disabled 0.5 250 250 250 A 1.5 1.5 1.5 mA 3.5 pF 6.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. All typical values are at VCC = 5 V. This data sheet limit may vary among suppliers. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ABT573 VCC = 5 V, TA = 25C MIN 4 tw Pulse duration, LE high tsu Setup time, data before LE th Hold time, data after LE POST OFFICE BOX 655303 MIN UNIT MAX 3.3 3.3 High 1.9 2.5 Low 1.5 2.5 1 2.5 * DALLAS, TEXAS 75265 MAX ns ns ns SCBS190F - JANUARY 1991 - REVISED SEPTEMBER 2003 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN74ABT573A VCC = 5 V, TA = 25C MIN tw tsu Pulse duration, LE high Setup time, data before LE MIN UNIT MAX 3.3 3.3 High 1.9 1.9 Low 1.5 1.8 1.5 1.8 th Hold time, data after LE This data-sheet limit may vary among suppliers. MAX ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT573 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q VCC = 5 V, TA = 25C MIN MAX MIN TYP MAX 1.9 3.2 5.4 1.4 6.4 2.2 4.2 5.7 1.6 6.7 2.2 4 6.1 2 7.1 3.2 5.2 6.7 2.8 7.5 1.2 3.2 4.7 0.8 6.2 2.7 4.7 6.2 2 7.2 2.5 4.9 6.4 2.2 7.7 2 4.2 6 1.4 7 UNIT ns ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74ABT573A PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q VCC = 5 V, TA = 25C MIN MAX MIN TYP MAX 1.9 3.2 5.4 1.9 5.9 2.2 4.2 5.7 2.2 6.2 2.2 4 6.1 2.2 6.6 3.2 5.2 6.7 3.2 7.2 1.2 2.5 3.2 4.7 6.2 1.2 2.5 5.2 4.7 2.5 4.9 6.4 2.5 6.7 7.1 2 4.2 6 2 6.5 UNIT ns ns ns ns This data-sheet limit may vary among suppliers. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SCBS190F - JANUARY 1991 - REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION 500 From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V Input 1.5 V 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V 1.5 V 1.5 V VOL Output tPLZ 3.5 V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at Open (see Note B) VOL + 0.3 V VOL tPHZ tPZH VOH 1.5 V 1.5 V 0V Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL 1.5 V tPZL VOH Output 3V Output Control tPHL tPLH 1.5 V 1.5 V VOH - 0.3 V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9321901Q2A ACTIVE LCCC FK 20 1 TBD 5962-9321901QRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type 1 TBD Call TI N / A for Pkg Type TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type 5962-9321901QSA ACTIVE CFP W 20 SN74ABT573ADBLE OBSOLETE SSOP DB 20 SN74ABT573ADBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573AGQNR NRND GQN 20 1000 TBD SNPB Level-1-240C-UNLIM SN74ABT573AN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ABT573ANE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ABT573ANSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573APWLE OBSOLETE TSSOP PW 20 TBD Call TI SN74ABT573APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT573APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM BGA MI CROSTA R JUNI OR Addendum-Page 1 Call TI PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 Orderable Device Status (1) Package Type Package Drawing SN74ABT573ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74ABT573ARGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74ABT573AZQNR ACTIVE ZQN 20 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SNJ54ABT573FK ACTIVE LCCC FK 20 1 TBD SNJ54ABT573J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type SNJ54ABT573W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type BGA MI CROSTA R JUNI OR Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT573 : * Catalog: SN74ABT573 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ABT573ADBR SN74ABT573ADWR SN74ABT573AGQNR Package Package Pins Type Drawing SSOP SOIC BGA MI CROSTA R JUNI OR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 GQN 20 1000 330.0 12.4 3.3 4.3 1.5 8.0 12.0 Q1 SN74ABT573ANSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1 SN74ABT573APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 VQFN RGY 20 3000 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 ZQN 20 1000 330.0 12.4 3.3 4.3 1.5 8.0 12.0 Q1 SN74ABT573ARGYR SN74ABT573AZQNR BGA MI CROSTA R JUNI OR Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT573ADBR SSOP DB 20 2000 346.0 346.0 33.0 SN74ABT573ADWR SOIC DW 20 2000 346.0 346.0 41.0 SN74ABT573AGQNR BGA MICROSTAR JUNIOR GQN 20 1000 346.0 346.0 29.0 SN74ABT573ANSR SO NS 20 2000 346.0 346.0 41.0 SN74ABT573APWR TSSOP PW 20 2000 346.0 346.0 33.0 SN74ABT573ARGYR VQFN RGY 20 3000 190.5 212.7 31.8 SN74ABT573AZQNR BGA MICROSTAR JUNIOR ZQN 20 1000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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