LTC4376
1
Rev. A
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TYPICAL APPLICATION
FEATURES DESCRIPTION
7A Ideal Diode with
Reverse Input Protection
The LT C
®
4376 is a 7A ideal diode that uses an internal
15mΩ N-channel MOSFET to replace a Schottky diode
when used in diode-OR and high current diode applica-
tions. The LTC4376 reduces power consumption, heat
dissipation and PC board area.
The LTC4376 controls the forward voltage drop across
the internal MOSFET to ensure smooth current delivery
without oscillation even at light loads. If a power source
fails or is shorted, a fast turn-off minimizes reverse cur-
rent transients. The LTC4376 also easily ORs power
sources to increase total system reliability.
With its low operating voltage, small solution size and the
ability to withstand reverse input voltage, the LTC4376
excels in portable battery applications. A shutdown mode
is available to reduce the quiescent current to 9μA. The
SHDN pin can also control the forward current path when
an external MOSFET is used in series with the internal
MOSFET in a back-to-back configuration.
12V, 7A Ideal Diode
Power Dissipation vs Load Current
APPLICATIONS
n Reduces Power Dissipation by Replacing a Power
Schottky Diode
n Wide Operating Voltage Range: 4V to 40V
n Internal 15mΩ N-Channel MOSFET
n Reverse Input Protection to –40V
n Low 9μA Shutdown Current
n Low 150μA Operating Current
n Smooth Switchover without Oscillation
n Available in 16-Pin 5mm × 4mm DFN Package
n AEC-Q100 Qualified for Automotive Applications
n Automotive Battery Protection
n Redundant Power Supplies
n Portable Battery Devices
n Computer Systems/Servers
All registered trademarks and trademarks are the property of their respective owners.
4376 TA01a
IN
CS
INK
SHDN
OUT
OUTK
VSS
LTC4376
V
OUT
12V
7A
VIN
12V
LTC4376
SCHOTTKY
MBR1045CT
POWER
SAVED
CURRENT (A)
0
1
2
3
4
5
6
7
0
1
2
3
4
POWER DISSIPATION (W)
4376 TA01b
LTC4376
2
Rev. A
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
IN, INK, CS, SHDN ...................................... –40V to 80V
OUT, OUTK ................................................. –0.3V to 80V
INK–OUTK ................................................. –45V to 100V
INK–CS ..........................................................–1V to 80V
IN–OUT (Note 3) ........................................ –45V to 0.3V
GATE (Note 4) ...........................VCS – 0.3V to VCS + 10V
Operating Junction Temperature Range
LTC4376C ................................................ 0°C to 70°C
LTC4376I .............................................–40°C to 85°C
LTC4376H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
16
15
14
13
12
11
10
9
17
OUT
1
2
3
4
5
6
7
8
IN
IN
IN
IN
SHDN
NC
INK
CS
IN
IN
IN
IN
NC
VSS
OUTK
GATE
DHD PACKAGE
16-LEAD (5mm × 4mm) PLASTIC DFN
JMAX = 150°C, θJA = 43°C/W, θJC
ORDER INFORMATION
TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4376CDHD#PBF LTC4376CDHD#TRPBF 4376 16-Lead (5mm x 4mm) Plastic DFN 0°C to 70°C
LTC4376IDHD#PBF LTC4376IDHD#TRPBF 4376 16-Lead (5mm x 4mm) Plastic DFN –40°C to 85°C
LTC4376HDHD#PBF LTC4376HDHD#TRPBF 4376 16-Lead (5mm x 4mm) Plastic DFN –40°C to 125°C
AUTOMOTIVE PRODUCTS**
LTC4376IDHD#WPBF LTC4376IDHD#WTRPBF 4376 16-Lead (5mm x 4mm) Plastic DFN –40°C to 85°C
LTC4376HDHD#WPBF LTC4376HDHD#WTRPBF 4376 16-Lead (5mm x 4mm) Plastic DFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
thesemodels.
LTC4376
3
Rev. A
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Note 1: Stresses beyond those listed underAbsolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, all voltages are referenced to
VSS unless otherwise specified.
Note 3: This voltage is set by the MOSFET’s body diode and will safely
exceed 0.3V during start-up for a limited time determined by the body
diode thermal dissipation.
Note 4: An internal clamp limits the GATE pin to a minimum of 10V above
CS or 90V above VSS. Driving this pin to voltages beyond the clamp may
damage the device.
Note 5: The IAS typical value is based on characterization and is not
production tested.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VINK = 4V to 40V, VIN = VINK, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VINK Operating Supply Range l4 40 V
IINK INK Pin Current INK = 12V
INK = OUTK = 12V, SHDN = 0V
INK = OUTK = 24V, SHDN = 0V
INK = –40V
l
l
l
l
0
150
9
15
–15
250
30
40
–40
µA
µA
µA
µA
IOUTK OUTK Pin Current INK = 12V, In Regulation
INK = 12V, ∆VSD = –1V
INK = OUTK = 12V, SHDN = 0V
INK = OUTK = 24V, SHDN = 0V
OUTK = 12V, INK = SHDN = 0V
l
l
l
l
l
3 5
120
0.8
0.8
6
7.5
220
3
3
15
µA
µA
µA
µA
µA
ICS CS Pin Current INK = 12V, ∆VSD = –1V
INK = CS = 12V, SHDN = 0V
CS = –40V
l
l
l
1
–0.4
150
4
–0.8
200
15
–1.5
µA
µA
mA
IOUT OUT Reverse Leakage Current IN = GATE = 0V, OUT = 40V l150 µA
∆VGATE Gate Drive (VGATE – VCS) INK = 4V, IGATE = 0, –1µA
INK = 8V to 40V, IGATE = 0, –1µA
l
l
4.5
10
5.5
12
18
18
V
V
∆VSD(REG) Source-Drain Regulation Voltage (VINK – VOUTK) 1mA < IIN < 100mA l20 30 45 mV
∆VSD(FWD) Body Diode Forward Voltage Drop (VIN – VOUT) IIN = 7A, MOSFET Off l0.55 0.77 1 V
RDS(ON) Internal N-Channel MOSFET On Resistance IIN = 7A l15 30 mΩ
IAS Peak Avalanche Current L = 0.1mH (Note 5) 40 A
IGATE(UP) Gate Pull-Up Current GATE = INK, ∆VSD = 0.1V l–6 –10 –17 µA
I
GATE(DOWN)
Gate Pull-Down Current Fault Condition, ∆VGATE = 5V, ∆VSD = –1V
Shutdown Mode, ∆VGATE = 5V, ∆VSD = 0.7V
l
l
70
0.6
130 180 mA
mA
tOFF Gate Turn-Off Delay Time ∆VSD = 0.1V to –1V, ∆VGATE < 2V l0.3 0.5 µs
VSHDN(TH) SHDN Pin Input Threshold INK = 4V to 40V l0.6 1.2 2 V
VSHDN(FLT) SHDN Pin Float Voltage INK = 4V to 40V l0.6 1.75 2.5 V
ISHDN SHDN Pin Current SHDN = 0.5V
SHDN = –40V
l
l
–0.5
–0.4
–3
–0.8
–5
–1.5
µA
mA
ILEAK SHDN Leakage Current SHDN = 2.6V l1 µA
VCS(TH) Reverse CS Threshold for GATE Off GATE = 0V, IGATE(DOWN) = 1mA l–0.9 –1.8 –2.7 V
LTC4376
4
Rev. A
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CS Current vs
Forward Voltage Drop
OUTK Current vs
Forward Voltage Drop
Total Negative Current vs
Negative Input Voltage
V
CS
= 40V
V
CS
= 12V
V
CS
= 4V
∆V
SD
(V)
–1
–0.5
0
0.5
1
–50
0
50
100
150
200
I
CS
(µA)
4376 G04
V
INK
= 40V
V
INK
= 12V
V
INK
= 4V
∆V
SD
(V)
–1
–0.5
0
0.5
1
0
40
80
120
160
I
OUTK
(µA)
4376 G05
INK = CS =
SHDN
VOLTAGE (V)
0
–10
–20
–30
–40
0
–0.5
–1.0
–1.5
–2.0
I
INK
+ I
CS
+ I
SHDN
(mA)
4376 G06
TYPICAL PERFORMANCE CHARACTERISTICS
INK Current in Regulation INK Current in Shutdown CS Current in Shutdown
V
INK
(V)
0
10
20
30
40
0
50
100
150
200
I
INK
(µA)
4376 G01
INK = CS = OUTK
SHDN = 0V
V
INK
(V)
0
10
20
30
40
0
10
20
30
40
I
INK
(µA)
4376 G02
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
INK = CS = OUTK
SHDN = 0V
V
CS
(V)
0
10
20
30
40
0
2
4
6
8
10
I
CS
(µA)
4376 G03
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
LTC4376
5
Rev. A
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GATE Current vs
Forward Voltage Drop GATE Drive vs GATE Current
Forward Voltage Drop vs
Load Current
∆V
SD
(mV)
–50
0
50
100
150
40
30
20
10
0
–10
–20
I
GATE
(µA)
4376 G07
VINK = VIN = 12V
VGATE = VIN + 2.5V
V
INK
> 12V
V
INK
= 8V
V
INK
= 4V
INK = CS
I
GATE
(µA)
0
–5
–10
–15
0
5
10
15
∆V
GATE
(V)
4376 G08
V
IN
= 40V
V
IN
= 4V
I
LOAD
(A)
0
1
2
3
4
5
6
7
0
20
40
60
80
100
120
∆V
SD
(mV)
4376 G09
TYPICAL PERFORMANCE CHARACTERISTICS
MOSFET RDS(ON) vs Temperature
FET Turn-Off Time vs
Initial Overdrive
FET Turn-Off Time vs
Final Overdrive
V
IN
= 40V
V
IN
= 4V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
5
10
15
20
25
R
DSON
(mΩ)
4376 G10
V
INITIAL
(V)
0
0.2
0.4
0.6
0.8
1
0
50
100
150
200
250
300
4376 G11
tPD (ns)
VINK = 12V
∆VSD = VINITIAL –1V
V
FINAL
(V)
0
–0.2
–0.4
–0.6
–0.8
–1
0
500
1000
1500
2000
4376 G12
tPD (ns)
VINK = 12V
∆VSD = 45mV VFINAL
LTC4376
6
Rev. A
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PIN FUNCTIONS
CS: Gate Drive Return. The fast pull-down current is
returned through this pin during a reverse current event.
This pin can be connected to IN or left open.
GATE: Gate Drive Output. The GATE pin pulls high, enhanc-
ing the N-channel MOSFET when the load current creates
more than 30mV of voltage drop across the MOSFET.
When the load current is small, GATE is actively driven
to maintain 30mV across the MOSFET. If reverse current
flows, a fast pull-down circuit quickly connects GATE to
the CS pin within 300ns, turning off the MOSFET. Connect
this pin to the gate of the external MOSFET in a back-to-
back configuration, otherwise leave open.
IN: Source of Internal N-Channel MOSFET. IN is the anode
of the ideal diode.
INK: Voltage Sense and Supply Voltage. The voltage
sensed at this pin is used to control the MOSFET voltage
drop. Connect this pin to IN.
NC: No Connection. Not internally connected.
OUT: The exposed pad is the drain of the internal N-channel
MOSFET. OUT is the cathode of the ideal diode and the
common output when multiple LTC4376s are configured
as an ideal diode-OR.
OUTK: Drain Voltage Sense. The voltage sensed at this
pin is used to control the MOSFET voltage drop. Connect
this pin to OUT.
SHDN: Shutdown Control Input. The LTC4376 can be shut
down to a low current mode by pulling the SHDN pin
below 0.6V. Pulling this pin above 2V turns the part on.
The SHDN pin can be pulled up to 40V or below VSS by
40V without damage. If the shutdown feature is not used,
connect SHDN to IN.
VSS: Device Ground.
BLOCK DIAGRAM
INK
–1.7V
M1
15mΩ
–
+
NEGATIVE
COMP
–
+
FPD
COMP
IN
GATE
OUT
VSS
4376 BD
CS
INK
OUTK
SHDN
+
–
–
+
GATE
AMP
+
–
30mV 30mV
3µA
CHARGE PUMP
f = 500kHz
SHUTDOWN
LTC4376
7
Rev. A
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OPERATION
The LTC4376 is a single positive voltage ideal diode con-
troller that drives an internal N-channel MOSFET as a
pass transistor to replace a Schottky diode. The IN and
OUT pins form the anode and cathode of the ideal diode,
respectively. The input supply is connected to the IN
pins, while the OUT pin serves as the output. Both the
INK and OUTK pins are connected directly to IN and OUT
respectively.
The GATE amplifier (see Block Diagram) senses across INK
and OUTK and drives the gate of the internal MOSFET to
regulate the forward voltage to 30mV. As the load current
increases, GATE is driven higher until a point is reached
where the internal MOSFET is fully on. Further increases
in load current result in a forward drop of RDS(ON)•ILOAD.
If the load current is reduced, the GATE amplifier drives
the MOSFET gate lower to maintain a 30mV drop. If the
input voltage is reduced to a point where a forward drop
of 30mV cannot be supported, the GATE amplifier drives
the MOSFET off.
Blocking diodes are commonly placed in series with
supply inputs for the purpose of ORing redundant power
sources and protecting against supply reversal. The
LTC4376 replaces diodes in these applications to reduce
both the voltage drop and power loss associated with a
passive solution.
The LTC4376 has a wide operating range of 4V to 40V
which allows operation during cold crank conditions and
transient conditions. The LTC4376 also protects against
negative inputs to –40V, which can occur when the auto-
motive battery is reversed.
A 12V/7A ideal diode application is shown in Figure1a.
Ideal diodes, like their non-ideal counterparts, exhibit a
behavior known as reverse recovery. In combination with
In the event of a rapid drop in input voltage, such as an
input short-circuit fault or negative-going voltage spike,
reverse current briefly flows through the MOSFET until it
shuts off. This current is provided by any load capacitance
and by other supplies or batteries that feed the output in
diode-OR applications. The FPD COMP (Fast Pull-Down
Comparator) quickly responds to this condition by turning
the MOSFET off in 300ns, thus minimizing the disturbance
to the output bus.
The IN, INK, CS, GATE and SHDN pins are protected
against reverse inputs of up to –40V. The NEGATIVE
COMP detects negative input potentials at the CS pin and
quickly pulls GATE to CS, turning off the MOSFET and
isolating the load from the negative input.
When pulled low, the SHDN pin turns off most of the
internal circuitry, reducing the quiescent current to 9µA
and holding the MOSFET off. The SHDN pin may be either
driven high or pulled up with a resistor of 1MΩ or less
to enable the LTC4376. In applications where an external
MOSFET is used in series with the internal MOSFET, the
SHDN pin serves as an on/off control for the forward path,
as well as enabling the diode function.
parasitic or intentionally introduced inductances, reverse
recovery spikes may be generated by an ideal diode dur-
ing commutation. D1, D2 and R1 protect against these
spikes which might otherwise exceed the LTC4376’s –40V
to 40V survival rating. If reverse input protection is not
needed, Figure1a can be simplified to Figure1b. D1 and
COUT absorb the reverse recovery energy and protect the
LTC4376. Spikes and protection schemes are discussed
in detail in the Input Short-Circuit Faults section.
It is important to note that the SHDN pin, while dis-
abling the LTC4376 and reducing its current consump-
tion to 9µA, does not disconnect the load from the input
since the internal MOSFET’s body diode is ever-present.
Adding an external MOSFET permits use in load switching
applications.
APPLICATIONS INFORMATION
LTC4376
8
Rev. A
For more information www.analog.com
Figure1a.
4376 F01a
IN
CS
INK
SHDN
OUT
OUTK
VSS
LTC4376
D1
SMAJ24CA
24V COUT
47nF
VOUT
12V
7A
VIN
12V
R1
1k
12V/7A Ideal Diode with Reverse Input Protection
Figure1b.
4376 F01b
IN
CS
INK
SHDN
OUT
OUTK
VSS
LTC4376
COUT
100µF
VOUT
12V
7A
VIN
12V
D1
SBR1U150SA
12V/7A Ideal Diode without Reverse Input Protection
Shutdown Mode
In shutdown, the LTC4376 pulls GATE low to CS, turning
off the internal MOSFET and reducing its current consump-
tion to 9µA. Shutdown does not interrupt forward current
flow, a path is still present through the internal MOSFET’s
body diode. A second external MOSFET is needed to block
the forward path; see the section Load Switching and
Inrush Control. When enabled, the LTC4376 operates as
an ideal diode. If shutdown is not needed, connect SHDN
to IN. SHDN may be driven with a 3.3V or 5V logic signal
or pulled up with an external resistor to IN. To enable
the part, SHDN must be pulled up to at least 2V. Use
a resistor value that provides more than the SHDN pin
leakage current of 1µA at 2.6V. A value of 1MΩ or less
is sufficient to turn the part on. To assert SHDN low, the
pull-down must sink at least 5µA plus the current pro-
vided by the external pull-up resistor at 500mV. When a
high impedance pull-up resistor is used, SHDN is subject
to capacitive coupling from nearby clock lines or traces
exhibiting high dV/dt. Bypass SHDN to VSS with 10nF to
eliminate injection. Figure2 is the simplest way to control
the shutdown pin. Since the control signal ground is dif-
ferent from the SHDN pin reference, VSS, there could be
momentary glitches on SHDN during transients. Figure3
APPLICATIONS INFORMATION
and Figure4 are alternative solutions that level-shift the
control signal and eliminate glitches.
Figure2.
OFFON
4376 F02
SHDN
VSS
LTC4376
R1
1k
M1
BSS123
SHDN Control
Figure3.
ON
OFF
4376 F03
IN
SHDN
VSS
LTC4376
Q1
2N5551
24V
R1
1k
Q2
2N5401
R4
240k
R2
100k
R5
240k
R3
100k
Transistor SHDN Control
Figure4.
OFFON
4376 F04
IN
SHDN
VSS
LTC4376
24V
R1
1k
R4
2k
R2
1M
R3
2M
MOC
207M
Opto-Isolator SHDN Control
Input Short-Circuit Faults
The dynamic behavior of an active, ideal diode entering
reverse bias is most accurately characterized by a delay
followed by a period of reverse recovery. During the delay
phase some reverse current is built up, limited by parasitic
resistances and inductances. During the reverse recovery
phase, energy stored in the parasitic inductances is trans-
ferred to other elements in the circuit. Current slew rates
during reverse recovery may reach 100A/µs or higher.
LTC4376
9
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
High slew rates coupled with parasitic inductances in
series with the input and output paths may cause poten-
tially destructive transients to appear at the IN, CS and
OUT pins of the LTC4376 during reverse recovery. A zero
impedance short-circuit directly across the input and
ground is especially troublesome because it permits the
highest possible reverse current to build up during the
delay phase. When the internal MOSFET finally turns off
to interrupt the reverse current, the LTC4376 IN and CS
pins experience a negative voltage spike while the OUT
pin spikes in the positive direction.
To prevent damage to the LTC4376 under conditions of
input short-circuit, protect the IN, CS and OUT pins as
shown in Figure5. The IN and CS pins are protected by
clamping to the VSS pin with a Tranzorb or TVS. For input
voltages 24V and greater, D3 is needed to protect the inter-
nal MOSFET’s gate oxide during input short-circuit condi-
tions. Negative spikes, seen after the MOSFET turns off
during an input short, are clamped by D2, a 24V TVS. D2
allows reverse inputs to 24V while keeping the MOSFET
off and is not required if reverse input protection is not
needed. D1 blocks D2 from conducting during normal
operation. When the input short condition disappears,
the current stored in the source parasitic inductance, LS,
flows through the body diode of the MOSFET charging
up CLOAD. If CLOAD is small or nonexistent, both the IN/
CS and OUT pins may rise to a level that can damage
the LTC4376. In this case, D1 will need to be a TVS or
TransZorb to limit the voltage difference between the IN/
CS and VSS pins.
OUT is protected by the MOSFET’s avalanche breakdown.
Nevertheless, the MOSFET could be damaged by exces-
sive current in applications greater than 24V. If the input
is greater than 24V, then a 28V TVS (SMAJ28A) or a snub-
ber can be used to protect the MOSFET and OUT pin. The
snubber allows applications up to 40V (see Figure13).
COUT and R1 preserve the fast turn-off time when output
parasitic inductance causes the IN and OUT voltages to
drop quickly.
Paralleling Supplies
Multiple LTC4376s can be used to combine the outputs of
two or more supplies for redundancy or for droop sharing,
as shown in Figure6. For redundant supplies, the supply
with the highest output voltage sources most or all of the
load current. If this supply’s output is quickly shorted to
ground while delivering load current, the flow of current
temporarily reverses and flows backwards through the
LTC4376’s internal MOSFET. The LTC4376 senses this
reverse current and activates a fast pull-down to quickly
turn off the MOSFET.
If the other, initially lower supply was not delivering any
load current at the time of the fault, the output falls until
the body diode of its ORing internal MOSFET conducts.
Meanwhile, the LTC4376 charges the internal MOSFET
gate with 10µA until the forward drop is reduced to 30mV.
If this supply was sharing load current at the time of the
fault, its associated ORing internal MOSFET was already
driven partially on. In this case, the LTC4376 will simply
Figure5.
D4*
SMAJ28A
* OPTIONAL FOR VIN > 24V
4376 F05
IN
CS
GATE
INK
SHDN
OUT
OUTK
VSS
LTC4376
D2
SMAJ24A
24V
D1
1N4148
D3
DDZ9699T
12V
COUT
>1.5µF
CLOAD
V
OUT
V
IN
R1
1k
LOUT
OUTPUT PARASITIC
INDUCTANCE
REVERSE
RECOVERY CURRENT
INPUT
SHORT
LIN
INPUT PARASITIC
INDUCTANCE
LS
SOURCE PARASITIC
INDUCTANCE
Reverse Recovery Produces Inductive Spikes at the IN, CS and OUT Pins. The Polarity of
Step Recovery Is Shown Across Parasitic Inductances
LTC4376
10
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
drive the internal MOSFET gate harder in an effort to main-
tain a drop of 30mV.
Droop sharing can be accomplished if both power supply
output voltages and output impedances are nearly equal.
The 30mV regulation technique ensures smooth load shar-
ing between outputs without oscillation. The degree of shar-
ing is a function of internal MOSFET R
DS(ON)
, the output
impedance of the supplies and their initial output voltages.
Load Switching and Inrush Control
By adding an external MOSFET as shown in Figure7,
the LTC4376 can be used to control power flow in the
forward direction while retaining ideal diode behavior in
the reverse direction. The body diodes of both the exter-
nal and internal MOSFETs prohibit current flow when the
MOSFETs are off. The internal MOSFET serves as the ideal
diode, while the external MOSFET, M1, acts as a switch
to control forward power flow. On/Off control is provided
by the SHDN pin, and C1 and R3 may be added if inrush
control is desired.
When SHDN is driven high and provided VIN>VOUT+30mV,
GATE sources 10µA and gradually charges C1, pulling up
both MOSFET gates. The external MOSFET operates as
source follower and
IINRUSH =
10µA • C
LOAD
C1
Figure6.
4376 F06
IN
CS
INK
SHDN
OUT
OUTK
VSS
LTC4376
D1B
SMAJ24CA
24V COUTB
1.5µF
VINB = 12V
PSB
RTNB
R1B
1k
IN
CS
INK
SHDN
OUT
OUTK
VSS
LTC4376
D1A
SMAJ24CA
24V COUTA
1.5µF
12V
7A
BUS
VINA = 12V
PSA
RTNA
R1A
1k
Redundant Power Supplies
Figure7.
4376 F07
IN
CS
GATE
INK
SHDN
OUT
OUTK
VSS
LTC4376
D2
SMAJ24A
24V
D1
SMAJ40A
40V
D3
DDZ9699T
12V
COUT
1.5µF
CLOAD
V
OUT
28V
7A
VIN
28V
R1
1k
OFFON
R2
10Ω
R3
10k
C1
10nF
M1
PSMN005-75B
28V Load Switch and Ideal Diode with Reverse Input Protection
LTC4376
11
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
If VIN<VOUT+30mV, the LTC4376 will be activated but
holds both the MOSFETs off until the input exceeds the
output by 30mV. In this way, normal diode behavior of
the circuit is preserved, but with soft starting when the
diode turns on.
When SHDN is pulled low, GATE pulls both the MOSFET
gates down quickly to CS turning off both forward and
reverse paths, and the input current is reduced to 9µA.
While C1 and R3 may be omitted if soft starting is not
needed, R2 is necessary to prevent MOSFET parasitic
oscillations and must be placed close to the external
MOSFET, M1.
Layout Considerations
The following advice should be considered when laying
out a printed circuit board for the LTC4376: The INK and
OUTK pins should be connected as close as possible to
the IN and OUT pins respectively for good accuracy. The
PCB traces associated with the power path through the
MOSFET should have low resistance. Keep the traces
to the IN and OUT wide and short to minimize resistive
losses. To ensure a low resistance contact, solder the
device’s OUT pin to the board using a reflow process. The
wide OUT trace also acts as a heat sink to remove the heat
from the device at high current load. Place COUT, surge
suppressors and necessary transient protection compo-
nents close to the LTC4376 using short lead lengths. See
Figure8 for the recommended layout. The temperature
rise of the recommended layout with 7A is 50°C.
Figure9 through Figure16 show typical applications of
the LTC4376.
Figure8.
4376 F08
IN
IN
IN
IN
IN
IN
IN
IN
NC
SHDN
INK
CS
NC
OUTK
GATE
VSS
OUT
17
LTC4376DHD
16
15
1
2
14
3
13
4
12
5
11
6
10
7
9
8
VOUT
VIN
VSS
COUT
Recommended Layout for DFN Package
LTC4376
12
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Figure9. 1.2V Diode-OR
Figure10. Lossless Solar Panel Isolation
4376 F09
IN
CS
INK
SHDN
OUT
OUTK
VSS
LTC4376
COUTB
47nF
V
INB
1.2V
R1B
1k
IN
CS
INK
SHDN
OUT
OUTK
VSS
LTC4376
COUTA
47nF
V
OUT
1.2V
7A
CLOAD
V
INA
1.2V
R1A
1k
–12V
–12V
4376 F10
IN
CS
INK
SHDN
OUT
OUTK
VSS
LTC4376
12V
BATTERY
SHUNT
REGULATOR
80W
SOLAR
PANEL
LOAD
+
LTC4376
13
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Figure12. 12V Load Switch and Ideal Diode with Precise Undervoltage Lockout
4376 F12
IN
CS
GATE
INK
SHDN
OUT
OUTK
VSS
LTC4376
D1
SMAJ24CA
24V
DDZ9697T
10V
2M8.2M
1M
UV = 10.8V
COUT
1.5µF
V
OUT
12V
7A
VIN
12V
R1
1k
R2
10Ω
M1
PSMN005-75B
+
–
IN+
IN–
HYST
REF
V–GND
LTC1540
Figure11. 12V Load Switch and Ideal Diode with Reverse Input Protection
4376 F11
IN
CS
GATE
INK
SHDN
OUT
OUTK
VSS
LTC4376
D1
SMAJ24CA
24V
COUT
47nF
D4
S1B
CLOAD
V
OUT
12V
7A
VIN
12V
R1
1k
ON
OFF
R2
10Ω
R3
10k
C1
10nF
M1
PSMN005-75B
LTC4376
14
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Figure13. 24V/7A Ideal Diode with Reverse Input Protection to VIN < VOUT – 40V
Figure14. 24V Load Switch without Ideal Diode Function
C1*
0.47µF
*OPTIONAL FOR VIN > 24V
4376 F13
IN
CS
GATE
INK
SHDN
OUT
OUTK
VSS
LTC4376
D2
SMAJ24A
24V
D1
SMAJ40A
40V
D3
DDZ9699T
12V
COUT
1.5µF
V
OUT
24V
7A
VIN
24V
R1
1k
D5*
1N4148
D4*
ES1A
R2*
1k
ON
OFF
4376 F14
OUT
CS
INK
GATE
IN
OUTK
VSS
LTC4376
D1
SMAJ40A
40V
D3
DDZ9699T
12V
CLOAD
R3
10k
C1
10nF
VOUT
24V
7A
VIN
24V
SHDN
LTC4376
15
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Figure15. Diode-OR with Selectable Power Supply Feeds and Reverse Input Protection
Figure16. Overvoltage Protector and Ideal Diode Blocks Reverse Input Voltage
*DECREASES GATE RAMP TIME BY BIASING CSX NEAR VINX
100k PATH TO VOUT IF VOUT < VINX
IN
CS
GATE
INK
SHDN
OUT
OUTK
VSS
LTC4376
COUTA
1.5µF
CLOAD
VOUT
12V
7A
VINA
12V
R1A
1k
ON
OFF
M1A
PSMN005-75B
R5A*
100k
4376 F15
IN
CS
GATE
INK
SHDN
OUT
OUTK
VSS
LTC4376
D1B
SMAJ24CA
24V
D1A
SMAJ24CA
24V
COUTB
1.5µF
VINB
12V
R1B
1k
ON
OFF
M1B
PSMN005-75B
R5B*
100k
4376 F16
IN
CS
INK
SHDN
SHDN
UV
OV
FB
ENOUT
F LT
OUT
OUTK
VSS
LTC4376
D1
SMAJ24CA
24V COUT
47nF
5A OUTPUT
(CLAMPED AT 16V)
VIN
12V
R1
1k
VCC GATE SNS
GND TMR
OUT
10Ω
10mΩFDD16AN08A0
57.6k
4.99k
0.1µF
22µF
LT4363
–27V TO 27V DC SURVIVAL
–40V TO 80V TRANSIENT SURVIVAL
LTC4376
16
Rev. A
For more information www.analog.com
PACKAGE DESCRIPTION
4.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
2.44 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
4.34 ±0.10
(2 SIDES)
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DHD16) DFN REV A 1113
0.25 ±0.05
PIN 1
NOTCH
0.50 BSC
4.34 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
2.44 ±0.05
(2 SIDES)
3.10 ±0.05
0.50 BSC
0.70 ±0.05
4.50
±0.05
PACKAGE
OUTLINE
0.25 ±0.05
DHD Package
16-Lead Plastic DFN (5mm × 4mm)
(Reference LTC DWG # 05-08-1707 Rev A)
LTC4376
17
Rev. A
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/19 Added AEC-Q100. 1, 2
LTC4376
18
Rev. A
For more information www.analog.com
ANALOG DEVICES, INC. 2018-2019
08/19
www.analog.com
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Input Diode for Supply Hold-Up on Plug-In Card
4376 TA02
IN
CS
GATE
INK
SHDN
OUT
OUTK
VSS
LTC4376
SMAJ40A
40V
DDZ9699T
12V
1.5µF
+
C
HOLDUP
VOUT1
GND
24V
1k
BACKPLANE
PLUG-IN
CARD
LTC4260
HOT SWAP
CONTROLLER