TB6556FG TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB6556FG 3-Phase Full-Wave Sine-Wave PWM Brushless Motor Controller The TB6556FG is designed for motor fan applications for three-phase brushless DC (BLDC) motors. Features Sine-wave PWM control Built-in triangular-wave generator (Carrier cycle = fOSC/252 (Hz)) Built-in lead angle control function (0 to 58 in 32 steps) External setting/automatic internal setting Built-in dead time function (setting 1.9 s or 3.8 s) Overcurrent protection signal input pin Built-in regulator (Vrefout = 5 V (typ.), 30 mA (max)) Operating supply voltage range: VCC = 6 V to 10 V Weight: 0.63 g (typ.) 1 2012-10-22 TB6556FG Block Diagram Gin Gout PH LPF LA UL LL 24 25 26 27 28 30 29 Peak hold + Upper limit Filter Lower limit Xin 14 System clock generator Xout 15 6-bit triangular wave generator HU 21 Comparator Phase U Position detector HV 20 Ve 2 Regulator 9 U Counter HW 19 VCC 1 10 Td 5-bit AD Internal Phase reference matching voltage Output waveform generator Data select Phase W Charger FG Comparator Rotating direction CW/CCW 18 SS 22 PWM HU HV HW RES 11 Idc 3 8 V 5 Y 7 W GND 13 Power-on reset Setting dead time Comparator 120/180 Vrefout 23 6 X Comparator Phase V ST/SP CW/CCW Protection ERR & GB reset Switching 120/180 and gate block protection on/off 4 Z 12 OS 120turn-on matrix FG 17 REV 16 Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2 2012-10-22 TB6556FG Pin Description Pin No. Symbol Description 21 HU Positional signal input pin U 20 HV Positional signal input pin V 19 HW Positional signal input pin W 18 CW/CCW 11 RES 2 Ve 24 Gin 25 Gout 26 Remarks When positional signal is HHH or LLL, gate block protection operates. With built-in pull-up resistor, built-in digital filter ( 500 ns) Rotation direction signal input pin L: Forward H: Reverse Reset-signal-input pin L: Reset (output is non-active) operation/halt operation, also used for gate protection, built-in pull-up resistor Voltage command signal With built-in pull-down resistor Gain setting Idc signal level at a gain that optimizes the LA PH Peak hold Connect the peak-hold capacitor and discharge resistor to GND, parallel to each other 27 LPF RC low-pass filter Connect the low-pass filter capacitor (built-in 100 k resistor) 28 LA Lead angle setting signal input pin Sets 0 to 58 in 32 steps 29 LL Lower limit for LA Set lower limit for LA (LL = 0 V to 5.0 V) 30 UL Upper limit for LA Set upper limit for LA (UL = 0 V to 5.0 V) 12 OS Inputs output logic select signal L: Active LOW H: Active HIGH 3 Idc Inputs overcurrent protection signal Inputs DC link current. Reference voltage: 0.5 V With built-in filter ( 1 s), built-in digital filter ( 1 s) 14 Xin Inputs clock signal 15 Xout Outputs clock signal 23 Vrefout 17 FG 16 REV 9 U Outputs turn-on signal 8 V Outputs turn-on signal 7 W Outputs turn-on signal 6 X Outputs turn-on signal 5 Y Outputs turn-on signal 4 Z Outputs turn-on signal 1 VCC With built-in feedback resistor Outputs reference voltage signal 5 V (typ.), 30 mA (max) FG signal output pin Outputs 3 PPR of positional signal Reverse rotation detection signal Detects reverse rotation. Select active HIGH or active LOW using the output logic select pin. Power supply voltage pin VCC = 6 to 10 V 10 Td Inputs setting dead time L: 3.8 s, H or OPEN: 1.9 s 22 SS 120/180 select signal L: 120 turn-on mode, H or OPEN: 180 turn-on mode 13 GND Ground pin 3 2012-10-22 TB6556FG Input/Output Equivalent Circuits Symbol Input/Output Signal Vrefout Vrefout Digital Positional signal input pin U Positional signal input pin V Positional signal input pin W HU HV HW Input/Output Internal Circuit 200 k Pin Description With Schmitt trigger Hysteresis 300 mV (typ.) Digital filter: 500 ns (typ.) 2.0 k L: 0.8 V (max) H: Vrefout - 1 V (min) 100 k Vrefout Vrefout Digital Forward/reverse switching input pin CW/CCW L: Forward (CW) H: Reverse (CCW) L: 0.8 V (max) 2.0 k H: Vrefout - 1 V (min) Digital Reset input L: Stops operation (reset) H: Operates 100 k Vrefout Vrefout RES L: 0.8 V (max) H: Vrefout - 1 V (min) Vrefout Vrefout SS L: 120 turn-on mode H: 180 turn-on mode (OPEN) With Schmitt trigger Hysteresis: 300 mV (typ.) 200 k Digital 120/180 select signal 2.0 k L: 0.8 V (max) 2.0 k H: Vrefout - 1 V (min) VCC Voltage command signal Analog Ve Input voltage range 0 to 5.4 V Input voltage of 5.4 V or higher is clipped to 5.4 V. 4 100 150 k 1.0 V < Ve 2.1 V Refresh operation (X, Y, Z pins: ON duty of 8%) 2012-10-22 TB6556FG Symbol Input/Output Signal When LA is fixed externally, connect LL to GND and UL to Vrefout, and then input the setting voltage to the LA pin. Lead angle setting signal input pin 0 V: 0 5 V: 58 (5-bit AD) Input/Output Internal Circuit VCC Input voltage range: 0 V to 5.0 V 100 (Vrefout) LA 200 k Pin Description Input voltage of Vrefout or higher is clipped to Vrefout. Automatic LA circuit When LA is fixed automatically, open the LA pin. In this state, the LA pin is used only for confirmation of LA width. VCC Gain setting signal input (LA setting) Gin Gout Non-inverted amplifier 25 dB (max) Gout output voltage LOW: GND HIGH: VCC - 1.7 V Gin VCC 100 Gout To peak hold circuit Idc VCC Peak hold (LA setting) PH Connect the peak-hold capacitor and discharge resistor to GND, parallel to each other. 100 k/0.1F recommended 100 100 VCC Low-pass filter (LA setting) LPF Connect the low-pass filter capacitor Built-in 100 k (typ.) resistor 0.1F recommended 100 k 100 VCC Lower limit for LA LL Clip lower limit for LA LL = 0 V to 5.0 V When LL UL, LA is fixed at LL value. 5 100 2012-10-22 TB6556FG Pin Description Symbol Input/Output Signal Input/Output Internal Circuit VCC Upper limit for LA UL Clip upper limit for LA UL = 0 V to 5.0 V When LL UL, LA is fixed at LL value. 100 Digital Setting dead time input pin L: 3.8 s H or OPEN: 1.9 s 100 k Vrefout Vrefout Td L: 0.8 V (max) H: Vrefout - 1 V (min) 2 k 100 k Vrefout Vrefout Digital Output logic select signal input pin OS L: Active LOW H: Active HIGH L: 0.8 V (max) 2 k H: Vrefout - 1 V (min) VCC 100 Gout Analog Idc Digital filter: 1 s (typ.) 5 pF Gate protected at 0.5 V or higher (released at carrier cycle) Clock signal input pin Gin Comparator 200 k 0.5 V Overcurrent protection signal input pin Vrefout Vrefout Xin Operating range 2 MHz to 8 MHz (ceramic oscillation) Clock signal output pin Xout Xout Xin 360 k 6 2012-10-22 TB6556FG Pin Description Symbol Input/Output Signal Input/Output Internal Circuit VCC Reference voltage signal output pin Vrefout 5 0.5 V (max 30 mA) Vrefout Reverse-rotation-detection signal output pin VCC VCC Vrefout Digital REV Push-pull output: 1 mA (max) 100 Vrefout Vrefout Digital FG signal output pin FG Push-pull output: 1 mA (max) 100 Vrefout Turn-on signal output pin U Turn-on signal output pin V Turn-on signal output pin W Turn-on signal output pin X Turn-on signal output pin Y Turn-on signal output pin Z U V W X Y Z Analog Push-pull output: 2 mA (max) 100 L: 0.78 V (max) H: Vrefout - 0.78 V (min) 7 2012-10-22 TB6556FG Absolute Maximum Ratings (Ta = 25C) Characteristics Symbol Rating Unit VCC 12 V Supply voltage Input voltage Vin (1) -0.3 to VCC (Note 1) Vin (2) -0.3 to Vrefout + 0.3 (Note 2) Turn-on signal output current IOUT 2 Power dissipation PD 1.50 Operating temperature Storage temperature V mA (Note 3) W Topr -30 to 115 (Note 4) C Tstg -50 to 150 C Note 1: Vin (1) pin: Ve, LA, Gin, Gout, PH, LPF, LL, UL Note 2: Vin (2) pin: HU, HV, HW, CW/CCW, RES, OS, Idc, Td, SS Note 3: When mounted on PCB (universal 50 mm 50 mm 1.6 mm, Cu 30%) Note 4: Operating temperature range is determined by the PD - Ta characteristic. Operating Conditions (Ta = 25C) Characteristics Symbol Min Typ. Max Unit Supply voltage VCC 6 7 10 V Ceramic oscillation frequency Xin 2 4 8 MHz PD - Ta 2.0 (1) When mounted on PCB Power dissipation PD (W) Universal 50 mm 50 mm 1.6 mm 1.5 (2) IC only Rth (j-a) = 110C/W (1) 1.0 (2) 0.5 0 0 50 100 Ambient temperature Ta 8 150 200 (C) 2012-10-22 TB6556FG Electrical Characteristics (Ta = 25C, VCC = 7 V) Characteristics Symbol Test Circuit ICC Min Typ. Max Unit Vrefout = open 5 8 mA Vin = 5 V LA 25 50 Vin = 5 V Ve 35 70 Iin (2)-1 Vin = 0 V HU, HV, HW, SS -50 -25 Iin (2)-2 Vin = 0 V CW/CCW, OS, Td, RES -100 -50 Vrefout -1 Vrefout Supply current Iin (1)-1 Input current Iin (1)-2 HIGH Vin Test Condition HU, HV, HW, CW/CCW, RES, OS, Td, SS LOW Input voltage H Ve M L Input hysteresis voltage Input delay time VH VDT VDC Output voltage Output leakage current 0.7 1.0 1.3 0.3 HU, HV, HW Xin = 4.19 MHz 0.5 Idc Xin = 4.19 MHz 1.0 Vrefout Vrefout - 0.78 - 0.3 V s IOUT = -2 mA U, V, W, X, Y, Z VREV (H) IOUT = 1 mA REV IOUT = -1 mA REV VFG (H) IOUT = 1 mA FG VFG (L) IOUT = -1 mA FG 0.2 1.0 Vrefout IOUT = 30 mA Vrefout 4.5 5.0 5.5 VOUT = 0 V U, V, W, X, Y, Z 0 10 VOUT = 3.5 V U, V, W, X, Y, Z 0 10 Td = HIGH or OPEN, Xin = 4.19 MHz, IOUT = 2 mA, OS = HIGH/LOW 1.5 1.9 Td = LOW, Xin = 4.19 MHz, IOUT = 2 mA, OS = HIGH/LOW 3.0 3.8 Idc 0.46 0.5 0.54 V GOUT output current 5 mA GIN, GOUT 11 k/1 k -40 mV LL = 0.7 V -20 20 UL = 2.0 V -20 20 VREV (L) IL (H) IL (L) TOFF (L) AMPOUT AMPOFS VCC monitor Turned-off Refresh V VOUT (L)-1 Vdc Lead angle correction 5.7 2.4 U, V, W, X, Y, Z Overcurrent detection LA peak hold output current 5.4 2.1 IOUT = 2 mA TOFF (H) LA limit setting difference 5.1 1.8 VOUT (H)-1 Output off-time by upper/lower transistor (Note 6) LA gain setting amp Modulation factor maximum (Note 5) V 0.8 Refresh Start motor operation HU, HV, HW, SS A L U 0.3 Vrefout Vrefout - 1.0 - 0.2 0.2 Vrefout Vrefout - 1.0 - 0.2 0.78 1.0 V A s mV PHOUT PH output current 5 TLA (0) LA = 0 V or OPEN, Hall IN = 100 Hz 0 TLA (2.5) LA = 2.5 V, Hall IN = 100 Hz 27.5 32 34.5 TLA (5) LA = 5 V, Hall IN = 100 Hz 53.5 59 62.5 VCC (H) Output start operation point 4.2 4.5 4.8 VCC (L) No output operation point 3.7 4.0 4.3 VH Input hysteresis width 0.5 mA V Note 5: Toshiba does not implement testing before shipping. 9 2012-10-22 TB6556FG Note 6: TOFF OS = HIGH 0.78 V Turn-on signal (U, V, W) 0.78 V TOFF TOFF Turn-on signal (X, Y, Z) 0.78 V 0.78 V OS = LOW Turn-on signal (U, V, W) Vrefout - 0.78 V TOFF Vrefout - 0.78 V Vrefout - 0.78 V TOFF Vrefout - 0.78 V Turn-on signal (X, Y, Z) 10 2012-10-22 TB6556FG Functional Description 1. Basic operation The motor is driven by the square-wave turn-on signal based on a positional signal. When the positional signal reaches frequency f = 5 Hz or higher, the rotor position is estimated according to the positional signal and a modulation wave is generated. The modulation wave and the triangular wave are compared; then the sine-wave PWM signal is generated and the motor is driven. From start to 5 Hz: When driven by square wave (120 turn-on) f = fOSC / (212 32 6) 5 Hz or higher: When driven by sine-wave PWM (180 turn-on); when fOSC = 4 MHz, approx. 5 Hz 2. Select drive function This function can select drive mode. SS pin HIGH or OPEN = Sine-wave PWM drive (180 turn-on mode) LOW = Square-wave drive (120 turn-on mode) Note: If the position sensing signal is f = 5 Hz or lower, the driver is 120 turn-on mode even when SS = HIGH. 3. Ve voltage command signal function and function to stabilize bootstrap voltage (1) (2) (3) When the voltage command signal is input at Ve 1.0 V: Turns off output (gate protection) When the voltage command signal is input at 1.0 V Ve 2.1 V: Turns on the lower transistor at the regular (carrier) cycle. (ON duty is approx. 8%.) When the voltage command signal is input at Ve 2.1 V: During sin-wave drive, outputs drive signal as it is. During square-drive, forcibly turns on the lower transistor at regular (carrier) cycle. (ON duty is approx. 8%) Note: At startup, turn the lower transistor on for a fixed time with 1.0 V Ve 2.1 V to charge the upper transistor gate power supply. PWM Duty 100% (1) (2) 1.0 V (3) 2.1 V 5.4 V Ve 4. Dead time function: upper/lower transistor output off-time When the motor is driven by sine-wave PWM, dead time is digitally generated in the IC to prevent a short circuit caused by the simultaneous turning on of upper and lower external power devices. When a square wave is generated in full-duty cycle mode, the dead time function is turned on to prevent a short circuit. Td Pin Internal Counter TOFF HIGH or OPEN 8/fOSC 1.9 s LOW 16/fOSC 3.8 s TOFF values above are obtained when fOSC = 4.19 MHz. fOSC = reference clock (ceramic oscillation) 11 2012-10-22 TB6556FG 5. Correcting the lead angle The lead angle can be corrected in the turn-on signal range from 0 to 58 in relation to the induced voltage. Analog input from LA pin (0 V to 5 V divided by 32): 0 V = 0 5 V = 58 (when more than 5 V is input, 58) 6. Setting the carrier frequency This function sets the triangular wave cycle (carrier cycle) necessary for generating the PWM signal. (The triangular wave is used for forcibly turning on the lower transistor when the motor is driven by square wave.) Carrier cycle = fOSC/252 (Hz) fOSC = reference clock (ceramic oscillation) 7. Switching the output of the turn-on signal This function switches the output of the turn-on signal between HIGH and LOW. Pin OS: HIGH = active HIGH LOW = active LOW 8. Outputting the reverse rotation detection signal This function detects the motor rotation direction every electrical angle of 360. (The output is HIGH immediately after reset.) When the signal of REV terminal is low, the operation transfers to 180 commutation mode. (Hall IN = 5 Hz or more) CW/CCW Pin Actual Motor Rotating Direction REV Pin CW (forward) LOW CCW (reverse) HIGH CW (forward) HIGH CCW (reverse) LOW LOW (CW) HIGH (CCW) 9. Protecting input pin 1. 2. Overcurrent protection (Pin Idc) When the DC-link-voltage which is converted from DC-link-current exceeds the internal reference voltage, performs gate block protection. Overcurrent protection is released for each carrier frequency. Reference voltage = 0.5 V (typ.) Gate protection (Pin RES) Output is turned off when the input signal is LOW, restarted when the input signal is HIGH. The abnormality is detected externally and the signal input to pin RES. RES Pin LOW OS Pin Output Turn-on Signal (U, V, W, X, Y, Z) LOW HIGH HIGH LOW (When RES = LOW, bootstrap capacitor charging stops.) 12 2012-10-22 TB6556FG 3. Internal protection Positional signal abnormality protection Output is turned off when the positional signal is HHH or LLL; otherwise, it is restarted. Low power supply voltage protection (VCC monitor) For power supply on/off outside the operating voltage range, the turn-on signal output is kept at high impedance outside the operating voltage range to prevent damage caused by power device short circuits. However, if the voltage level is supplied from the Ve pin, this function is restricted, e.g., when Ve 4.9 V is applied, low power supply voltage protection does not operate. VCC Power supply voltage 4.5 V (typ.) 4.0 V (typ.) GND VM Turn-on signal Output at high impedance Output 13 Output at high impedance 2012-10-22 TB6556FG Operation Flow Positional signal (Hall IC) Position detector Phase U U Counter X Phase V V Phase matching Y Phase Sine-wave pattern W (modulation signal) Comparator W Z Voltage instruction Driven by square wave (Note) Output ON duty (U, V, W) 92% 2.1 V (typ.) 5.0 V (typ.) Voltage command signal Ve Note: Output ON time is decreased by the dead time (carrier cycle 92% - Td 2) Driven by sine wave 100% Modulation ratio (modulation signal) Oscillator Triangular wave (carrier frequency) System clock generator 0 2.1 V (typ.) 5.4 V (typ.) Voltage command signal Ve 14 2012-10-22 TB6556FG The modulation waveform is generated using Hall signals. The modulation waveform is then compared with the triangular wave and a sine-wave PWM signal is generated. The time (electrical degrees: 60) from the rising (or falling) edges of the three Hall signals to the next falling (or rising) edges is counted. The counted time is used as the data for the next 60 phase of the modulation waveform. There are 32 items of data for the 60 phase of the modulation waveform. The time width of one data item is 1/32 of the time width of the 60 phase of the previous modulation waveform. The modulation waveform moves forward by the width. HU (6) (1) (3) * HU, HV, HW: Hall signals HV (5) (2) HW (6)' (1)' (2)' (3)' SU SV Sw In the above diagram, the modulation waveform (1)' data moves forward by the 1/32 time width of the time (1) from HU: to HW: . Similarly, data (2)' moves forward by the 1/32 time width of the time (2) from HW: to HV: . If the next edge does not occur after the 32 data items end, the next 32 data items move forward by the same time width until the next edge occurs. *t 32 31 30 6 5 4 3 2 1 SV (1)' 32 data items * t = t(1) 1/32 The modulation wave is brought into phase with every zero-cross point of the Hall signal. The modulation wave is reset in synchronization with the rising and falling edges of the Hall signal at every 60 electrical angle. Thus, when the Hall device is not placed at the correct position or during acceleration and deceleration, the modulation waveform is not continuous at every reset. 15 2012-10-22 TB6556FG Timing Charts Hall signal (input) HU HV HW FG signal (output) FG Turn-on signal when driven by square wave (output) U V W X Y Z Su Modulation waveform when driven by sine wave (inside of IC) Sv Sw Forward Hall signal (input) HU HV HW FG signal (output) FG Turn-on signal when driven by square wave (output) U V W X Y Z Su Modulation waveform when driven by sine wave (inside the IC) S v Sw Reverse Timing charts may be simplified for explanatory purposes. 16 2012-10-22 TB6556FG Operating Waveform When Driven by Square Wave (CW/CCW = LOW, OS = HIGH, SS = High) Hall signal HU HV HW Output waveform U X V Y W Z Enlarged waveform W TONU Td TONL Td Z To stabilize the bootstrap voltage, the lower outputs (X, Y, and Z) are always turned on at the carrier cycle even during off time. At that time, the upper outputs (U, V, and W) are assigned dead time and turned off at the timing when the lower outputs are turned on. (Td varies with input Ve.) Carrier cycle = fOSC/252 (Hz) Dead time: Td = 16/fOSC (s) (In more than Ve = 5.0 V when Td = Low.) TONL = carrier cycle 8% (s) (Uniformity) When the motor is driven by a square wave, acceleration or deceleration is determined by voltage Ve. The motor accelerates or decelerates according to the ON duty of TONU. (See the diagram of output ON duty on page 14.) Note: The motor is driven by a square wave when the Hall signals are 5 Hz or lower (fOSC = 4 MHz) and the motor is rotating in the reverse direction to that of the TB6556FG controlling it (REV = HIGH). 17 2012-10-22 TB6556FG Operating Waveform When Driven by Sine-Wave PWM (CW/CCW = LOW, OS = HIGH, SS = High) Generation inside of IC Modulation signal Triangular wave (carrier frequency) Phase U Phase V Phase W Output waveform U X V Y W Z Inter-line voltage VUV (U-V) VVW (V-W) VWU (W-U) When driven by a sine wave, the motor is accelerated or decelerated according to the ON duty of TONU as the amplitude of the modulation symbol changes according to voltage Ve. (See the diagram of the modulation ratio on page 14.) Triangular wave frequency = carrier frequency = fOSC/252 (Hz) Note: At startup, the motor is driven by a sine wave when the Hall signals are 5 Hz or higher (fOSC = 4 MHz) and the motor is rotating in the same direction as the TB6556FG controlling it (REV = LOW). 18 2012-10-22 TB6556FG Example of Application Circuit Vrefout Vrefout G = 1 + (R2/R1) R1 (10 k) 100 k R2 (100 k) 0.1 F LA Gin 24 Gout 25 PH 26 Peak hold LPF 27 + UL 30 LL 29 28 Upper limit Filter Lower limit Xin 14 System clock generator Xout 15 21 HU 20 HV 19 HW 6 to 10 V Ve VCC Phase U Position detector Regulator 9 Counter Internal Phase reference matching voltage Output waveform generator Vrefout Selecting Phase V data Comparator Phase W Comparator RES SS FG REV FG Rotating direction Comparator 18 22 PWM HU HV HW 11 Idc 3 CW/CCW Charger Power-on reset 6 Setting dead time 8 5 7 13 23 ST/SP CW/CCW Td Comparator 120/180 GND MCU 10 5-bit AD 2 1 Triangular wave generator 6-bit Switching 120/180 & gate block protection on/off 4 12 U X V M Power device Y W Z OS 120turn-on matrix Protection ERR & GB reset 17 16 (Note 1) (Note 1) Hall IC signal Note 1: Connect to ground as necessary to prevent IC malfunction due to noise. Note 2: Connect GND to signal ground on the application circuit. Note 3: Utmost care is necessary in the design of the output, VCC, and GND lines since the IC may be destroyed by short-circuiting between outputs, air contamination faults, or faults due to improper grounding, or by short-circuiting between contiguous pins. 19 2012-10-22 TB6556FG Package Dimensions Weight: 0.63 g (typ.) 20 2012-10-22 TB6556FG Notes on Contents 1. Block Diagrams Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. Test Circuits Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. IC Usage Considerations Notes on handling of ICs [1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. [2] Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. 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