9338FMQB - National Semiconductor

TL/F/9794

9338/DM9338 8-Bit Multiple Port Register

June 1989

9338/DM9338 8-Bit Multiple Port Register

General Description

The DM9338 is an 8-bit multiple port register designed for

high speed random access memory applications where the

ability to simultaneously read and write is desirable. A com-

mon use would be as a register bank in a three address

computer. Data can be written into any one of the eight bits

and read from any two of the eight bits simultaneously.

Connection Diagrams

Dual-In-Line Package

TL/F/9794–1

Order Number 9338DMQB, 9338FMQB or DM9338N

See NS Package Number J16A, N16E or W16A

Pin Names Description

A0– A2 Write Address Inputs

DAData Input

B0– B2 B Read Address Inputs

C0– C2 C Read Address Inputs

CP Clock Pulse Input (Active Rising Edge)

SLE Slave Enable Input (Active LOW)

ZBB Output

ZCC Output

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C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 5.5V

Operating Free Air Temperature Range

Military b55§Ctoa

125§C

Commercial 0§Ctoa

70§C

Storage Temperature Range b65§Ctoa

150§C

Note:

The ‘‘Absolute Maximum Ratings’’ are those values

beyond which the safety of the device cannot be guaran-

teed. The device should not be operated at these limits. The

parametric values defined in the ‘‘Electrical Characteristics’’

table are not guaranteed at the absolute maximum ratings.

The ‘‘Recommended Operating Conditions’’ table will define

the conditions for actual device operation.

Recommended Operating Conditions

Symbol Parameter Military Commercial Units

Min Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.8 0.8 V

IOH High Level Output Current b0.8 b0.8 mA

IOL Low Level Output Current 16 16 mA

TAFree Air Operating Temperature b55 125 0 70 §C

ts(H) Setup Time HIGH or LOW 20 20 ns

ts(L) DAto CP 12 12

th(H) Hold Time HIGH or LOW 0 0 ns

th(L) DAto CP b8.0 b8.0

ts(H) Setup Time HIGH or LOW 10 10 ns

ts(L) Anto CP 10 10

th(H) Hold Time HIGH or LOW 0 0 ns

th(L) Anto CP 0 0

tw(H) CP Pulse Width HIGH or LOW 23 23 ns

tw(L) 13 13

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 1)

VIInput Clamp Voltage VCC eMin, IIeb

12 mA b1.5 V

VOH High Level Output Voltage VCC eMin, IOH eMax 2.4 3.4 V

VIL eMax

VOL Low Level Output Voltage VCC eMin, IOL eMax 0.2 0.4 V

VIH eMin

IIInput Current @Max VCC eMax, VIe5.5V 1mA

Input Voltage

IIH High Level Input Current VCC eMax, VIe2.4V 27 mA

IIL Low Level Input Current VCC eMax, VIe0.4V b1.1 mA

IOS Short Circuit VCC eMax MIL b10 b70 mA

Output Current (Note 2) COM b10 b70

ICC Supply Current VCC eMax 135 mA

Note 1: All typicals are at VCC e5V, TAe25§C.

Note 2: Not more than one output should be shorted at a time.

Switching Characteristics

VCC ea

5.0V, TAea

25§C (See Section 1 for waveforms and load configurations)

CLe15 pF

Symbol Parameter 9338 (MIL) DM9338 (COM) Units

Min Max Min Max

tPLH Propagation Delay 40 13 40 ns

tPHL Bnor Cnto Zn35 18 35

tPLH Propagation Delay 45 25 45 ns

tPHL DAto Zn50 25 50

tPLH Propagation Delay 35 18 35 ns

tPHL CP to Zn30 13 30

Functional Description

The 9338 8-bit multiple port register can be considered a 1-

bit slice of eight high speed working registers. Data can be

written into any one and read from any two of the eight

locations simultaneously. Master/slave operation eliminates

all race problems associated with simultaneous read/write

activity from the same location. When the clock input (CP) is

LOW data applied to the data input line (DA) enters the

selected master. This selection is accomplished by coding

the three write input select lines (A0– A2) appropriately.

Data is stored synchronously with the rising edge of the

clock pulse.

The information for each of the two slaved (output) latches

is selected by two sets of read address inputs (B0– B2 and

C0– C2). The information enters the slave while the clock is

HIGH and is stored while the clock is LOW. If Slave Enable

is LOW (SLE), the slave latches are continuously enabled.

The signals are available on the output pins (ZBand ZC).

The input bit selection and the two output bit selections can

be accomplished independently or simultaneously. The data

flows into the device, is demultiplexed according to the state

of the write address lines and is clocked into the selected

latch. The eight latches function as masters and store the

input data. The two output latches are slaves and hold the

data during the read operation. The state of each slave is

determined by the state of the master selected by its associ-

ated set of read address inputs.

The method of parallel expansion is shown in

Figure a

. One

9338 is needed for each bit of the required word length. The

read and write input lines should be connected in common

on all of the devices. This register configuration provides

two words of n-bits each at one time, where n devices are

connected in parallel.

Logic Symbol

TL/F/9794–2

VCC ePin 16

GND ePin 8

TL/F/9794–4

FIGURE a. Parallel Expansion

Logic Diagram

TL/F/9794–3

Physical Dimensions inches (millimeters)

16-Lead Ceramic Dual-In-Line Package (J)

Order Number 9338DMQB

NS Package Number J16A

16-Lead Molded Dual-In-Line Package (N)

Order Number DM9338N

NS Package Number N16E

9338/DM9338 8-Bit Multiple Port Register

Physical Dimensions inches (millimeters) (Continued)

16-Lead Ceramic Flat Package (W)

Order Number 9338FMQB

NS Package Number W16A

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into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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