© Semiconductor Components Industries, LLC, 2016
December, 2016 − Rev. 23 1Publication Order Number:
MC74HC595A/D
MC74HC595A
8-Bit Serial-Input/Serial or
Parallel-Output Shift
Register with Latched
3-State Outputs
High−Performance Silicon−Gate CMOS
The MC74HC595A consists of an 8−bit shift register and an 8−bit
D−type latch with three−state parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register also
provides parallel data to the 8−bit latch. The shift register and latch
have independent clock inputs. This device also has an asynchronous
reset for the shift register.
The HC595A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
Features
•Output Drive Capability: 15 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2.0 to 6.0 V
•Low Input Current: 1.0 mA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance with the Requirements Defined by JEDEC
Standard No. 7 A
•Chip Complexity: 328 FETs or 82 Equivalent Gates
•Improvements over HC595
♦Improved Propagation Delays
♦50% Lower Quiescent Power
♦Improved Input Noise and Latchup Immunity
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These Devices are Pb−Free, Halogen Free and are RoHS Compliant
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MARKING DIAGRAMS
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G, G= Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
SOIC−16 TSSOP−16
1
16
HC595AG
AWLYWW
HC
595A
ALYWG
G
1
16
(Note: Microdot may be in either location)
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
QFN16
MN SUFFIX
CASE 485AW
1
595A
ALYWG
G
QFN16*
*V595A marking used for
NLV74HC595AMN1TWG
MC74HC595A
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2
Figure 1. Pin Assignments
116
215
314
413
512
611
710
89
GND
VCC
SQH
GND
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
LATCH CLOCK
OUTPUT ENABLE
A
QA
VCC
SQH
RESET
SHIFT CLOCK
QE
QD
QC
QB
GND
QH
QG
QF
QB
QE
QD
QC
QH
QG
QFLATCH CLOCK
OUTPUT ENABLE
A
QA
RESET
SHIFT CLOCK
SOIC, TSSOP QFN
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
11
10
12
13
SHIFT
CLOCK
RESET
LATCH
CLOCK
OUTPUT
ENABLE
SHIFT
REGISTER LATCH
15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
SQH
A
VCC = PIN 16
GND = PIN 8
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT
MC74HC595A
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
Vin DC Input Voltage (Referenced to GND) –0.5 to VCC+0.5 V
Vout DC Output Voltage (Referenced to GND) –0.5 to VCC+0.5 V
Iin DC Input Current, per Pin ±20 mA
Iout DC Output Current, per Pin ±35 mA
ICC DC Supply Current, VCC and GND Pins ±75 mA
PDPower Dissipation in Still Air, SOIC Package†
TSSOP Package† 500
450 mW
Tstg Storage Temperature –65 to +150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package) 260
_C
VESD ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 3000
> 400
N/A
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
and reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output V oltage
(Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types –55 +125 _C
tr, tfInput Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC595A
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4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbo
l
Parameter Test Conditions VCC
V
Guaranteed Limit
Unit
–55 to 25_C≤ 85_C≤ 125_C
VIH Minimum High−Level Input
Voltage Vout = 0.1 V or V CC – 0.1 V
|Iout| ≤ 20 mA2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL Maximum Low−Level Input
Voltage Vout = 0.1 V or V CC – 0.1 V
|Iout| ≤ 20 mA2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH Minimum High−Level Output
Voltage, QA − QHVin = VIH or VIL
|Iout| ≤ 20 mA2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout| ≤ 2.4 mA
|Iout| ≤ 6.0 mA
|Iout| ≤ 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
VOL Maximum Low−Level Output
Voltage, QA − QHVin = VIH or VIL
|Iout| ≤ 20 mA2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout| ≤ 2.4 mA
|Iout| ≤ 6.0 mA
|Iout| ≤ 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH Minimum High−Level Output
Voltage, SQHVin = VIH or VIL
IIoutI ≤ 20 mA2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout| ≤ 2.4 mA
IIoutI ≤ 4.0 mA
IioutI ≤ 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
VOL Maximum Low−Level Output
Voltage, SQHVin = VIH or VIL
IIoutI ≤ 20 mA2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout| ≤ 2.4 mA
IIoutI ≤ 4.0 mA
IioutI ≤ 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Iin Maximum Input Leakage
Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
IOZ Maximum Three−State
Leakage
Current, QA − QH
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0 ±0.5 ±5.0 ±10 mA
ICC Maximum Quiescent Supply
Current (per Package) Vin = VCC or GND
lout = 0 mA6.0 4.0 40 160 mA
MC74HC595A
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5
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbo
l
Parameter VCC
V
Guaranteed Limit
Unit
–55 to 25_C≤ 85_C≤ 125_C
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7) 2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
24
MHz
tPLH,
tPHL Maximum Propagation Delay, Shift Clock to SQH
(Figures 1 and 7) 2.0
3.0
4.5
6.0
140
100
28
24
175
125
35
30
210
150
42
36
ns
tPHL Maximum Propagation Delay, Reset to SQH
(Figures 2 and 7) 2.0
3.0
4.5
6.0
145
100
29
25
180
125
36
31
220
150
44
38
ns
tPLH,
tPHL Maximum Propagation Delay, Latch Clock to QA − QH
(Figures 3 and 7) 2.0
3.0
4.5
6.0
140
100
28
24
175
125
35
30
210
150
42
36
ns
tPLZ,
tPHZ Maximum Propagation Delay, Output Enable to QA − QH
(Figures 4 and 8) 2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL,
tPZH Maximum Propagation Delay, Output Enable to QA − QH
(Figures 4 and 8) 2.0
3.0
4.5
6.0
135
90
27
23
170
110
34
29
205
130
41
35
ns
tTLH,
tTHL Maximum Output Transition Time, QA − QH
(Figures 3 and 7) 2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
31
18
15
ns
tTLH,
tTHL Maximum Output Transition Time, SQH
(Figures 1 and 7) 2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Cin Maximum Input Capacitance − 10 10 10 pF
Cout Maximum Three−State Output Capacitance (Output in
High−Impedance State), QA − QH− 15 15 15 pF
CPD Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, VCC = 5.0 V
pF
300
MC74HC595A
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6
TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)
Symbo
l
Parameter VCC
V
Guaranteed Limit
Unit
25_C to – 55_C≤ 85_C≤ 125_C
tsu Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5) 2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
tsu Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6) 2.0
3.0
4.5
6.0
75
60
15
13
95
70
19
16
110
80
22
19
ns
thMinimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5) 2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
trec Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2) 2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
twMinimum Pulse Width, Reset
(Figure 2) 2.0
3.0
4.5
6.0
60
45
12
10
75
60
15
13
90
70
18
15
ns
twMinimum Pulse Width, Shift Clock
(Figure 1) 2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
twMinimum Pulse Width, Latch Clock
(Figure 6) 2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
tr, tfMaximum Input Rise and Fall Times
(Figure 1) 2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
MC74HC595A
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7
FUNCTION TABLE
Operation
Inputs Resulting Function
Reset
Serial
Input
AShift
Clock Latch
Clock Output
Enable
Shift
Register
Contents
Latch
Register
Contents
Serial
Output
SQH
Parallel
Outputs
QA − QH
Reset shift register L X X L, H, ↓L L U L U
Shift data into shift
register H D ↑L, H, ↓L D →SRA;
SRN →SRN+1 U SRG →SRHU
Shift register remains
unchanged H X L, H, ↓L, H, ↓L U U U U
Transfer shift register
contents to latch
register
H X L, H, ↓ ↑ L U SRN →LRNU SRN
Latch register remains
unchanged X X X L, H, ↓L * U * U
Enable parallel outputs X X X X L * ** * Enabled
Force outputs into high
impedance state X X X X H * ** * Z
SR = shift register contents D = data (L, H) logic level ↑ = Low−to−High * = depends on Reset and Shift Clock inputs
LR = latch register contents U = remains unchanged ↓ = High−to−Low ** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTS
A (Pin 14)
Serial Data Input. The data on this pin is shifted into the
8−bit serial shift register.
CONTROL INPUTS
Shift Clock (Pin 11)
Shift Register Clock Input. A low− to−high transition on
this input causes the data at the Serial Input pin to be shifted
into the 8−bit shift register.
Reset (Pin 10)
Active−low, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8−bit latch is not af fected.
Latch Clock (Pin 12)
Storage Latch Clock Input. A low−to−high transition on
this input latches the shift register data.
Output Enable (Pin 13)
Active−low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
on this input forces the outputs (QA−QH) into the
high−impedance state. The serial output is not affected by
this control unit.
OUTPUTS
QA − Q H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Noninverted, 3−state, latch outputs.
SQH (Pin 9)
Noninverted, Serial Data Output. This is the output of the
eighth stage of the 8−bit shift register. This output does not
have three−state capability.
MC74HC595A
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8
SWITCHING WAVEFORMS
SERIAL
INPUT A 50%
50%
SWITCH
CLOCK
VCC
GND
VALID
tsu th
Figure 5.
SHIFT
CLOCK
OUTPUT
SQH
trtf
VCC
GND
90%
50%
10%
90%
50%
10%
tPLH tPHL
tTLH tTHL
tw
1/fmax
RESET
OUTPUT
SQH
SHIFT
CLOCK
tw
50%
50%
50%
VCC
GND
VCC
GND
tPHL
trec
tsu
50%
50%
VCC
GND
LATCH
CLOCK
QA-QH
OUTPUTS
50%
tPLH tPHL
tTLH tTHL
90%
50%
10%
VCC
GND
VCC
GND
SHIFT
CLOCK
LATCH
CLOCK
Figure 3.
VCC
GND tw
Figure 1. Figure 2.
Figure 4.
Figure 6.
OUTPUT Q
OUTPUT Q
50%
50%
90%
10%
tPZL tPLZ
tPZH tPHZ
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
OUTPUT
ENABLE
50%
TEST CIRCUITS
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kW
Figure 7. Figure 8.
MC74HC595A
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9
D
R
Q
SRA
DQ
LRA
DQ
SRB
DQ
LRB
R
DQ
SRC
DQ
LRC
R
DQ
SRD
DQ
LRD
R
DQ
SRE
DQ
LRE
R
DQ
SRF
DQ
LRF
R
DQ
SRG
DQ
LRG
R
DQ
SRH
DQ
LRH
R
EXPANDED LOGIC DIAGRAM
OUTPUT
ENABLE
LATCH
CLOCK
SERIAL
DATA
INPUT A
SHIFT
CLOCK
RESET
13
12
14
11
10
15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
SERIAL
DATA
OUTPUT SQH
PARALLEL
DATA
OUTPUTS
MC74HC595A
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10
TIMING DIAGRAM
SHIFT
CLOCK
SERIAL DATA
INPUT A
RESET
LATCH
CLOCK
OUTPUT
ENABLE
QA
QB
QC
QD
QE
QF
QG
QH
SERIAL DATA
OUTPUT SQH
NOTE: implies that the output is in a high−impedance
state.
ORDERING INFORMATION
Device Package Shipping†
MC74HC595ADG
SOIC−16
(Pb−Free)
48 Units / Rail
NLV74HC595ADG* 48 Units / Rail
MC74HC595ADR2G 2500 / Tape & Reel
NLV74HC595ADR2G* 2500 / Tape & Reel
MC74HC595ADTG
TSSOP−16
(Pb−Free)
96 Units / Tube
NLV74HC595ADTG* 96 Units / Tube
MC74HC595ADTR2G 2500 / Tape & Reel
NLV74HC595ADTR2G* 2500 / Tape & Reel
MC74HC595AMNTWG# QFN16
(Pb−Free)
3000 / Tape & Reel
NLV74HC595AMNTWG*# 3000 / Tape & Reel
NLV74HC595AMN1TWG*# 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
#MN suffix is with pull−back lead, MN1 is without pull−back lead. Refer to ’Detail A’ of case outline on page 13.
QFN16, 2.5x3.5, 0.5P
CASE 485AW−01
ISSUE O
DATE 11 DEC 2008
ÉÉÉ
ÉÉÉ
ÉÉÉ
DIM MIN MAX
MILLIMETERS
A
A1 0.00 0.05
A3
b0.20 0.30
D2.50 BSC
D2 0.85 1.15
E3.50 BSC
E2
e0.50 BSC
K0.20 ---
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
0.20 REF
b
D2
L
PIN ONE
E2
1
8
15
10
D
E
B
A
C0.15
C0.15
2X
2X
e
2
16X
16X
0.10 C
0.05 C
A B
NOTE 3
A
16X
K
A1
(A3)
SEATING
PLANE
C0.08
C0.10
0.80 1.00
L0.35 0.45
1.85 2.15
SCALE 2:1
GENERIC MARKING
DIAGRAM*
XXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
XXXX
ALYWG
G
1
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÉÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
DETAIL B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.80
3.80
1.10
0.50
0.60
16X
0.30
16X
DIMENSIONS: MILLIMETERS
1
REFERENCE
TOP VIEW
SIDE VIEW
NOTE 4
C
0.15 C A B
0.15 C A B
DETAIL A
BOTTOM VIEW
e/2
L1 --- 0.15
(Note: Microdot may be in either location)
2.10
PITCH
PACKAGE
OUTLINE
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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DOCUMENT NUMBER:
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PAGE 1 OF 1
QFN16, 2.5X3.5, 0.5P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
STYLE 1:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
14. COLLECTOR
15. EMITTER
16. COLLECTOR
STYLE 2:
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
16. CATHODE
STYLE 3:
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
15. EMITTER, #4
16. COLLECTOR, #4
STYLE 4:
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
STYLE 5:
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
STYLE 7:
PIN 1. SOURCE N‐CH
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
9. SOURCE P‐CH
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
16
89
8X
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42566B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
SOIC−16
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
TSSOP−16
CASE 948F−01
ISSUE B
DATE 19 OCT 2006
SCALE 2:1
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
1
16
GENERIC
MARKING DIAGRAM*
XXXX
XXXX
ALYW
1
16
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G or G= Pb−Free Package
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASH70247A
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
TSSOP−16
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
www.onsemi.com
1
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