S12
Microcontrollers
freescale.com
MC9S12HY64
Reference Manual
Covers MC9S12HY/HA Family
MC9S12HY64RMV1
Rev. 1.05
09/2012
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
freescale.com
A full list of family members and options is included in the appendices.
The following revision history table summarizes changes contained in this document.
This document contains information for all constituent modules, with the exception of the CPU. For CPU
information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual.
Revision History
Date Revision
Level Description
July, 2009 1.00 initial v1.00 version
Aug, 2009 1.01 update SCI block guide, update motor pad input leakage in Appendix A
Nov, 2009 1.02 update FTMRC block guide, update MC10B8C block guide, minor update in
chapter 1, minor typo correction in Appendix F
May, 2010 1.03 update PIM block guide, update CPMU block guide, update TIM block guide
Nov, 2010 1.04 update SCI block guide, update typo in device overview
Sep, 2012 1.05 update Device overview, PIM, BDM, DBG, CPMU, INT, PWM and Appendix
for Bandgap and Motor/LCD pad maximum value update
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Chapter 1 Device Overview MC9S12HY/HA-Family . . . . . . . . . . . . . . . . .11
Chapter 2 Port Integration Module (S12HYPIMV1) . . . . . . . . . . . . . . . . . .53
Chapter 3 S12P Memory Map Control (S12PMMCV1). . . . . . . . . . . . . . .135
Chapter 4 Interrupt Module (S12SINTV1). . . . . . . . . . . . . . . . . . . . . . . . .151
Chapter 5 Background Debug Module (S12SBDMV1) . . . . . . . . . . . . . .159
Chapter 6 S12S Debug Module (S12SDBGV2) . . . . . . . . . . . . . . . . . . . .183
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU) . . .
227
Chapter 8 Analog-to-Digital Converter (ADC12B8CV1) . . . . . . . . . . . . .285
Chapter 9 Freescale’s Scalable Controller Area Network (S12MSCANV3).
311
Chapter 10 Inter-Integrated Circuit (IICV3) . . . . . . . . . . . . . . . . . . . . . . . .365
Chapter 11 Pulse-Width Modulator (S12PWM8B8CV1) . . . . . . . . . . . . . .393
Chapter 12 Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . .425
Chapter 13 Serial Peripheral Interface (S12SPIV5). . . . . . . . . . . . . . . . . .463
Chapter 14 Timer Module (TIM16B8CV2) . . . . . . . . . . . . . . . . . . . . . . . . .489
Chapter 15 32 KByte Flash Module (S12FTMRC32K1V1). . . . . . . . . . . . .517
Chapter 16 48 KByte Flash Module (S12FTMRC48K1V1). . . . . . . . . . . . .567
Chapter 17 64 KByte Flash Module (S12FTMRC64K1V1). . . . . . . . . . . . .617
Chapter 18 Liquid Crystal Display (LCD40F4BV1) . . . . . . . . . . . . . . . . . .667
Chapter 19 Motor Controller (MC10B8CV1). . . . . . . . . . . . . . . . . . . . . . . .689
Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .721
Appendix B Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .756
Appendix C Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .757
Appendix D PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .763
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Appendix E Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .767
Appendix F Detailed Register Address Map. . . . . . . . . . . . . . . . . . . . . . . .768
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Chapter 1
Device Overview MC9S12HY/HA-Family
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.6 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.7 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.8 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
1.9 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.11 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
1.12 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
1.13 ATD External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
1.14 S12CPMU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.15 Documentation Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Chapter 2
Port Integration Module (S12HYPIMV1)
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
2.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Chapter 3S12P Memory Map Control (S12PMMCV1)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
3.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
3.5 Implemented Memory in the System Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
3.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Chapter 4
Interrupt Module (S12SINTV1)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
4.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
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4.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Chapter 5
Background Debug Module (S12SBDMV1)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Chapter 6
S12S Debug Module (S12SDBGV2)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Chapter 7
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
7.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
7.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Chapter 8
Analog-to-Digital Converter (ADC12B8CV1)
Block Description
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
8.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
8.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
8.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
8.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Chapter 9
Freescale’s Scalable Controller Area Network (S12MSCANV3)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
9.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
9.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
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9.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Chapter 10
Inter-Integrated Circuit (IICV3) Block Description
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
10.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
10.7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Chapter 11
Pulse-Width Modulator (S12PWM8B8CV1)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
11.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Chapter 12
Serial Communication Interface (S12SCIV5)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
12.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Chapter 13
Serial Peripheral Interface (S12SPIV5)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Chapter 14
Timer Module (TIM16B8CV2) Block Description
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
14.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
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Chapter 15
32 KByte Flash Module (S12FTMRC32K1V1)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
15.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
15.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
15.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Chapter 16
48 KByte Flash Module (S12FTMRC48K1V1)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
16.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
16.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
16.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Chapter 17
64 KByte Flash Module (S12FTMRC64K1V1)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
17.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
17.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
17.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Chapter 18
Liquid Crystal Display (LCD40F4BV1) Block Description
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
18.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
18.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Chapter 19
Motor Controller (MC10B8CV1)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
19.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
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Freescale Semiconductor 9
19.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
19.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Appendix A
Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
A.1.5 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
A.1.8 Power Dissipation and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
A.2.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
A.2.2 Factors Influencing Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
A.3 NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
A.3.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
A.3.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
A.4 Reset, Oscillator,IRC,IVREG,IPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
A.5 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
A.5.1 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
A.6 Electrical Characteristics for the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
A.7 Electrical Characteristics for the IRC1M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
A.8 Electrical Characteristics for the Oscillator (OSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
A.9 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
A.10 Electrical Specification for Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
A.11 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
A.12 LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
A.13 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
A.14 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
A.14.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
A.14.2 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754
Appendix B
Ordering Information
Appendix C
Package Information
C.1 100-Pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
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10 Freescale Semiconductor
C.2 64-Pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
Appendix D
PCB Layout Guidelines
Appendix E
Derivative Differences
E.1 Memory Sizes and Package Options S12HY/S12HA - Family . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Appendix F
Detailed Register Address Map
MC9S12HY/HA-Family Reference Manual, Rev. 1.05
Freescale Semiconductor 11
Chapter 1
Device Overview MC9S12HY/HA-Family
1.1 Introduction
The MC9S12HY/HA family is an automotive, 16-bit microcontroller product line that is specifically
designed for entry level instrument clusters. This family also services generic automotive applications
requiring CAN, LCD, Motor driver control or LIN/J2602. Typical examples of these applications include
instrument clusters for automobiles and 2 or 3 wheelers, HVAC displays, general purpose motor control
and body controllers.
The MC9S12HY/HA family uses many of the same features found on the MC9S12P family, including
error correction code (ECC) on flash memory, a separate data-flash module for diagnostic or data storage,
a fast analog-to-digital converter (ATD) and a frequency modulated phase locked loop (IPLL) that
improves the EMC performance. The MC9S12HY/HA family features a 40x4 liquid crystal display (LCD)
controller/driver and a motor pulse width modulator (MC) consisting of up to 16 high current outputs. It
is capable of stepper motor stall detection (SSD), please contact a Freescale sales office for detailed
information.
The MC9S12HY/HA family delivers all the advantages and efficiencies of a 16-bit MCU while retaining
the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users
of Freescale’s existing 8-bit and 16-bit MCU families. Like the MC9S12HZ family, the MC9S12HY/HA
family run 16-bit wide accesses without wait states for all peripherals and memories. The MC9S12HY/HA
family is available in 100-pin LQFP and 64-pin LQFP package options. In addition to the I/O ports
available in each module, further I/O ports are available with interrupt capability allowing wake-up from
stop or wait modes.
1.2 Features
This section describes the key features of the MC9S12HY/HA family.
Device Overview MC9S12HY/HA-Family
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12 Freescale Semiconductor
1.2.1 MC9S12HY/HA Family Comparison
Table 1 provides a summary of different members of the MC9S12HY/HA family and their proposed
features. This information is intended to provide an understanding of the range of functionality offered by
this microcontroller family.
Table 1. MC9S12HY/MC9S12HA Family
Feature MC9S12
HY32
MC9S12
HY48
MC9S12
HY64
MC9S12
HA32
MC9S12
HA48
MC9S12
HA64
CPU HCS12 V1
Flash memory
(ECC) 32 KB 48 KB 64 KB 32 KB 48 KB 64 KB
Data flash (ECC) 4 KB
RAM 2 KB 4 KB 4 KB 2 KB 4 KB 4 KB
Pin Quantity 64 100 64 100 64 100 64 100 64 100 64 100
CAN 1-
SCI 1
SPI 1
IIC 1
Timer 0 8 ch x 16-bit
Timer 1 8 ch x 16-bit
PWM 8 ch x 8-bit or 4 ch x16-bit
ADC (10-bit) 6 ch 8 ch 6 ch 8 ch 6 ch 8 ch 6 ch 8 ch 6 ch 8 ch 6 ch 8 ch
Stepper Motor
Controller(1)
1. the third stepper motor controller (M2) has a restricted output current on the 64 pin version, which is half of normal motor
pad driving current
343434343434
LCD Driver
(FPxBP) 20x4 40x4 20x4 40x4 20x4 40x4 20x4 40x4 20x4 40x4 20x4 40x4
Key Wakeup Pins 18 22 18 22 18 22 18 22 18 22 18 22
Frequency Modu-
lated PLL Ye s
External osc
(4–16 MHz Pierce
with loop control)
Ye s
Internal 1 MHz RC
osc Ye s
Supply voltage 4.5 V – 5.5 V
RTI, LVI, CPMU,
RST, COP, DBG,
POR, API
Ye s
Device Overview MC9S12HY/HA-Family
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Freescale Semiconductor 13
1.2.2 Chip-Level Features
On-chip modules available within the family include the following features:
S12 CPU core
Maximum 64 MHz core freqency, 32 MHz bus frequency
Up to 64 KB on-chip flash with ECC
4 KB data flash with ECC
Up to 4 KB on-chip SRAM
Phase locked loop (IPLL) frequency multiplier with internal filter
4–16 MHz amplitude controlled Pierce oscillator
1 MHz internal RC oscillator
Two timer modules (TIM0 and TIM1) supporting input/output channels that provide a range of 16-
bit input capture, output compare, counter and pulse accumulator functions
Pulse width modulation (PWM) module with up to 8 x 8-bit channels
Up to 8-channel, 10-bit resolution successive approximation analog-to-digital converter (ATD)
Up to 40x4 LCD driver
PWM motor controller (MC) with up to 16 high current drivers
Output slew rate control on Motor driver pad
One serial peripheral interface (SPI) module
One Inter-IC bus interface (IIC) module
One serial communication interface (SCI) module supporting LIN communications
One multi-scalable controller area network (MSCAN) module (supporting CAN protocol 2.0A/B)
On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages
Autonomous periodic interrupt (API)
Up to 22 key wakeup inputs
1.3 Module Features
The following sections provide more details of the modules implemented on the MC9S12HY/HA family.
1.3.1 S12 16-Bit Central Processor Unit (CPU)
The S12 CPU is a high-speed, 16-bit processing unit that has a programming model identical to that of the
industry standard M68HC11 central processor unit (CPU).
Full 16-bit data paths support efficient arithmetic operation and high-speed math execution
Supports instructions with odd byte counts, including many single-byte instructions. This allows
much more efficient use of ROM space.
Extensive set of indexed addressing capabilities, including:
Using the stack pointer as an indexing register in all indexed operations
Using the program counter as an indexing register in all but auto increment/decrement mode
Device Overview MC9S12HY/HA-Family
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14 Freescale Semiconductor
Accumulator offsets using A, B, or D accumulators
Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)
1.3.2 On-Chip Flash with ECC
On-chip flash memory on the MC9S12HY/HA features the following:
Up to 64 KB of program flash memory
32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
Erase sector size 512 bytes
Automated program and erase algorithm
User margin level setting for reads
Protection scheme to prevent accidental program or erase
4 KB data flash space
16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
Erase sector size 256 bytes
Automated program and erase algorithm
User margin level setting for reads
1.3.3 On-Chip SRAM
Up to 4 KB of general-purpose RAM, no single cycle misaligned access
1.3.4 Main External Oscillator (XOSC)
Loop control Pierce oscillator using a 4 MHz to 16 MHz crystal
Current gain control on amplitude output
Signal with low harmonic distortion
Low power
Good noise immunity
Eliminates need for external current limiting resistor
Transconductance sized for optimum start-up margin for typical crystals
1.3.5 Internal RC Oscillator (IRC)
Trimmable internal reference clock.
Frequency: 1 MHz
Trimmed accuracy over –40˚C to +125˚C ambient temperature range: ±2.0%
Trimmed accuracy over –40˚C to +85˚C ambient temperature range: ±1.5%
Device Overview MC9S12HY/HA-Family
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Freescale Semiconductor 15
1.3.6 Internal Phase-Locked Loop (IPLL)
Phase-locked-loop clock frequency multiplier
No external components required
Reference divider and multiplier allow large variety of clock rates
Automatic bandwidth control mode for low-jitter operation
Automatic frequency lock detector
Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
Reference clock sources:
External 4–16 MHz resonator/crystal (XOSC)
Internal 1 MHz RC oscillator (IRC)
1.3.7 System Integrity Support
Power-on reset (POR)
System reset generation
Illegal address detection with reset
Low-voltage detection with interrupt or reset
Real time interrupt (RTI)
Computer operating properly (COP) watchdog
Configurable as window COP for enhanced failure detection
Initialized out of reset using option bits located in flash memory
Clock monitor supervising the correct function of the oscillator
Temperature sensor
1.3.8 Timer (TIM0)
8 x 16-bit channels for input capture
8 x 16-bit channels for output compare
16-bit free-running counter with 7-bit precision prescaler
1 x 16-bit pulse accumulator
1.3.9 Timer (TIM1)
8 x 16-bit channels for input capture
8 x 16-bit channels for output compare
16-bit free-running counter with 7-bit precision prescaler
1 x 16-bit pulse accumulator
Device Overview MC9S12HY/HA-Family
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16 Freescale Semiconductor
1.3.10 Liquid Crystal Display Driver (LCD)
Configurable for up to 40 frontplanes and 4 backplanes or general-purpose input or output
5 modes of operation allow for different display sizes to meet application requirements
Unused frontplane and backplane pins can be used as general-purpose I/O
1.3.11 Motor Controller (MC)
PWM motor controller (MC) with up to 16 high current drivers
Each PWM channel switchable between two drivers in an H-bridge configuration
Left, right and center aligned outputs
Support for sine and cosine drive
Dithering
Output slew rate control
1.3.12 Pulse Width Modulation Module (PWM)
8 channel x 8-bit or 4 channel x 16-bit pulse width modulator
Programmable period and duty cycle per channel
Center-aligned or left-aligned outputs
Programmable clock select logic with a wide range of frequencies
1.3.13 Inter-IC Bus Module (IIC)
1 Inter-IC (IIC) bus module
Multi-master operation
Soft programming for one of 256 different serial clock frequencies
General Call (Broadcast) mode support
10-bit address support
1.3.14 Controller Area Network Module (MSCAN)
1 Mbit per second, CAN 2.0 A, B software compatible
Standard and extended data frames
0–8 bytes data length
Programmable bit rate up to 1 Mbps
Five receive buffers with FIFO storage scheme
Three transmit buffers with internal prioritization
Flexible identifier acceptance filter programmable as:
2 x 32-bit
4 x 16-bit
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Freescale Semiconductor 17
8 x 8-bit
Wakeup with integrated low pass filter option
Loop back for self test
Listen-only mode to monitor CAN bus
Bus-off recovery by software intervention or automatically
16-bit time stamp of transmitted/received messages
1.3.15 Serial Communication Interface Module (SCI)
Full-duplex or single-wire operation
Standard mark/space non-return-to-zero (NRZ) format
Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
13-bit baud rate selection
Programmable character length
Programmable polarity for transmitter and receiver
Active edge receive wakeup
Break detect and transmit collision detect supporting LIN
1.3.16 Serial Peripheral Interface Module (SPI)
Configurable 8- or 16-bit data size
Full-duplex or single-wire bidirectional
Double-buffered transmit and receive
Master or slave mode
MSB-first or LSB-first shifting
Serial clock phase and polarity options
1.3.17 Analog-to-Digital Converter Module (ATD)
Up to 8-channel, 10-bit analog-to-digital converter
—3µs single conversion time
8-/10 bit resolution
Left or right justified result data
Internal oscillator for conversion in stop modes
Wakeup from low power modes on analog comparison > or <= match
Continuous conversion mode
Multiple channel scans
Pins can also be used as digital I/O
Device Overview MC9S12HY/HA-Family
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18 Freescale Semiconductor
1.3.18 On-Chip Voltage Regulator (VREG)
Linear voltage regulator with bandgap reference
Low-voltage detect (LVD) with low-voltage interrupt (LVI)
Power-on reset (POR) circuit
Low-voltage reset (LVR)
High temperature sensor
1.3.19 Background Debug (BDM)
Non-intrusive memory access commands
Supports in-circuit programming of on-chip nonvolatile memory
1.3.20 Debugger (DBG)
Trace buffer with depth of 64 entries
Three comparators (A, B and C)
Comparators A compares the full address bus and full 16-bit data bus
Exact address or address range comparisons
Two types of comparator matches
Tagged This matches just before a specific instruction begins execution
Force This is valid on the first instruction boundary after a match occurs
Four trace modes
Four stage state sequencer
Device Overview MC9S12HY/HA-Family
MC9S12HY/HA-Family Reference Manual, Rev. 1.05
Freescale Semiconductor 19
1.4 Block Diagram
Figure 1-1 shows a block diagram of the MC9S12HY/HA-Family devices
Figure 1-1. MC9S12HY/HA-Family 100 LQFP Block Diagram
2K/4K bytes RAM
RESET
EXTAL
XTAL
4K bytes Data Flash
BKGD
VDDR
Periodic Interrupt
Clock Monitor
Single-wire Background
TEST
Voltage Regulator
Debug Module
ATD
Multilevel
Interrupt Module
PTAD(KWU)
SCI
SS
SCK
MOSI
MISO
SPI
AN[7:0]
PAD[7:0]
10-bit 8-channel
Analog-Digital Converter
TIM1
Asynchronous Serial IF
8-bit 8channel
Pulse Width Modulator
PWM
IRQ
XIRQ
ECLK
PA 4
PA 3
PA 2
PA 1
PA 0
PA 7
PA 6
PA 5
PTA
32K/48K/64K bytes Flash
CPU12-V1
Amplitude Controlled
Low Power Pierce or
Full drive Pierce
Oscillator
COP Watchdog
PLL with Frequency
Modulation option
Debug Module
3 address breakpoints
1 data breakpoints
64 Byte Trace Buffer
Reset Generation
and Test Entry
RXD
TXD
CAN(HY family only)
PR3
PR0
PR1
PR2
PTR(KWU)
msCAN 2.0B
RXCAN
TXCAN
PR4
PR5
Synchronous Serial IF
Auto. Periodic Int.
PT3
PT0
PT1
PT2
PTT(KWU)
PT7
PT4
PT5
PT6
PP3
PP0
PP1
PP2
PTP
PP7
PP4
PP5
PWM3
PWM0
PWM1
PWM2
PWM4
PWM5
PWM6
IOC1_3
IOC1_0
IOC1_1
IOC1_2
IOC1_7
IOC1_4
IOC1_5
IOC1_6
VDDA/VRH
VSSA/VRL
VDDX/VSSX
VDDM2/VSSM2
5V IO Supply
VSS3
VSSPLL
PP6
PWM7
VDDM1/VSSM1
PU4
PU3
PU2
PU1
PU0
PU7
PU6
PU5
PTU
Motor Driver0
PV4
PV3
PV2
PV1
PV0
PV7
PV6
PV5
PTV
Motor Driver1
Motor Driver2
Motor Driver3
PB3
PB0
PB1
PB2
PTB
PB4
PB5
PH3
PH0
PH1
PH2
40 X 4 LCD display
PH4
PH5
IIC SDA
SCL
PH6
PH7
VLCD
PR6
PR7
PS3
PS0
PS1
PS2
PTS(KWU)
PS4
PS5
PS6
PS7
PB6
PB7
PTH
TIM0
IOC0_3
IOC0_0
IOC0_1
IOC0_2
IOC0_7
IOC0_4
IOC0_5
IOC0_6
VDDA/VSSA
Device Overview MC9S12HY/HA-Family
MC9S12HY/HA-Family Reference Manual, Rev. 1.05
20 Freescale Semiconductor
1.5 Device Memory Map
Table 1-2 shows the device register memory map.
Table 1-2. Device Register Memory Map (Sheet 1 of 2)
Address Module Size
(Bytes)
0x0000–0x0009 PIM (port integration module)10
0x000A–0x000B MMC (memory map control) 2
0x000C–0x000D PIM (port integration module) 2
0x000E–0x000F Reserved 2
0x0010–0x0017 MMC (memory map control) 8
0x0018–0x0019 Reserved 2
0x001A–0x001B Device ID register 2
0x001C–0x001F PIM (port integration module) 4
0x0020–0x002F DBG (debug module) 16
0x0030–0x0033 Reserved 4
0x0034–0x003F CPMU (clock and power management) 12
0x0040–0x006F TIM0 (timer module) 48
0x0070–0x009F ATD (analog-to-digital converter 10 bit 8-channel) 48
0x00A0–0x00C7 PWM (pulse-width modulator 8 channels) 40
0x00C8–0x00CF SCI (serial communications interface) 8
0x00D0–0x00D7 Reserved 8
0x00D8–0x00DF SPI (serial peripheral interface) 8
0x00E0–0x00E7 IIC (Inter IC bus) 8
0x00E8–0x00FF Reserved 24
0x0100–0x0113 FTMRC control registers 20
0x0114–0x011F Reserved 12
0x0120 INT (interrupt module) 1
0x0121–0x013F Reserved 31
0x0140–0x017F CAN 64
0x0180–0x01BF Reserved 64
0x1C0–0x1FF MC (motor controller) 64
0x0200–0x021F LCD 32
0x0220–0x023F Reserved 32
0x0240–0x029F PIM (port integration module) 96
0x02A0–0x02CF TIM1 (timer module) 48
0x02D0–0x02EF Reserved 32
0x02F0–0x02FF CPMU (clock and power management) 16
Device Overview MC9S12HY/HA-Family
MC9S12HY/HA-Family Reference Manual, Rev. 1.05
Freescale Semiconductor 21
NOTE
Reserved register space shown in Table 1-2 is not allocated to any module.
This register space is reserved for future use. Writing to these locations has
no effect. Read access to these locations returns zero.
Figure 1-2,Figure 1-3 and Figure 1-4 shows S12HY/HA family CPU and BDM local address translation
to the global memory map. It indicates also the location of the internal resources in the memory map.
Table 1-3 shows the mapping of D-Flash and unpaged P-Flash memory. The whole 256K global memory
space is visible through the P-Flash window located in the 64K local memory map located at 0x8000
0xBFFF using the PPAGE register.
Table 1-4. MC9S12HY/MC9S12HA Derivatives
0x0300–0x03FF Reserved 256
Table 1-3. MC9S12HY/MC9S12HA -Family mapping for D-Flash and unpaged P-Flash
Local 64K memory map Global 256K memory map
D-Flash 0x0400 - 0x13FF 0x0_4400 - 0x0_53FF
P-Flash
0x1400 - 0x2FFF(1)
1. 0x2FFF for MC9S12HY64 because of 4K RAM size
0x3_1400 -0x3_2FFF(2)
2. 0x3_2FFF for MC9S12HY64 because of 4K RAM size
0x4000 - 0x7FFF 0x3_4000 - 0x3_7FFF
0xC000 - 0xFFFF 0x3_C000 - 0x3_FFFF
Feature MC9S12HY32
MC9S12HA32 MC9S12HY48
MC9S12HA48 MC9S12HY64
MC9S12HA64
P-Flash size 32KB 48KB 64KB
PF_LOW
PPAGES 0x3_8000
0x0E - 0x0F 0x3_4000
0x0D - 0x0F 0x3_0000
0x0C - 0x0F
RAMSIZE 2KB 4KB 4KB
RAM_LOW 0x0_3800 0x0_3000 0x0_3000
Table 1-2. Device Register Memory Map (Sheet 2 of 2)
Address Module Size
(Bytes)
Device Overview MC9S12HY/HA-Family
MC9S12HY/HA-Family Reference Manual, Rev. 1.05
22 Freescale Semiconductor
Figure 1-2. MC9S12HY64/HA64-Family Global Memory Map
0x3_FFFF
PPAGE
CPU and BDM
Local Memory Map Global Memory Map
0xFFFF
0xC000
0x8000
P-Flash window
PF_LOW=0x3_4000
PF_LOW=0x3_8000
PF_LOW=0x3_C000
0x0_4000
0x0000
0x4000
0x0400 D-Flash
RAM
Unpaged P-Flash
REGISTERS
Unpaged P-Flash
Unpaged P-Flash
0
P0
P1P2P3
000
0x1400
RAMSIZE
0x0_0000
RAM
RAMSIZE
10 *16K paged
P-Flash
PF_LOW=0x0_8000
NVM Resources
REGISTERS
RAM_LOW
Unpaged P-Flash
PF_LOW=0x3_0000
Unimplemented Area
Unpaged P-Flash
Unpaged P-Flash
(PPAGE 0x0C) (PPAGE 0x0D) (PPAGE 0x0E) (PPAGE 0x0F)
Unpaged P-Flash
or
(PPAGE 0x02-0x0B))
(PPAGE 0x01)
(PPAGE 0x00)
Unpaged P-Flash
0x0_4400 D-Flash
0x0_5400
NVM Resources
Device Overview MC9S12HY/HA-Family
MC9S12HY/HA-Family Reference Manual, Rev. 1.05
Freescale Semiconductor 23
Figure 1-3. MC9S12HY48/HA48-Family Global Memory Map
0x3_FFFF
PPAGE
CPU and BDM
Local Memory Map Global Memory Map
0xFFFF
0xC000
0x8000
P-Flash window
PF_LOW=0x3_4000
PF_LOW=0x3_8000
PF_LOW=0x3_C000
0x0_4000
0x0000
0x4000
0x0400 D-Flash
RAM
REGISTERS
Unpaged P-Flash
Unpaged P-Flash
0
P0
P1P2P3
000
0x1400
RAMSIZE
0x0_0000
RAM
RAMSIZE
10 *16K paged
P-Flash
PF_LOW=0x0_8000
NVM Resources
REGISTERS
RAM_LOW
Unpaged P-Flash
PF_LOW=0x3_0000
Unimplemented Area
Unpaged P-Flash
Unpaged P-Flash
(PPAGE 0x0C) (PPAGE 0x0D) (PPAGE 0x0E) (PPAGE 0x0F)
Unpaged P-Flash
or
(PPAGE 0x02-0x0B))
(PPAGE 0x01)
(PPAGE 0x00)
0x0_4400 D-Flash
0x0_5400
NVM Resources
Reserved
Unpaged P-Flash
Device Overview MC9S12HY/HA-Family
MC9S12HY/HA-Family Reference Manual, Rev. 1.05
24 Freescale Semiconductor
Figure 1-4. MC9S12HY32/HA32-Family Global Memory Map
0x3_FFFF
PPAGE
CPU and BDM
Local Memory Map Global Memory Map
0xFFFF
0xC000
0x8000
P-Flash window
PF_LOW=0x3_4000
PF_LOW=0x3_8000
PF_LOW=0x3_C000
0x0_4000
0x0000
0x4000
0x0400 D-Flash
RAM
REGISTERS
Reserved
Unpaged P-Flash
0
P0
P1P2P3
000
0x1400
RAMSIZE
0x0_0000
RAM
RAMSIZE
10 *16K paged
P-Flash
PF_LOW=0x0_8000
NVM Resources
REGISTERS
RAM_LOW
Unpaged P-Flash
PF_LOW=0x3_0000
Unimplemented Area
Unpaged P-Flash
Unpaged P-Flash
(PPAGE 0x0C) (PPAGE 0x0D) (PPAGE 0x0E) (PPAGE 0x0F)
Unpaged P-Flash
or
(PPAGE 0x02-0x0B))
(PPAGE 0x01)
(PPAGE 0x00)
0x0_4400 D-Flash
0x0_5400
NVM Resources
Reserved
Unpaged P-Flash
Device Overview MC9S12HY/HA-Family
MC9S12HY/HA-Family Reference Manual, Rev. 1.05
Freescale Semiconductor 25
1.6 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B).
The read-only value is a unique part ID for each revision of the chip. Table 1-5 shows the assigned part ID
number and Mask Set number.
The Version ID in Table 1-5 is a word located in a flash information row at address 0x040B6. The version
ID number indicates a specific version of internal NVM controller.
1.7 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the
individual IP blocks on the device.
Table 1-5. Assigned Part ID Numbers
Device Mask Set Number Part ID(1)
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-6: Minor family identifier
Bit 5-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor — non full — mask set revision
Version ID
MC9S12HY64 0M34S $1A80 $00
MC9S12HY48 0M34S $1A80 $00
MC9S12HY32 0M34S $1A80 $00
MC9S12HA64 0M34S $1A80 $00
MC9S12HA48 0M34S $1A80 $00
MC9S12HA32 0M34S $1A80 $00
Device Overview MC9S12HY/HA-Family
MC9S12HY/HA-Family Reference Manual, Rev. 1.05
26 Freescale Semiconductor
1.7.1 Device Pinout
Figure 1-5. MC9S12HY/HA-Family 100 LQFP pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PA1 / XIRQ / FP30
PA0 / IRQ / FP29
XTAL
EXTAL
VSSPLL
VSS3
VDDR
PB0 / FP28
PR7 / FP27
PH7 / FP26
PH6 / FP25
PH5 / FP24
PH4 / FP23
VDDX
VSSX
PH3 / SS / SDA / FP22
PH2 / ECLK / SCK / FP21
PH1 / MOSI / FP20
PH0 / MISO / SCL / FP19
PR6 / SCL / FP18
PR5 / SDA / FP17
PT7 / IOC0_7 / KWT7 / FP16
PT6 / IOC0_6 / KWT6 / FP15
PT5 / IOC0_5 / KWT5 / FP14
PT4 / IOC0_4 / KWT4 / FP13
TXD / PWM7 / PS1
RXCAN / PS2
TXCAN / PS3
MISO / SCL / PWM0 / PS4
KWS5 / MOSI / PWM1 / PS5
KWS6 / SCK / PWM2 / PS6
SS / SDA / PWM3 / PS7
KWR0 / IOC0_6 / PR0
KWR1 / IOC0_7 / PR1
KWR2 / IOC1_6 / PR2
KWR3 / IOC1_7 / PR3
FP0 / PWM0 / PP0
FP1 / PWM1 / PP1
FP2 / PWM2 / PP2
FP3 / PWM3 / PP3
FP4 / PWM4 / PP4
FP5 / PWM5 / PP5
FP6 / PWM6 / PP6
FP7 / PWM7 / PP7
FP8 / KWT0 / IOC1_4 / PT0
FP9 / KWT1 / IOC1_5 / PT1
FP10 / KWT2 / IOC1_6 / PT2
FP11 / KWT3 / IOC1_7 / PT3
FP12 / PR4
RESET
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
MC9S12HY/HA-Family
100 LQFP
TEST
NC
M0C0M / IOC0_0 / PU0
M0C0P / PU1
M0C1M / IOC0_1 / PU2
M0C1P / PU3
VDDM1
VSSM1
M1C0M / IOC0_2 / PU4
M1C0P / PU5
M1C1M / IOC0_3 / PU6
M1C1P / PU7
M2C0M / IOC1_0 / SCL / PWM4 / MISO / PV0
M2C0P / MOSI / PWM5 / PV1
M2C1M / IOC1_1 / SCK / PWM6 / PV2
M2C1P / SDA / PWM7 / SS / PV3
VDDM2
VSSM2
M3C0M / IOC1_2 / PV4
M3C0P / PV5
M3C1M / IOC1_3 / PV6
M3C1P / PV7
NC
NC
RXD / PWM6 / PS0
PAD07 / AN07 / KWAD7
PAD06 / AN06 / KWAD6
PAD05 / AN05 / KWAD5
PAD04 / AN04 / KWAD4
PAD03 / AN03 / KWAD3
PAD02 / AN02 / KWAD2
PAD01 / AN01 / KWAD1
PAD00 / AN00 / KWAD0
VDDA / VRH
VSSA / VRL
BKGD / MODC
VLCD
PB7 / BP3
PB6 / BP2
PB5 / BP1
PB4 / BP0
PB3 / FP39
PB2 / FP38
PB1 / FP37
PA7 / FP36
PA6 / FP35
PA5 / FP34
PA4 / FP33
PA3 / API_EXTCLK / FP32
PA2 / FP31
Pins shown in BOLD are
not available on the
64 LQFP package
Device Overview MC9S12HY/HA-Family
MC9S12HY/HA-Family Reference Manual, Rev. 1.05
Freescale Semiconductor 27
Figure 1-6. MC9S12HY/HA-Family 64 LQFP pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
MC9S12HY/HA-
Family
64 LQFP
TXD / PWM7 / PS1
RXCAN / PS2
TXCAN / PS3
KWR0 / IOC0_6 / PR0
KWR1 / IOC0_7 / PR1
KWR2 / IOC1_6 / PR2
KWR3 / IOC1_7 / PR3
FP0 / PWM0 / PP0
FP1 / PWM1 / PP1
FP2 / PWM2 / PP2
FP3 / PWM3 / PP3
FP8 / KWT0 / IOC1_4 / PT0
FP9 / KWT1 / IOC1_5 / PT1
FP10 / KWT2 / IOC1_6 / PT2
FP11 / KWT3 / IOC1_7 / PT3
RESET
TEST
M0C0M / IOC0_0 / PU0
M0C0P / PU1
M0C1M / IOC0_1 / PU2
M0C1P / PU3
VDDM1
VSSM1
M1C0M / IOC0_2 / PU4
M1C0P / PU5
M1C1M / IOC0_3 / PU6
M1C1P / PU7
M2C0M / IOC1_0 / SCL / PWM4 / MISO / PV0
M2C0P / MOSI / PWM5 / PV1
M2C1M / IOC1_1 / SCK / PWM6 / PV2
M2C1P / SDA / PWM7 / SS / PV3
RXD / PWM6 / PS0
PAD05 / AN05 / KWAD5
PAD04 / AN04 / KWAD4
PAD03 / AN03 / KWAD3
PAD02 / AN02 / KWAD2
PAD01 / AN01 / KWAD1
PAD00 / AN00 / KWAD0
VDDA / VRH
VSSA / VRL
BKGD / MODC
VLCD
PB7 / BP3
PB6 / BP2
PB5 / BP1
PB4 / BP0
PA3 / API_EXTCLK / FP32
PA2 / FP31
PA1 / XIRQ / FP30
PA0 / IRQ / FP29
XTAL
EXTAL
VSS3 / VSSPLL
VDDR
VDDX
VSSX
PH3 / SS / SDA / FP22
PH2 / ECLK / SCK / FP21
PH1 / MOSI / FP20
PH0 / MISO / SCL / FP19
PT7 / IOC0_7 / KWT7 / FP16
PT6 / IOC0_6 / KWT6 / FP15
PT5 / IOC0_5 / KWT5 / FP14
PT4 / IOC0_4 / KWT4 / FP13
Device Overview MC9S12HY/HA-Family
MC9S12HY/HA-Family Reference Manual, Rev. 1.05
28 Freescale Semiconductor
1.7.2 Pin Assignment Overview
Table 1-6 provides a summary of which ports are available for each package option. Routing of pin
functions is summarized in Table 1-7.
Table 1-6. Port Availability by Package Option
Port 100 LQFP 64 LQFP
Port AD/ADC Channels 8/8 6/6
Port A 8 4
Port B 8 4
Port H 8 4
Port P 8 4
Port R 8 4
Port S 8 4
Port T 8 8
Port U 8 8
Port V 8 4
Sum of Ports 80 50
I/O Power Pairs VDDM/VSSM 2/2 1/1
I/O Power Pairs VDDX/VSSX 1/1 1/1
I/O Power Pairs VDDA/VSSA(1)
1. VRH/VRL are sharing with VDDA/VSSA pins
1/1 1/1
VREG Power Pairs VDDR/VSS3 1/1 1/1
I/O Power Pair VSSPLL 1 0(2)
2. Double bond with VSS3 on 64LQFP package
VLCD power 1 1