TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 HIGH-EFFICIENCY, MIDRANGE-INPUT, SYNCHRONOUS BUCK CONTROLLER WITH VOLTAGE FEED-FORWARD FEATURES CONTENTS 1 * Operation Over 4.5-V to 28-V Input Range * Programmable, Fixed-Frequency, up to 1-MHz, Voltage-Mode Controller * Predictive Gate DriveTM Anti-Cross-Conduction Circuitry * <1% Internal 700-mV Reference * Internal Gate Drive Outputs for High-Side and Synchronous N-Channel MOSFETs * 16-Pin PowerPADTM Package * Thermal Shutdown Protection * Pre-Bias Compatible * Power-Stage Shutdown Capability * Programmable High-Side Sense Short-Circuit Protection 23 Device Ratings. . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics. . . . . . . . . . . . . . . . . 4 Terminal Information. . . . . . . . . . . . . . . . . . . . 11 Application Information. . . . . . . . . . . . . . . . . . 14 Example Applications. . . . . . . . . . . . . . . . . . . 23 References. . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DESCRIPTION The TPS40077 is a midvoltage, wide-input (4.5-V to 28-V), synchronous, step-down controller, offering design flexibility for a variety of user-programmable functions, including soft start, UVLO, operating frequency, voltage feed-forward, and high-side, FET-sensed, short-circuit protection. APPLICATIONS * * * * * Power Modules Networking/Telecom PCI Express Industrial Servers SIMPLIFIED APPLICATION DIAGRAM TPS40077PWP VDD 1 2 Powergood KFF ILIM RT VDD 3 LVPB 4 PGD 5 SGND 6 16 VDD 15 BOOST 14 HDRV 13 SW 12 SS DBP 11 7 FB LDRV 10 8 COMP PGND 9 VOUT VOUT UDG-09041 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Predictive Gate Drive, PowerPAD are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007-2009, Texas Instruments Incorporated TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com DESCRIPTION (CONTINUED) The TPS40077 drives external N-channel MOSFETs using second-generation, predictive-gate drive to minimize conduction in the body diode of the low-side FET and maximize efficiency. Pre-biased outputs are supported by not allowing the low-side FET to turn on until the voltage commanded by the closed-loop soft start is greater than the pre-bias voltage. Voltage feed-forward provides good response to input transients and provides a constant PWM gain over a wide input-voltage operating range to ease compensation requirements. Programmable short-circuit protection provides fault-current limiting and hiccup recovery to minimize power dissipation with a shorted output. The 16-pin PowerPAD package gives good thermal performance and a compact footprint. ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER Plastic HTSSOP (PWP) Tube TPS40077PWP Plastic HTSSOP (PWP) Tape and reel TPS40077PWPR ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPS40077 VDD, ILIM VVDD VOUT Input voltage range Output voltage range 30 COMP, FB, KFF, PGD, LVBP -0.3 to 6 SW -0.3 to 40 SW, transient < 50 ns -2.5 COMP, KFF, RT, SS -0.3 to 6 VBOOST IOUT Output current sink Output current DBP V 10.5 6 LDRV, HDRV 1.5 LDRV, HDRV 2 KFF 10 RT A 1 LVBP mA 1.5 TJ Operating junction temperature range -40 to 125 Tstg Storage temperature -55 to 150 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) V 50 LVBP Output current source UNIT C 260 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VDD Input voltage 4.5 28 V TA Operating free-air temperature -40 85 C ELECTROSTATIC DISCHARGE (ESD) PROTECTION UNIT Human body model (HBM) 2000 V Charged device model (CDM) 1500 V 2 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 PACKAGE DISSIPATION RATINGS Thermal Impedance, Junction-to-Ambient (1) (1) TA = 25C Power Rating TA = 85C Power Rating Natural convection 37C/W 2.7 W 1.08 W 150 LFM airflow 30C/W 3.33 W 1.33 W 250 LFM airflow 28C/W 3.57 W 1.42 W 500 LFM airflow 26C/W 3.84 W 1.52 W For more information on the board and the methods used to determine ratings, see the PowerPAD Thermally Enhanced Package application report (SLMA002). Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 3 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS TA = -40C to 85C, VIN = 12 Vdc, RT = 90.9 k, IKFF = 300 A, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VVDD Input voltage range, VIN 4.5 28 V 2.5 3.5 mA 3.9 4.2 4.5 V 450 500 550 kHz OPERATING CURRENT IVDD Quiescent current Output drivers not switching Output voltage TA = TJ = 25C LVBP VLVBP OSCILLATOR/RAMP GENERATOR fOSC Accuracy VRAMP PWM ramp voltage (1) VRT RT voltage tON Minimum output pulse time (1) VPEAK - VVAL 2.23 Feed-forward voltage IKFF Feed-forward current operating range (1) 2.4 CHDRV = 0 nF Maximum duty cycle VKFF 2 V 2.58 V 150 ns VFB = 0 V, 100 kHz fSW 500 kHz 84% 93% VFB = 0 V, fSW = 1 MHz 76% 93% 0.35 0.4 20 0.45 V 1100 A 17 A 75 s s SOFT START ISS Charge current tDSCH Discharge time CSS = 3.9 nF Soft-start time CSS = 3.9 nF, VSS rising from 0.7 V to 1.6 V tSS VSSSD VSSSDH 7 12 25 210 290 500 Turnon threshold 310 365 420 Shutdown threshold 225 275 325 Shutdown threshold hysteresis 35 mV 150 DBP VDBP Output voltage VDD > 10 V 7 8 VDD = 4.5 V, IOUT = 25 mA 4 4.3 9 V ERROR AMPLIFIER TJ = 25C 0.698 0.7 0.704 0C TJ 85C 0.69 0.7 0.707 -40C TJ 85C 0.69 0.7 0.715 VFB Feedback regulation voltage total variation VSS Soft-start offset from VSS (1) GBW Gain bandwidth (1) AVOL Open-loop gain 50 ISRC Output source current 2.5 4.5 ISINK Output sink current 2.5 6 IBIAS Input bias current (1) 4 Offset from VSS to error amplifier 5 VFB = 0.7 V -250 V 1 V 10 MHz dB mA 0 nA Ensured by design. Not production tested. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ELECTRICAL CHARACTERISTICS (continued) TA = -40C to 85C, VIN = 12 Vdc, RT = 90.9 k, IKFF = 300 A, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 80 105 125 A -75 -50 -30 mV 135 225 ns SHORT-CIRCUIT CURRENT PROTECTION IILIM Current sink into current limit VILIM(ofst) Current limit offset voltage (VSW - VILIM) VILIM = 11.5 V, VVDD = 12 V tHSC Minimum HDRV pulse duration During short circuit Propagation delay to output (2) 50 ns 50 ns tBLANK Blanking time (2) tOFF Off time during a fault (SS cycle times) 7 Cycles VSW Switching level to end precondition (VVDD - VSW) (2) 2 V tPC Precondition time (2) VILIM Current limit precondition voltage threshold (2) 100 ns 6.8 V 36 ns 48 ns 72 ns 96 ns 24 ns 48 ns CLDRV = 2200 pF, VVDD = 4.5 V, 0.2 V VSS 4 V 48 ns IHDRV = -0.01 A 0.7 1 IHDRV = -0.1 A 0.95 1.3 IHDRV = 0.01A 0.06 0.1 IHDRV = 0.1 A 0.65 1 OUTPUT DRIVERS tHFALL High-side driver fall time (HDRV - SW) (2) (2) tHRISE High-side driver rise time (HDRV - SW) tHFALL High-side driver fall time (HDRV - SW) (2) tHRISE High-side driver rise time (HDRV - SW) (2) CHDRV = 2200 pF CHDRV = 2200 pF, VVDD = 4.5 V, 0.2 V VSS 4 V (2) tLFALL Low-side driver fall time tLRISE Low-side driver rise time (2) tLFALL Low-side driver fall time (2) CLDRV = 2200 pF (2) tLRISE Low-side driver rise time VOH High-level output voltage, HDRV (VBOOST - VHDRV) VOL Low-level output voltage, HDRV (VHDRV - VSW) VOH High-level output voltage, LDRV (VDBP - VLDRV) VOL Low-level output voltage, LDRV 96 ns ILDRV= -0.01A 0.65 1 ILDRV = -0.1 A 0.875 1.2 ILDRV = 0.01 A 0.03 0.05 ILDRV = 0.1 A 0.3 0.5 V V V V BOOST REGULATOR VBOOST Output voltage VDD = 12 V 15.2 17 V Programmable UVLO threshold voltage RKFF = 90.9 k, turn-on, VVDD rising 6.2 7.2 8.2 Programmable UVLO hysteresis RKFF = 90.9 k 1.1 1.55 2 Fixed UVLO threshold voltage Turn-on, VVDD rising 4.15 4.3 4.45 275 365 UVLO VUVLO Fixed UVLO hysteresis V mV POWER GOOD VPG Power-good voltage VOH High-level output voltage, FB IPG = 1 mA 370 770 VOL Low-level output voltage, FB 630 500 mV THERMAL SHUTDOWN Shutdown temperature threshold (2) 165 Hysteresis (2) (2) 15 C Ensured by design. Not production tested. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 5 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS LVBP VOLTAGE vs JUNCTION TEMPERATURE DBP VOLTAGE vs JUNCTION TEMPERATURE 8.15 4.30 8.10 VDD = 28 V VDD = 28 V VDBP - DBP Voltage - V VLVPP - LVBP Voltage - V 4.25 4.20 VDD = 12 V 4.15 4.10 4.05 8.05 8.00 VDD = 12 V 7.95 7.90 7.85 4.00 -50 -25 0 25 50 100 75 7.80 -50 125 -25 50 75 Figure 2. DBP VOLTAGE vs JUNCTION TEMPERATURE BOOTSTRAP DIODE VOLTAGE vs JUNCTION TEMPERATURE 100 125 2.0 VDD = 4.5 V ILOAD = 25 mA 1.9 VDROP - Bootstrap Diode Voltage Drop - V 4.49 4.48 VDBP - DBP Voltage - V 25 Figure 1. 4.50 4.47 4.46 4.45 4.44 4.43 4.42 4.41 4.40 -50 -25 0 25 50 75 100 125 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 -50 -25 TJ - Junction Temperature - C Figure 3. 6 0 TJ - Junction Temperature - C TJ - Junction Temperature - C 0 25 50 75 100 125 TJ - Junction Temperature - C Figure 4. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 TYPICAL CHARACTERISTICS (continued) CURRENT LIMIT OFFSET VOLTAGE vs JUNCTION TEMPERATURE CURRENT LIMIT SINK CURRENT vs JUNCTION TEMPERATURE 150 145 -10 IILIM - Current Limit Sink Current - A VILIM(offst) - Current Limit Offset Voltage Drop - mV 0 +3 S -20 Average -30 -40 -3 S -50 -60 -50 -25 0 25 50 75 100 140 135 130 125 120 115 VDD 28 V 12 V 4.5 V 110 105 100 -50 125 -25 TJ - Junction Temperature - C 25 50 75 Figure 5. Figure 6. FEEDBACK REGULATION VOLTAGE vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs INPUT VOLTAGE 704 100 125 500 RRT = 90.1k VDD 28 V 4.5 V 12 V 499 fSW - Switching Frequency - kHz 703 VFB - Feedback Voltage - V 0 TJ - Junction Temperature - C 702 701 700 699 698 498 497 496 495 494 493 492 491 697 -50 490 -25 0 25 50 75 100 125 4 TJ - Junction Temperature - C Figure 7. 8 12 16 20 VVDD - Input Voltage - V 24 28 Figure 8. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 7 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) MAXIMUM DUTY CYCLE vs JUNCTION TEMPERATURE UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE 93 VUVLO - Undervoltage Lockout Threshold - V 4.35 DMAX - Maximum Duty Cycle - % 92 91 fSW = 100 kHZ 90 89 88 fSW = 500 kHZ 87 86 85 fSW = 1 MHZ 84 83 -50 -25 0 25 50 75 100 TJ - Junction Temperature - C 4.20 4.15 4.10 4.05 4.00 VUVLO(off) 3.95 -25 0 25 50 75 100 TJ - Junction Temperature - C Figure 10. PROGRAMMABLE UVLO THRESHOLD vs JUNCTION TEMPERATURE SOFT-START CHARGING CURRENT vs JUNCTION TEMPERATURE 125 14.0 1.08 VUVLO(off) VUVLO(on) 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 -25 0 25 50 75 100 125 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 -50 TJ - Junction Temperature - C -25 0 25 50 75 100 125 TJ - Junction Temperature - C Figure 11. 8 VUVLO(on) Figure 9. ISS - Soft-Start Charging Current - A VUVLO - Relative Programmable UVLO Threshold - % 4.25 3.90 -50 125 1.10 0.90 -50 4.30 Figure 12. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 TYPICAL CHARACTERISTICS (continued) ERROR AMPLIFIER INPUT BIAS CURRENT vs JUNCTION TEMPERATURE MINIMUM OUTPUT VOLTAGE vs FREQUENCY 5.0 -10 -20 -30 -40 -50 -60 VIN = 8 V 2.5 2.0 1.0 25 50 75 100 0.5 100 125 VIN = 10 V 3.0 -80 0 VIN = 18 V VIN = 15 V VIN = 12 V 3.5 1.5 -25 VIN = 24 V 4.0 -70 -90 -50 VIN = 28 V 4.5 VOUT - Output Voltage - V IBIAS - Error Amplifier Input Bias Current - nA 0 VIN = 5 V 300 400 500 600 700 800 900 1000 fOSC - Oscillator Frequency - kHz 200 TJ - Junction Temperature - C Figure 13. Figure 14. SWITCHING FREQUENCY vs TIMING RESISTANCE UNDERVOLTAGE LOCKOUT THRESHOLD vs FEED-FORWARD IMPEDANCE 600 20 VUVLO - Programmable UVLO Threshold - V fSW = 300 kHz RT - Timing Resistance - k 500 400 300 200 100 0 0 200 400 600 800 fSW - Switching Frequency - kHz 1000 UVLOVON 18 16 14 12 UVLOVOFF 10 8 6 4 2 100 150 200 250 300 350 400 450 RKFF - Feedforward Impedance - k G017 Figure 15. Figure 16. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 9 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) UNDERVOLTAGE LOCKOUT THRESHOLD vs FEED-FORWARD IMPEDANCE UNDERVOLTAGE LOCKOUT THRESHOLD vs FEED-FORWARD IMPEDANCE 20 20 fSW = 750 kHz UVLOVON 18 VUVLO - Programmable UVLO Threshold - V VUVLO - Programmable UVLO Threshold - V fSW = 500 kHz 16 14 12 UVLOVOFF 10 8 6 4 2 UVLOVON 18 16 14 12 UVLOVOFF 10 8 6 4 2 60 90 120 150 180 210 240 RKFF - Feedforward Impedance - k Figure 17. 270 40 60 80 100 120 140 160 RKFF - Feedforward Impedance - k Figure 18. TYPICAL MAXIMUM DUTY CYCLE vs INPUT VOLTAGE 100 180 DBP VOLTAGE vs INPUT VOLTAGE 10 UVLO(on) = 15 V VDBP - Driver Bypass Voltage - V 90 80 Duty Cycle - % UVLO(on) = 8 V UVLO(on) = 12 V 70 60 UVLO(on) = 4.5 V 50 40 9 8 7 6 5 30 4 20 4 8 12 16 20 VIN - Input Voltage - V 24 28 0 10 15 VDD - Input Voltage - V 20 25 G024 G023 Figure 19. 10 5 Figure 20. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 TYPICAL CHARACTERISTICS (continued) INPUT VOLTAGE vs LOW-VOLTAGE BYPASS VOLTAGE VDBP - Low Voltage Bypass Voltage - V 4.50 4.45 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 5 10 15 20 25 VDD - Input Voltage - V 30 G025 Figure 21. DEVICE INFORMATION Terminal Configuration PWP PACKAGE (TOP VIEW) KFF RT LVBP PGD SGND SS FB COMP (1) 1 16 2 3 15 4 5 14 Thermal Pad 13 12 6 11 7 10 8 9 ILIM VDD BOOST HDRV SW DBP LDRV PGND P0047-01 (1) For more information on the PWP package, see the PowerPAD Thermally Enhanced Package technical brief (SLMA002). Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 11 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com Table 1. Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. BOOST 14 I The peak voltage on BOOST is equal to the SW node voltage plus the voltage present at DBP less the bootstrap diode drop. This drop can be 1.4 V for the internal bootstrap diode or 300 mV for an external Schottky diode. The voltage differential between this pin and SW is the available drive voltage for the high-side FET. COMP 8 O Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the FB pin to compensate the overall loop. The COMP pin is internally clamped to 3.4 V. DBP 11 O 8-V reference used for the gate drive of the N-channel synchronous rectifier. This pin should be bypassed to ground with a 1-F ceramic capacitor. FB 7 I Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal reference voltage, 0.7 V. HDRV 13 O Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW (MOSFET off). ILIM 16 I Short-circuit-protection programming pin. This pin is used to set the short circuit detection threshold. An internal current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD. The voltage on this pin is compared to the voltage drop (VVDD - VSW) across the high side N-channel MOSFET during conduction. Just prior to the beginning of a switching cycle, this pin is pulled to approximately VDD/2 and released when SW is within 2 V of VDD or after a timeout (the precondition time), whichever occurs first. Placing a capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch-on time, effectively programming the ILIM blanking time. See Application Information. KFF 1 I A resistor connected from this pin to VIN programs the amount of feed-forward voltage. The current fed into this pin is internally divided by 25 and used to control the slope of the PWM ramp and program undervoltage lockout. Nominal voltage at this pin is maintained at 400 mV. LDRV 10 O Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to ground (MOSFET off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50 nC. LVBP 3 O 4.2-V reference used for internal device logic only. This pin should be bypassed by a 0.1-F ceramic capacitor. External loads that are less than 1 mA and electrically quiet may be applied. PGD 4 O This is an open-drain output that pulls to ground when soft start is active, or when the FB pin is outside a 10% band around VREF. PGND 9 - Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the lower MOSFET(s). RT 2 I A resistor is connected from this pin to ground to set the internal oscillator and switching frequency. SGND 5 - Signal ground reference for the device. Low-level quiet circuitry around the IC should connect to this pin. This pin should be connected to the thermal pad under the IC, and that thermal pad should connect to the PGND pin. Do not allow power currents to flow in the thermal pad or in the SGND part of the ground for best results. SS 6 I Soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an internal current source of 12 A. The resulting voltage ramp on the SS pin is used as a second noninverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V less than that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on the SS pin reaches the internal offset voltage of 1 V plus the internal reference voltage of 700 mV. If SS is pulled below 225 mV, the device goes into a shutdown state where the power FETSs are turned off and the prebias circuitry is reset. If the programmed UVLO voltage is below 6 V, connect a 330-k resistor in parallel with the SS capacitor. Also provides timing for fault recovery attempts. SW 12 I This pin is connected to the switched node of the converter. It is used for short-circuit sensing and gate-drive timing information and is the return for the high-side driver. A 1.5- resistor is required in series with this pin for protection against substrate current issues. VDD 15 I Supply voltage for the device. 12 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 FUNCTIONAL BLOCK DIAGRAM 11 DBP VDD VDD 15 LVBP 3 RT 2 Reference Regulator UVLO Controller Ramp Generator Oscillator 16 ILIM UVLO SW CLK Pulse Control 9 KFF 1 PGD 4 SGND RAMP Power Good Logic 5 770 mV FB 630 mV SS Active 12 SW Soft Start and Fault Control SS 6 COMP 8 OC CLK 14 BOOST DBP CLK OC + + Short-Circuit Comparator and Control OC 7 700 mV ILIM CLK SS Active LVBP FB PGND PWM 13 HDRV Predictive Gate Drive Control Logic SW UVLO 10 LDRV FAULT PGND B0150-01 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 13 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com APPLICATION INFORMATION The TPS40077 allows the user to construct synchronous voltage-mode buck converters with inputs ranging from 4.5 V to 28 V and outputs as low as 700 mV. Predictive Gate Drive circuitry optimizes switching delays for increased efficiency and improved converter output-power capability. Voltage feed-forward is employed to ease loop compensation for wide-input-range designs and provide better line transient response. The TPS40077 incorporates circuitry to allow startup into a preexisting output voltage without sinking current from the source of the preexisting output voltage. This avoids damaging sensitive loads at start-up. An integrated power-good indicator is available for logic (open-drain) output of the condition of the output of the converter. MINIMUM PULSE DURATION The TPS40077 devices have limitations on the minimum pulse duration that can be used to design a converter. Reliable operation is assured for nominal pulse durations of 150 ns and above. This places some restrictions on the conversion ratio that can be achieved at a given switching frequency. Figure 14 shows minimum output voltage for a given input voltage and frequency. SLEW RATE LIMIT ON VDD The regulator that supplies power for the drivers on the TPS40077 requires a limited rising slew rate on VDD for proper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can overshoot and damage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than 0.12 V/s as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of the device. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor from the VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor in normal operation. This places some constraints on the R-C values that can be used. Figure 22 is a schematic fragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for R and C that limit the slew rate in the worst-case condition. TPS40077 R ILIM 16 15 VDD VIN + _ HDRV 13 C SW 12 9 PGND LDRV 10 S0203-01 Figure 22. Limiting the Slew Rate 14 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 V IN * 8 V R SR 0.2 V Rt f SW Q g(TOT) ) I DD Cu (1) (2) where * * * * * VVIN is the final value of the input voltage ramp fSW is the switching frequency Qg(TOT) is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet) IDD is the TPS40077 input current (3.5 mA maximum) SR is the maximum allowed slew rate [12 x104] (V/s) SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR) The TPS40077 has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves as the master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the switching frequency of the clock oscillator. The clock frequency is related to RT by: RT + f SW(kHz) 1 17.82 10 *6 * 23 kW (3) PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations, because the PWM is not required to wait for loop delays before changing the duty cycle. (See Figure 23). The PWM ramp must reach approximately 1 V in amplitude during a clock cycle, or the PWM is not allowed to start. The PWM ramp time is programmed via a single resistor (RKFF) connected from KFF VDD. RKFF, VSTART, and RT are related by (approximately): R KFF + 0.131 RT V UVLO(on) * 1.61 10*3 2 V UVLO(on) ) 1.886 V UVLO * 1.363 * 0.02 R T * 4.87 10*5 R 2T (4) where * * RT and RKFF are in k VUVLO(on) is in V This yields typical numbers for the programmed startup voltage. The minimum and maximum values may vary up to 15% from this number. Figure 16 through Figure 18 show the typical relationship of VUVLO(on), VUVLO(off) and RKFF at three common frequencies. The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. For example, if the startup voltage is programmed to be 10 V, the controller starts when VDD reaches 10 V and shuts down when VDD falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twice the startup voltage. Below this point, the maximum duty cycle is as specified in the Electrical Characteristics table. Note that with this scheme, the theoretical maximum output voltage that the converter can produce is approximately two times the programmed startup voltage. For design, set the programmed startup voltage equal to or greater than the desired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz and below). For example, a 5-V output converter should not have a programmed startup voltage below 5.9 V. Figure 23 shows the theoretical maximum duty cycle (typical) for various programmed startup voltages. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 15 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com VIN VIN SW SW RAMP VPEAK COMP COMP RAMP VVALLEY tON1 t d + ON T T1 tON2 T2 tON1 > tON2 and d1 > d2 VDG-03172 Figure 23. Voltage Feed-Forward and PWM Duty Cycle Waveforms PROGRAMMING SOFT START TPS40077 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft start is programmed by connecting an external capacitor (CSS) from the SS pin to GND. This capacitor is charged by a fixed current, generating a ramp signal. The voltage on SS is level-shifted down approximately 1 V and fed into a separate noninverting input to the error amplifier. The loop is closed on the lower of the level-shifted SS voltage or the 700-mV internal reference voltage. Once the level-shifted SS voltage rises above the internal reference voltage, output-voltage regulation is based on the internal reference. To ensure a controlled ramp-up of the output voltage, the soft-start time should be greater than the L-COUT time constant or: t START w 2p L COUT (5) Note that there is a direct correlation between tSTART and the input current required during start-up. The lower tSTART is, the higher the input current required during start-up, because the output capacitance must be charged faster. For a desired soft-start time, the soft-start capacitance, CSS, can be found from: I SS C SS + t SS VFB (6) 16 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 PROGRAMMING SHORT-CIRCUIT PROTECTION The TPS40077 uses a two-tier approach for short-circuit protection. The first tier is a pulse-by-pulse protection scheme. Short-circuit protection is implemented on the high-side MOSFET by sensing the voltage drop across the MOSFET when its gate is driven high. The MOSFET voltage is compared to the voltage dropped across a resistor (RILIM) connected from VVDD to the ILIM pin when driven by a constant-current sink. If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated. The MOSFET remains off until the next switching cycle is initiated. This is illustrated in Figure 24. ILIM ILIM Threshold (A) Overcurrent VIN - 2V SW T2 ILIM T1 VIN - 2V ILIM Threshold (B) SW T1 T3 UDG-03173 Figure 24. Switching and Current-Limit Waveforms and Timing Relationship In addition, just prior to the high-side MOSFET turning on, the ILIM pin is pulled down to approximately half of VVDD. The ILIM pin is allowed to return to its nominal value after one of two events occurs. If the SW node rises to within approximately 2 V of VVDD, the device allows ILIM to go back to its nominal value. This is illustrated in Figure 24(A). T1 is the delay time from the internal PWM signal being asserted and the rise of SW. This includes a driver delay of 50 ns, typical. T2 is the reaction time of the sensing circuit that allows ILIM to start to return to its nominal value, typically 20 ns. The second event that can cause ILIM to return to its nominal value is for an internal timeout to expire. This is illustrated in Figure 24(B) as T3. Here SW never rises to VVDD - 2 V, for whatever reason, and the internal timer times out, releasing the ILIM pin. Prior to ILIM starting back to its nominal value, overcurrent sensing is not enabled. In normal operation, this ensures that the SW node is at a higher voltage than ILIM when overcurrent sensing starts, avoiding false trips while allowing for a quicker blanking delay than would ordinarily be possible. Placing a capacitor across RILIM sets an exponential approach to the normal voltage at the ILIM pin. This exponential decay of the overcurrent threshold can be used to compensate for ringing on the SW node after its rising edge and to help compensate for slower-turnon FETs. Choosing the proper capacitance requires care. If the capacitance is too large, the voltage at ILIM does not approach the desired overcurrent level quickly enough, resulting in an apparent shift in overcurrent threshold as pulse duration changes. As a general rule, it is best to make the time constant of the R-C at the ILIM pin 0.2 times or less of the nominal pulse duration of the converter as shown in Equation 11. Also, the comparator that uses ILIM and SW to determine if an overcurrent condition exists has a clamp on its SW input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be as much as 2 V at -40C) below VVDD. When ILIM is more than 1.4 V below VVDD, the overcurrent circuit is effectively disabled. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 17 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com The second-tier protection incorporates a fault counter. The fault counter is incremented on each cycle with an overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7), a fault condition is declared by the controller. When this happens, the outputs are placed in a state defined in Table 2. Seven soft-start cycles are initiated (without activity on the HDRV and LDRV outputs) and the PWM is disabled during this period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM is re-enabled and the controller attempts to restart. If the fault has been removed, the output starts up normally. If the output is still present, the counter counts seven overcurrent pulses and re-enters the second-tier fault mode. Refer to Figure 25 for typical fault-protection waveforms. The minimum short-circuit limit setpoint (ISCP(min)) depends on tSTART, COUT, VOUT, ripple current in the inductor (IRIPPLE), and the load current at turnon (ILOAD). COUT VOUT I I SCP(min) u ) I LOAD ) RIPPLE t START 2 (7) The short-circuit limit programming resistor (RILIM) is calculated from: I SCP RDS(onMAX) ) VILIM (offset) R ILIM + W I ILIM (8) where * * * IILIM is the current into the ILIM pin (110 A, typical) VILIM(offset) is the offset voltage of the ILIM comparator (-50 mV, typical) ISCP is the short-circuit protection current To find the range of the overcurrent values, use the following equations: 1.09 I ILIM(max) R ILIM * 0.09 RVDD I R * 0.045 V ) 75 mV VDD I SCP(max) + (A) R DS(ON)min 1.09 I SCP(min) + I ILIM(min) R ILIM * 0.09 RVDD IR VDD * 0.045 V ) 30 mV R DS(ON)max (9) (A) (10) The TPS40077 provides short-circuit protection only. Therefore, it is recommended that the minimum short-circuit protection level be placed at least 20% above the maximum output current required from the converter. The maximum output of the converter should be the steady state maximum output plus any transient specification that may exist. The ILIM capacitor maximum value can be found from: V OUT 0.2 C ILIM(max) + (Farads) VIN RILIM f SW (11) Note that this is a recommended maximum value. If a smaller value can be used, it should be. For most applications, consider using half the maximum value above. 18 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 HDRV Clock tBLANKING VILIM VVIN - VSW SS 7 Current-Limit Trips (HDRV Cycle Terminated by Current-Limit Trip) 7 Soft-Start Cycles VDG-03174 Figure 25. Typical Fault Protection Waveforms LOOP COMPENSATION Voltage-mode, buck-type converters are typically compensated using Type III networks. Because the TPS40077 uses voltage feed-forward control, the gain of the voltage feed-forward circuit must be included in the PWM gain. The gain of the voltage feed-forward circuit, combined with the PWM circuit and power stage for the TPS40077 is: KPWM VUVLO(on) The remainder of the loop compensation is performed as in a normal buck converter. Note that the voltage feed-forward circuitry removes the input voltage term from the expression for PWM gain. PWM gain is strictly a function of the programmed startup voltage. SHUTDOWN AND SEQUENCING The TPS40077 can be shut down by pulling the SS pin below 250 mV. In this state, both of the output drivers are in the low-output state, turning off both of the power FETs. This places the output of the converter in a high-impedance state. When shutting down the converter, a crisp pulldown of the SS pin is preferred to a slow pulldown. A slow pulldown could allow the output to be pulled low, possibly sinking current from the load. As a general rule of thumb, the fall time of SS when shutting down the converter should be no more than 1/10th of the control loop crossover frequency. An example of a shutdown interface is shown in Figure 26. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 19 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com TPS40077 6 SS Shutdown S0204-01 Figure 26. TPS40077 Shutdown In a similar manner, power supplies based on the TPS40077 can be sequenced by connecting the PGD pin of the first supply to come up to the SS pin of the second supply as shown in Figure 27. TPS40077 6 SS PGD TPS40077 4 6 SS PGD 4 To System Power Good S0205-01 Figure 27. TPS40077 Sequencing BOOST AND LVBP BYPASS CAPACITANCE The BOOST capacitance provides a local, low-impedance flying source for the high-side driver. The BOOST capacitor should be a good-quality, high-frequency capacitor. A capacitor with a minimum value of 100-nF is suggested. The LVBP pin must provide energy for both the synchronous MOSFET and the high-side MOSFET (via the BOOST capacitor). The suggested value for this capacitor is 1-F ceramic, minimum. 20 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 INTERNAL REGULATORS The internal regulators are linear regulators that provide controlled voltages from which the drivers and the internal circuitry operate. The DBP pin is connected to a nominal 8-V regulator that provides power for the driver circuits. This regulator has two modes of operation. At VDD voltages below 8.5 V, the regulator is in a low-dropout mode of operation and tries to provide as little impedance as possible from VDD to DBP. Above 10 V at VDD, the regulator regulates DBP to 8 V. Between these two voltages, the regulator remains in the state it was in when VDD entered this region (see Figure 20). Small amounts of current can be drawn from this pin for other circuit functions, as long as power dissipation in the controller device remains at acceptable levels and junction temperature does not exceed 125C. The LVBP pin is connected to another internal regulator that provides 4.2 V (nom) for the operation of low-voltage circuitry in the controller. This pin can be used for other circuit purposes, but extreme care must be taken to ensure that no extra noise is coupled onto this pin; otherwise, controller performance suffers. Current draw is not to exceed 1 mA. See Figure 21 for typical output voltage at this pin. TPS40077 POWER DISSIPATION The power dissipation in the TPS40077 is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power (neglecting external gate resistance) can be calculated from: PD = Qg x VDR x fSW (Watts/driver) where VDR is the driver output voltage The total power dissipation in the TPS40077, assuming the same MOSFET is selected for both the high-side and synchronous rectifier, is described in Equation 14 or Equation 15. 2 PD PT + ) IQ V IN (Watts) V DR (14) or P T + 2 Qg f SW ) I Q V IN (Watts) (15) where IQ is the quiescent operating current (neglecting drivers) The maximum power capability of the TPS40077 PowerPAD package is dependent on the layout as well as air flow. The thermal impedance from junction to air, assuming 2-oz. copper trace and thermal pad with solder and no air flow, is 37C/W. See the application report titled PowerPAD Thermally Enhanced Package (SLMA002) for detailed information on PowerPAD package mounting and usage. The maximum allowable package power dissipation is related to ambient temperature by Equation 16. For JA, see the Package Dissipation Ratings table. T * TA PT + J (Watts) q JA (16) Substituting Equation 16 into Equation 15 and solving for fSW yields the maximum operating frequency for the TPS40077. The result is described in Equation 17. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 21 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com T J*T A q JA V DD f SW + 2 * IQ (Hz) Q g (17) BOOST DIODE The TPS40077 series has internal diodes to charge the boost capacitor connected from SW to BOOST. The drop across these diodes is rather large, 1.4 V nominal, at room temperature. If this drop is too large for a particular application, an external diode may be connected from DBP (anode) to BOOST (cathode). This provides significantly improved gate drive for the high-side FET, especially at lower input voltages. GROUNDING AND BOARD LAYOUT The TPS40077 provides separate signal ground (SGND) and power ground (PGND) pins. Care should be given to proper separation of the circuit grounds. Each ground should consist of a plane to minimize its impedance, if possible. The high-power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (DBP), and the input capacitor should be connected to PGND plane. Sensitive nodes such as the FB resistor divider and RT should be connected to the SGND plane. The SGND plane should only make a single-point connection to the PGND plane. It is suggested that the SGND pin be tied to the copper area for the thermal pad underneath the chip. Tie the PGND to the thermal-pad copper area as well, and make the connection to the power circuit ground from the PGND pin. Reference the output voltage divider to the SGND pin. Component placement should ensure that bypass capacitors (LVPB and DBP) are located as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located near high-dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow careful layout practices results in suboptimal operation. More detailed information can be found in the TPS40077EVM User's Guide (SLVU192). SYNCHRONOUS RECTIFIER CONTROL Table 2 describes the state of the rectifier MOSFET control under various operating conditions. Table 2. Synchronous Rectifier MOSFET States SYNCHRONOUS RECTIFIER OPERATION DURING SOFT-START NORMAL Off until first high-side pulse is Turns off at the start of a new detected, then on when high-side cycle. Turns on when the MOSFET is off high-side MOSFET is turned off FAULT (FAULT RECOVERY IS SAME AS SOFT-START) OFF OVERVOLTAGE Turns OFF only at start of next cycle only if the pulse width modulator duty cycle is greater than zero. Otherwise, stays ON For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50 nC. 22 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 APPLICATION 1: BUCK REGULATOR 8-V TO 16-V INPUT, 1.8-V OUTPUT AT 10 A Table 3. Specifications PARAMETER NOTES AND CONDITIONS MIN NOM MAX UNITS INPUT CHARACTERSTICS VIN Input voltage IIN Input current VIN = NOM, IOUT = MAX 8 No-load input current VIN = NOM, IOUT = 0 A VIN_UVLO Input UVLO IOUT = MIN to MAX VIN_ONV Input ONV IOUT = MIN to MAX 12 16 1.8 2 V 62.6 3.6 mA 5.4 6 6.6 V 6.3 7 7.7 V 1.75 1.8 1.85 V A OUTPUT CHARACTERSTICS VOUT Output voltage Line regulation VIN = NOM, IOUT = NOM (1) VIN = MIN to MAX, IOUT = NOM 0.5% Load regulation (1) VIN = NOM, IOUT = MIN to MAX 0.5% VOUT_ripple Output voltage ripple VIN = NOM, IOUT = MAX IOUT Output current VIN = MIN to MAX IOCP Output overcurrent inception point VIN = NOM, VOUT = VOUT - 5% VOVP Output OVP IOUT = MIN to MAX 100 mVpp 0 5 10 A 12.25 19.4 34 A NA NA NA Transient response I Load step IOUT_Max to 0.2 x IOUT _Max Load slew rate Overshoot Settling time 8 A 10 A/s 200 mV 1 ms SYSTEM CHARACTERSTICS fSW Switching frequency pk Peak efficiency VIN = NOM, IOUT = MIN to MAX 240 90% Full-load efficiency VIN = NOM, IOUT = MAX 90% Top Operating temperature range VIN = MIN to MAX, IOUT = MIN to MAX -40 300 25 360 kHz 85 C MECHANICAL CHARACTERSTICS L W h (1) 2 Width Inches 5.08 3 Length Component height cm Inches 7.62 cm 0.41 Inch 1.04 cm Voltage accuracy is dependent on resistor tolerance and reference accuracy. Line and load regulation are calculated with respect to the actual set point voltage. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 23 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com Schematic and Performance Curves VIN CIN + ELCO RKFF RT CDELAY RLIM U1 TPS40077PWP CBP5 1 KFF QSW 16 ILIM 2 15 RT VDD 3 BP5 BOOST 4 PGD HDRV 5 SGND SW 6 SS DBP 7 FB LDRV 8 PGND COMP PWP RPGD CSS R10 330 kW LOUT CBOOST 14 13 VOUT CVDD 12 C_IN MLCC 11 R4 0W 10 9 + QSR COUT ELCO C_OUT MLCC C13 2.2nF CDBP RPZ2 VOUT = 1.8 V IOUT up to 10 A CZ2 CP2 0V RZ1 RSET RP1 CPZ1 C11 0.1 mF S0239-01 Figure 28. Schematic Diagram 100 90 80 8V - Efficiency - % 70 12 V 16 V 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 IOUT - Load Current - A 8 9 10 G026 Figure 29. Module Efficiency, 8 V, 12 V, and 16 V In, 0 to 10 A Out 24 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 200 50 45 180 Phase 160 35 140 30 120 25 100 20 80 15 60 Gain 10 40 5 20 0 100 1k Phase - Gain - dB 40 10k 100k 0 1M f - Frequency - Hz G027 Figure 30. Bode Plot Showing 57 Phase Margin at Crossover Frequency of 54 kHz Component Selection Power Train Components Output Inductor, LOUT The output inductor is one of the most important components to select. It stores the energy necessary to keep the output regulated when the switch FET is turned off. The value of the output inductor dictates the peak and RMS currents in the converter. These currents are important when selecting other components. Equation (1) can be used to calculate a value for LOUT for this module which operates at a switching frequency (f) of 300 kHz. V IN(max) * V OUT VOUT LOUT + V IN(max) f s I RIPPLE (18) IRIPPLE is the allowable ripple in the inductor. Select IRIPPLE to be between 20% and 30% of maximum IOUT. For this design, IRIPPLE of 2.5 A was selected. Calculated LOUT is 2.13 H. A standard inductor with value of 2.5 H was chosen. This will reduce IRIPPLE by about 17% to 2.07 A. This IRIPPLE value can be used calculate the rms and peak current flowing in LOUT. Note that this peak current is also seen by the switching FET and synchronous rectifier. I LOUT_RMS + I OUT 2 2 I ) RIPPLE + 10.02 A 12 (19) The power loss from the selected inductor DCR is 357 mW. The ac core loss for this Coilcraft inductor may be found from the Coilcraft Web site, where there is a loss calculator. The loss is 179 mW. I I PK + I OUT ) RIPPLE + 11.03 A 2 (20) The inductor is selected with a saturation current higher than this current plus the current that is developed charging the output capacitance during the soft-start interval. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 25 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com Output Capacitor, COUT, ELCO and MLCC Several parameters must be considered when selecting the output capacitor. The capacitance value should be selected based on the output overshoot, VOVER, and undershoot, VUNDER, during a transient load, ISTEP, on the converter. The equivalent series resistance (ESR) is chosen to allow the converter to meet the output ripple specification, VRIPPLE. The voltage rating must be greater than the maximum output voltage. Another parameter to consider is equivalent series inductance, which is important in fast-transient load situations. Also, size and technology can be factors when choosing the output capacitor. In this design, a large-capacitance electrolytic type capacitor, COUT ELCO, is used to meet the overshoot and undershoot specifications. Its ESR is chosen to meet the output ripple specification. Smaller multiple-layer ceramic capacitors, COUT MLCC, are used to filter high-frequency noise. The minimum required capacitance and maximum ESR can be calculated using the following equations. 2 COUT + 2 LOUT I STEP VUNDER Dmax (VIN * VOUT) (21) 2 COUT + LOUT I STEP 2 VOVER VOUT (22) V ESR + RIPPLE I RIPPLE (23) From Equation 21, Equation 22, and Equation 23, the capacitance for COUT should be greater than 444 F, and its ESR should be less than 12 m. The 470-F/6.3-V capacitor from Panasonic's FC series was chosen. Its ESR is 160 m. MLCCs of 47 F and 22 F/16 V are also added in parallel to achieve the required ESR and to reduce high-frequency noise. Input Capacitor, CIN ELCO and MLCC The input capacitor is selected to handle the ripple current of the buck stage. Also, a relatively large capacitance is used to keep the ripple voltage on the supply line low. This is especially important where the supply line has high impedance. It is recommended however, that the supply-line impedance be kept as low as possible. The input-capacitor ripple current can be calculated using Equation 24. I CAP(RMS) + IOUT * IIN(AVG) 2 I ) RIPPLE 12 2 D ) I IN(AVG) 2 (1 * D) (24) IIN(AVG) is the average input current. This is calculated simply by multiplying the output dc current by the duty cycle. The ripple current in the input capacitor is 3.3 A. An 1812 MLCC using X5R material has a typical dissipation factor of 5%. For a 22-F capacitor at 300 kHz, the ESR is approximately 4 m. Two capacitors are used in parallel, so the power dissipation in each capacitor is less than 11 mW. A 470-F/16-V electrolytic is added to maintain the voltage on the input rail. Switching MOSFET, QSW The following key parameters must be met by the selected MOSFET. * Drain source voltage, Vds, must be able to withstand the input voltage plus spikes that may be on the switching node. For this design a Vds rating of 30 volts is recommended. * Drain current, ID, at 25C, must be greater than that calculated using Equation 25. I QSW(RMS) + * * 26 V OUT VIN(MIN) I I OUT(MAX) ) RIPPLE 12 2 2 (25) With the parameters specified, the calculation of IQSW(RMS) should be greater than 5 A. Gate source voltage, Vgs, must be able to withstand the gate voltage from the control IC. For the TPS40077, Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 this is 11 V. Once the above boundary parameters are defined, the next step in selecting the switching MOSFET is to select the key performance parameters. Efficiency is the performance characteristic which drives the other selection criteria. Target efficiency for this design is 90%. Based on 1.8-V output and 10 A, this equates to a power loss in the converter of 1.8 W. Based on this figure, a target of 0.6 W dissipated in the switching FET was chosen. The following equations can be used to calculate the power loss, PQSW, in the switching MOSFET. P QSW + PCON ) PSW ) PGATE P CON + RDS(on) P SW + VIN fS P GATE + Q g(TOT) 2 I QSW(RMS) + R DS(on) V OUT VIN 2 I out ) I RIPPLE 12 (27) I ) IRIPPLE Q ) Q gs1 OUT gd 2 Q ) Q OSS(SW) OSS(SR) ) 12 Ig Vg (26) 2 f SW (28) (29) where PCON = conduction losses PSW = switching losses PGATE = gate-drive losses Qgd = drain-source charge or Miller charge Qgs1 = gate-source post-threshold charge Ig = gate-drive current QOSS(SW) = switching MOSFET output charge QOSS(SR) = synchronous MOSFET output charge Qg(TOT) = total gate charge from zero volts to the gate voltage Vg = gate voltage If the total estimated loss is split evenly between conduction and switching losses, Equation 27 and Equation 28 yield preliminary values for RDS(on) and (Qgs1 + Qgd). Note output losses due to QOSS and gate losses have been ignored here. Once a MOSFET is selected, these parameters can be added. The switching MOSFET for this design should have an RDS(on) of less than 8 m. The sum of Qgd and Qgs should be approximately 4 nC. It may not always be possible to get a MOSFET which meets both these criteria, so a compromise may be necessary. Also, by selecting different MOSFETs close to these criteria and calculating power loss, the final selection can be made. It was found that the Si7860DP MOSFET from Vishay semiconductor gave reasonable results. This device has an RDS(on) of 8 m and a (Qgs1 + Qgd) of 5 nC. The estimated conduction losses are 0.115 W and the switching losses are 0.276 W. This gives a total estimated power loss of 0.391 W versus 0.6 W for our initial boundary condition. Note this does not include gate losses of approximately 71 mW and output losses of 20 mW. Rectifier MOSFET, QSR Similar criteria to the foregoing can be used for the rectifier MOSFET. There is one significant difference: due to the body diode conducting, the rectifier MOSFET switches with zero voltage across its drain and source, so effectively with zero switching losses. However, there are some losses in the body diode. These are minimized by reducing the delay time between the transition from the switching MOSFET turnoff to rectifier MOSFET turnon and vice-versa. The TPS40077 incorporates TI's proprietary Predictive Gate Drive circuitry (PGD), which helps reduce these delays to around 10 ns. The equations used to calculate the losses in the rectifier MOSFET are: Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 27 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com P QSR + PCON ) PBD ) PGATE P CON + RDS(on) P BD + Vf 1* I OUT (30) V OUT * t 1 ) t 2 VIN t1 ) t 2 fS Vg fS P GATE + Q g(TOTAL) fS 2 I out ) I RIPPLE 12 2 (31) (32) (33) where PBD = body diode losses t1 = body diode conduction prior to turnon of channel = 12 ns for PGD t2 = body diode conduction after turnoff of channel = 12 ns for PGD Vf = body diode forward voltage Estimating the body diode losses based on a forward voltage of 1 V gives 0.072 W. The gate losses are unknown at this time, so assume 0.1-W gate losses. This leaves 0.428 W for conduction losses. Using this figure, a target RDS(on) of 5 m was calculated. The Si7336ADP from Vishay was chosen. Using the parameters from its data sheet, the actual expected power losses are calculated. Conduction loss is 0.317 W, body diode loss is 0.072 W, and the gate loss is 0.136W. This totals 0.525 W associated with the rectifier MOSFET. Two other criteria should be verified before finalizing on the rectifier MOSFET. One is the requirement to ensure that predictive gate drive functions correctly. The turnoff delay of the Si7336ADP is 97 ns. The minimum turnoff delay of the Si7860DP is 25 ns. Together these devices meet the 130-ns requirement. Secondly, the ratio between Cgs and Cgd should be greater than 1. The Si7336ADP easily meets this criterion. This helps reduce the risk of dv/dt-induced turnon of the rectifier MOSFET. If this is likely to be a problem, a small resistor may be added in series with the boost capacitor, CBOOST. Component Selection for TPS40077 Timing Resistor, RT The timing resistor is calculated using the following equation. 1 RT + * 23 f S 17.82 10 *6 (34) This gives a resistor value of 165 k. The nominal frequency using this resistor is 300 kHz. Feed-Forward and UVLO Resistor, RKFF A resistor connected to the KFF pin of the IC feeds into the ramp generator. This resistor provides current into the ramp generator proportional to the input voltage. The ramp is then adjusted to compensate for different input voltages. This provides the voltage feed-forward feature of the TPS40077. The same resistor also sets the undervoltage lockout point. The input start voltage should be used to calculate a value for RKFF. For this module, the minimum input voltage is 8 V; however, due to tolerances in the IC, a start voltage of 10% less than the minimum input voltage is selected. The start voltage for RKFF calculation is 7.2 V. Using Equation 35, RKFF can be selected. R KFF + 0.131 * 4.87 10*5 RT RT V UVLO(on) * 1.61 10*3 2 V UVLO(on) ) 1.886 V UVLO * 1.363 * 0.02 RT 2 (35) where RKFF and RT are in k. This equation gives an RKFF value of 156 k. The closest lower standard value of 154 k should be selected. This gives a minimum start voltage of 7.1 V. 28 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 Soft-Start Capacitor, CSS It is good practice to limit the rise time of the output voltage. This helps prevent output overshoot and possible damage to the load. The selection of the soft-start time is arbitrary. It must meet one condition: it should be greater than the time constant of the output filter, LOUT and COUT. This time is given by t w 2p LOUT COUT START (36) The soft-start time must be greater than 0.23 ms. A time of 0.75 ms was chosen. This time also helps limit the initial input current during start-up so that the peak current plus the capacitor start-up current is less than the minimum short-circuit current. The value of CSS can be calculated using Equation 37. I C SS + SS t START VFB (37) A standard 15-nF MLCC capacitor was chosen. The calculated start time using this capacitor is 0.875 ms. Short-Circuit Protection, RILIM and CILIM Short-circuit protection is programmed using the RILIM resistor. Selection of this resistor depends on the RDS(on) of the switching MOSFET selected and the required short-circuit current trip point, ISCP. The minimum ISCP is limited by the inductor peak current, the output voltage, the output capacitor, and the soft-start time. Their relationship is given by Equation 38. A short-circuit current trip point greater than that calculated by this equation should be used. COUT V OUT I SCP w ) I PK t START (38) The minimum short-circuit current trip point for this design is 12.25 A. This value is used in Equation 39 to calculate the minimum RILIM value. I SCP RDS(on)MAX ) VILIM(Max) R ILIM + I LIM(Min) (39) RILIM is calculated to be 1.17 k, and a 1.2-k resistor is used to verify that the short-circuit current requirements are met. The minimum and maximum short-circuit current can be calculated using Equation 40 and Equation 41. I ILIM(MIN) RILIM(MIN) * VILIM(MAX) I SCP(MIN) + R DS(on)MAX (40) I SCP(MAX) + I ILIM(MAX) RILIM(MAX) * VILIM(MIN) R DS(on)MIN (41) where: VILIM(MAX) and VILIM(MIN) are maximum and minimum voltages across the high side FET when it is turned on, taking into account temperature variations. The minimum ISCP is 12.25 A, and the maximum is 34 A. It is also recommended to add a small capacitor, CILIM, across RILIM. The value of this capacitor should be about half the value calculated in Equation 42. VOUT 0.2 C ILIM(Max) + VIN RILIM f S (42) This equation yields a maximum CILIM as 55 pF. A smaller value of 27 pF is chosen is chosen. Boost Voltage, CBOOST and DBOOST (Optional) To be able to drive an N-channel MOSFET in the switch location of a buck converter, a capacitor charge pump or boost circuit is required. The TPS40077 contains the elements for this boost circuit. The designer must only add a capacitor, CBOOST, from the switch node of the buck power stage to the BOOST pin of the IC. Selection of this capacitor is based on the total gate charge of the switching MOSFET and the allowable ripple on the boost voltage, VBOOST. A ripple of 0.2 V is assumed for this design. Using these two parameters and Equation 43, the minimum value for CBOOST can be calculated. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 29 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com CBOOST u Q g(TOTAL) DV BOOST (43) The total gate charge of the switching MOSFET is 23 nC. A minimum CBOOST of 0.092 F is required. A 0.1 F capacitor was chosen. This capacitor must be able to withstand the maximum input voltage plus the maximum voltage on DBP. This is 13.2 V plus 9.0 V, which is 22.2 V. A 50-V capacitor is used. To reduce losses in the TPS40077 and to increase the available gate voltage for the switching MOSFET, an external diode can be added between the DBP pin and the BOOST pin of the IC. A small-signal Schottky diode should be used here, such as the BAT54. Closing the Feedback Loop, RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2, and CPZ1 A graphical method is used to select the compensation components. This is a standard feed-forward buck converter. Its PWM gain is given by Equation 44. V K PWM ^ UVLO 1V (44) The ramp voltage is 1 V at the UVLO voltage. Because of the feed-forward compensation, the programmed UVLO voltage is the voltage that sets the PWM gain. The gain of the output LC filter is given by Equation 45. 1 ) s ESR COUT K LC + LOUT ) s 2 LOUT COUT 1)s ROUT (45) The PWM and LC gain is G c(s) + KPWM VUVLO 1V KLC 1)s 1 ) s ESR LOUT ) s 2 ROUT COUT LOUT COUT (46) To plot this on a Bode plot, the dc gain must be expressed in dB. The dc gain is equal to KPWM. To express this in dB, take its logarithm and multiply by 20. For this converter, the dc gain is DCGAIN + 20 V UVLO + 20 VRAMP log log(7) + 16.9 dB (47) Also, the pole and zero frequencies should be calculated. A double pole is associated with the LC and a zero is associated with the ESR of the output capacitor. The frequencies where these occur can be calculated using equations, 1 f LC_Pole + + 4.3 kHz 2p LOUT COUT (48) 1 f ESR_Zero + + 2.1 kHz 2p ESR COUT (49) These are shown in the Bode plot of Figure 31. 30 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 30 20 Double Pole 10 ESR Zero Gain - dB 0 -10 ESR = 0.16 Slope = -20 dB/Decade -20 -30 -40 -50 -60 0.1 1 10 100 1k f - Frequency - kHz G028 Figure 31. PWM and LC Filter Gain The next step is to establish the required compensation gain to achieve the desired overall system response. The target response is to have the crossover frequency between 1/9 and 1/5 times the switching frequency, in order to have a phase margin greater than 45 and a gain margin greater than 6 dB. A type-III compensation network, shown in Figure 32, was used for this design. This network gives the best overall flexibility for compensating the converter. RP1 CPZ1 TPS40077 VOUT 6 SS 7 FB 8 COMP RZ1 CZ2 CP2 RPZ2 RSET S0240-01 Figure 32. Type-III Compensation With the TPS40077 A typical Bode plot for this type of compensation network is shown in Figure 33. Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 31 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com 40 30 High-Frequency Gain Gain - dB 20 10 0 -10 fZ1 fZ2 fP1 fP2 -20 0.1 1 10 100 1k f - Frequency - kHz G029 Figure 33. Type-III Compensation Typical Bode Plot The high-frequency gain and the break (pole and zero) frequencies are calculated using the following equations. RZ1 ) RSET VOUT + VREF RSET (50) R Z1 ) R P1 R Z1 R P1 GAIN + R PZ2 f P1 + f P2 + f Z1 + f Z2 + 2p 1 R P1 2p C P2 ) CZ2 R PZ2 C P2 (51) C PZ1 (52) C Z2 [ 1 R PZ2 2p CP2 (53) 1 2p R Z1 C PZ1 2p 1 R PZ2 ) R P1 (54) C Z2 [ 1 2p R PZ2 CZ2 (55) Looking at the PWM and LC bode plot, there are a few things which must be done to achieve stability. 1. Place two zeros close to the double pole, e.g., fZ1 = fZ2 = 4.3 kHz 2. Place both poles well above the crossover frequency. The crossover frequency was selected as one sixth the switching frequency, fco1 = 50 kHz, fP1 = 66 kHz 3. Place the second pole at three times fco1. This ensures that the overall system gain falls off quickly to give good gain margin, fp2 = 150 kHz 4. The high-frequency gain should be sufficient to ensure 0 dB at the required crossover frequency, GAIN = -1 x gain of PWM and LC at the crossover frequency, GAIN = 16.9 dB Using these values and Equation 50 through Equation 55, the Rs and Cs around the compensation network can be calculated. 1. Set RZ1 = 51 k 2. Calculate RSET using Equation 50, RSET = 32.4 k 3. Using Equation 54 and fz1 = 4.3 kHz, CPZ1 can be calculated to be 726 pF, CPZ1= 680 pF 4. fP1 and Equation 52 yields RP1 to be a standard value of 3.3 k. 32 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 5. The required gain of 16.9 dB and Equation 51 sets the value for RPZ2. RPZ2 = 21.5 k. 6. CZ2 is calculated using Equation 55 and the desired frequency for the second zero, CZ2 = 1.7 nF, or using standard values, 1.8 nF. 7. Finally, CP2 is calculated using the second pole frequency and Equation 53; CP2 = 47 pF. Using these values, the simulated results are 57 of phase margin at 54 kHz. Table 4. Bill of Materials RefDes Count Value Description Size Part Number Mfr C1 1 470 F Capacitor, aluminum, 470-F, 25-V, 20% 0.457 x 0.406 EEVFK1E471P Panasonic C2, C10 2 0.1 F Capacitor, ceramic, 25-V, X7R, 20% 0603 Std Vishay C3 1 15 nF Capacitor, ceramic, 25-V, X7R 20% 0603 Std Vishay C4 1 47 pF Capacitor, ceramic, 25-V, X7R, 20% 0603 Std Vishay C5 1 1.8 nF Capacitor, ceramic, 25-V, X7R 20% 0603 Std Vishay C6 1 680 pF Capacitor, ceramic, 25-V, X7R 20% 0603 Std Vishay C7 1 51 pF Capacitor, ceramic, 25-V, COG 20% 0603 Std Vishay C8, C11 2 0.1 F Capacitor, ceramic, 25-V, X7R, 20% 0603 Std Vishay C9 1 1 F Capacitor, ceramic, 25-V, X7R, 20% 0805 Std Vishay C12, C14, C15 3 22 F Capacitor, ceramic, 22-F, 16-V, X5R, 20% 1812 C4532X5R1C226MT TDK C13 1 2.2 nF Capacitor, ceramic, 25-V, X7R, 20% 0603 Std Vishay C16 1 470 F Capacitor, aluminum, SM, 6.3-V, 300-m (FC series) 8 mm x 10 mm Std Panasonic C17 1 47 F Capacitor, ceramic, 47-uF, 6.3-V, X5R, 20% 1812 C4532X5R0J476MT TDK D1 1 BAT54 Diode, Schottky, 200-mA, 30-V SOT23 BAT54 Vishay J1, J2 2 ED1609-ND Terminal block, 2-pin, 15-A, 5,1-mm 0.40 x 0.35 ED1609 OST J3 1 PTC36SAAN Header, 2-pin, 100-mil spacing, (36-pin strip) 0.100 x 2 PTC36SAAN Sullins L1 1 2.5 H Inductor, SMT, 2.5 H, 16.5-A, 3.4- m 0.515 x 0.516 MLC1550-252ML Coilcraft Q1 1 Si7860DP MOSFET, N-channel, 30-V, 18-A, 8.0-m PWRPAK S0-8 Si7860DP Vishay Q2 1 Si7336ADP MOSFET, N-channel, 30-V, 18-A, 40-m PWRPAK S0-8 Si7886ADP Vishay Q3 1 FDV301N MOSFET, N-channel, 25-V, 220-mA, 5- SOT23 FDV301N Fairchild R1 1 10 k Resistor, chip, 1/16-W, 20% 0603 Std Std R2, R6 2 165 k Resistor, Chip, 1/16-W, 20% 0603 Std Std R3 1 32.4 k Resistor, chip, 1/16-W, 20% 0603 Std Std R4, R11 2 0 Resistor, chip, 1/16-W, 20% 0603 Std Std R5 1 21.5 k Resistor, chip, 1/16-W, 20% 0603 Std Std R7 1 51 k Resistor, chip, 1/16-W, 20% 0603 Std Std R8 1 3.3 k Resistor, chip, 1/16-W, 20% 0603 Std Std R9 1 1.8 k Resistor, chip, 1/16-W, 20% 0603 Std Std R10 1 330 k Resistor, chip, 1/16-W, 20% 0603 Std Std R12 1 51 Resistor, chip, 1/16-W, 20% 0603 Std Std R13 1 1 k Resistor, chip, 1/16-W, 20% 0603 Std Std U1 1 TPS40077PWP IC, Texas Instruments PWP16 TPS40077PWP TI Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 33 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com EXAMPLE APPLICATIONS + VDD 12 V - R6 165 kW R9 2 kW TPS40077PWP R2 165 kW 1 KFF ILIM 16 2 RT VDD 15 3 LVBP BOOST 14 4 PGD HDRV 13 5 SGND SW 12 6 SS DBP 11 C3 22 nF C5 5.6 nF C12 22 mF C10 0.1 mF C2 0.1 mF R5 10 kW C7 10 pF FB 8 COMP C4 470 pF LDRV 10 PGND 9 C8 0.1 mF L1 Pulse Q1 PG0077.202 Si7840BDP 2 mH D1 BAT54 C9 1 mF 7 C14 22 mF + Q2 Si7856ADP + C13 4.7 nF C15 47 mF + C16 470 mF C17 470 mF C18 0.1 mF VOUT 1.8 V 10 A - PWP R7 8.66 kW R3 5.49 kW C6 4.7 nF R8 226 W S0209-01 Figure 34. 300 kHz, 12 V to 1.8 V 34 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077 www.ti.com ..................................................................................................................................................... SLUS714D - JANUARY 2007 - REVISED APRIL 2009 + VDD 12 V - R6 165 kW R9 2 kW TPS40077PWP R2 165 kW 1 KFF ILIM 16 2 RT VDD 15 3 LVBP BOOST 14 4 PGD HDRV 13 5 SGND SW 12 6 SS DBP 11 C3 22 nF C5 5.6 nF C12 22 mF C10 0.1 mF C2 0.1 mF R5 10 kW C7 10 pF FB 8 COMP C4 470 pF LDRV 10 PGND 9 C8 0.1 mF L1 Pulse Q1 PG0077.202 Si7840BDP 2 mH D1 BAT54 C9 1 mF 7 C14 22 mF + Q2 Si7856ADP + C13 4.7 nF C15 47 mF + C16 470 mF C17 470 mF C18 0.1 mF VOUT 1.8 V 10 A - PWP R7 8.66 kW R3 5.49 kW C6 4.7 nF R8 226 W S0210-01 See the Boost Diode section. Figure 35. 300 kHz, 12 V to 1.8 V With Improved High-Side Gate Drive Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 35 TPS40077 SLUS714D - JANUARY 2007 - REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com + VDD 5V - R6 47 kW R2 90.1 kW 1 KFF ILIM 16 2 RT VDD 15 C12 22 mF C10 0.1 mF C2 0.1 mF C3 22 nF C7 10 pF R9 2 kW TPS40077PWP 3 LVBP BOOST 14 4 PGD HDRV 13 5 SGND SW 12 6 SS DBP 11 R5 10 kW C5 5.6 nF 7 FB 8 COMP C4 470 pF LDRV 10 PGND 9 C8 0.1 mF Q1 Si7860DP L1 Pulse PG0077.202 2 mH D1 BAT54 C9 1 mF R4 330 kW C14 22 mF + Q2 Si7860DP + C13 4.7 nF C15 47 mF + C16 470 mF C17 470 mF C18 0.1 mF VOUT 1.2 V 10 A - PWP R7 8.66 kW R3 12.1 kW C6 4.7 nF R8 226 W Note: Resistor across soft start capacitor. S0211-01 See the Boost Diode section. Figure 36. 500 kHz, 5 V to 1.2 V With Improved High-Side Gate Drive REFERENCES Related Parts The following parts are similar to the TPS40077 and may be of interest: * TPS40190 Low Pin Count Synchronous Buck Controller (SLUS658) * TPS40100 Midrange Input Synchronous Buck Controller With Advanced Sequencing and Output Margining (SLUS601) * TPS40075 Midrange Input Synchronous Buck Controller With Voltage Feed-Forward (SLUS676) * TPS40057 Wide-Input Synchronous Buck Controller (SLUS593) 36 Submit Documentation Feedback Copyright (c) 2007-2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS40077PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40077PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40077PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40077PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS40077PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 16 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40077PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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