1
FEATURES CONTENTS
DESCRIPTION
APPLICATIONS
SIMPLIFIED APPLICATION DIAGRAM
5
13
12
16
15
1
2
3
KFF
RT
LVPB
SGND
VDD
HDRV
SW
DBP
4 PGD
11
ILIM
TPS40077PWP
6 SS
7 FB
8 COMP
14BOOST
LDRV 10
PGND 9
VOUT
Powergood
VDDVDD
VOUT
UDG-09041
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
HIGH-EFFICIENCY, MIDRANGE-INPUT, SYNCHRONOUSBUCK CONTROLLER WITH VOLTAGE FEED-FORWARD
23
•Operation Over 4.5-V to 28-V Input Range
Device Ratings ........................ 2•Programmable, Fixed-Frequency, up to 1-MHz,Voltage-Mode Controller Electrical Characteristics ................. 4•Predictive Gate Drive™ Anti-Cross-Conduction
Terminal Information .................... 11Circuitry
Application Information .................. 14•< 1% Internal 700-mV Reference
Example Applications ................... 23•Internal Gate Drive Outputs for High-Side and
References ........................... 36Synchronous N-Channel MOSFETs•16-Pin PowerPAD™ Package•Thermal Shutdown Protection
The TPS40077 is a midvoltage, wide-input (4.5-V to•Pre-Bias Compatible
28-V), synchronous, step-down controller, offering•Power-Stage Shutdown Capability
design flexibility for a variety of user-programmable•Programmable High-Side Sense Short-Circuit
functions, including soft start, UVLO, operatingProtection
frequency, voltage feed-forward, and high-side,FET-sensed, short-circuit protection.
•Power Modules•Networking/Telecom
•PCI Express
•Industrial
•Servers
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Predictive Gate Drive, PowerPAD are trademarks of Texas Instruments.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION (CONTINUED)
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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The TPS40077 drives external N-channel MOSFETs using second-generation, predictive-gate drive to minimizeconduction in the body diode of the low-side FET and maximize efficiency. Pre-biased outputs are supported bynot allowing the low-side FET to turn on until the voltage commanded by the closed-loop soft start is greater thanthe pre-bias voltage. Voltage feed-forward provides good response to input transients and provides a constantPWM gain over a wide input-voltage operating range to ease compensation requirements. Programmableshort-circuit protection provides fault-current limiting and hiccup recovery to minimize power dissipation with ashorted output. The 16-pin PowerPAD package gives good thermal performance and a compact footprint.
ORDERING INFORMATION
PACKAGE ORDERABLE PART NUMBER
Plastic HTSSOP (PWP) Tube TPS40077PWPPlastic HTSSOP (PWP) Tape and reel TPS40077PWPR
over operating free-air temperature range unless otherwise noted
(1)
TPS40077 UNIT
VDD, ILIM 30COMP, FB, KFF, PGD, LVBP – 0.3 to 6V
VDD
Input voltage range VSW – 0.3 to 40SW, transient < 50 ns – 2.5COMP, KFF, RT, SS – 0.3 to 6VBOOST 50V
OUT
Output voltage range VDBP 10.5LVBP 6Output current source LDRV, HDRV 1.5I
OUT
LDRV, HDRV 2 AOutput current sink
KFF 10RT 1Output current mALVBP 1.5T
J
Operating junction temperature range – 40 to 125T
stg
Storage temperature – 55 to 150 ° CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260
(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN NOM MAX UNIT
V
DD
Input voltage 4.5 28 VT
A
Operating free-air temperature – 40 85 ° C
UNIT
Human body model (HBM) 2000 VCharged device model (CDM) 1500 V
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PACKAGE DISSIPATION RATINGS
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
Thermal Impedance, T
A
= 25 ° C Power Rating T
A
= 85 ° C Power RatingJunction-to-Ambient
(1)
Natural convection 37 ° C/W 2.7 W 1.08 W150 LFM airflow 30 ° C/W 3.33 W 1.33 W250 LFM airflow 28 ° C/W 3.57 W 1.42 W500 LFM airflow 26 ° C/W 3.84 W 1.52 W
(1) For more information on the board and the methods used to determine ratings, see the PowerPAD Thermally Enhanced Packageapplication report (SLMA002 ).
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ELECTRICAL CHARACTERISTICS
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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T
A
= – 40 ° C to 85 ° C, V
IN
= 12 V
dc
, R
T
= 90.9 k Ω, I
KFF
= 300 µA, f
SW
= 500 kHz, all parameters at zero power dissipation(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
V
VDD
Input voltage range, VIN 4.5 28 V
OPERATING CURRENT
I
VDD
Quiescent current Output drivers not switching 2.5 3.5 mA
LVBP
V
LVBP
Output voltage T
A
= T
J
= 25 ° C 3.9 4.2 4.5 V
OSCILLATOR/RAMP GENERATOR
f
OSC
Accuracy 450 500 550 kHzV
RAMP
PWM ramp voltage
(1)
V
PEAK
– V
VAL
2 VV
RT
RT voltage 2.23 2.4 2.58 Vt
ON
Minimum output pulse time
(1)
C
HDRV
= 0 nF 150 nsV
FB
= 0 V, 100 kHz ≤f
SW
≤500 kHz 84% 93%Maximum duty cycle
V
FB
= 0 V, f
SW
= 1 MHz 76% 93%V
KFF
Feed-forward voltage 0.35 0.4 0.45 VI
KFF
Feed-forward current operating range
(1)
20 1100 µA
SOFT START
I
SS
Charge current 7 12 17 µAt
DSCH
Discharge time C
SS
= 3.9 nF 25 75 µsC
SS
= 3.9 nF, V
SS
rising from 0.7 V tot
SS
Soft-start time 210 290 500 µs1.6 VTurnon threshold 310 365 420V
SSSD
Shutdown threshold 225 275 325 mVV
SSSDH
Shutdown threshold hysteresis 35 150
DBP
V
DD
> 10 V 7 8 9V
DBP
Output voltage VV
DD
= 4.5 V, I
OUT
= 25 mA 4 4.3
ERROR AMPLIFIER
T
J
= 25 ° C 0.698 0.7 0.704V
FB
Feedback regulation voltage total variation 0 ° C ≤T
J
≤85 ° C 0.69 0.7 0.707 V– 40 ° C ≤T
J
≤85 ° C 0.69 0.7 0.715V
SS
Soft-start offset from VSS
(1)
Offset from V
SS
to error amplifier 1 VG
BW
Gain bandwidth
(1)
5 10 MHzA
VOL
Open-loop gain 50 dBI
SRC
Output source current 2.5 4.5
mAI
SINK
Output sink current 2.5 6I
BIAS
Input bias current V
FB
= 0.7 V – 250 0 nA
(1) Ensured by design. Not production tested.
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
ELECTRICAL CHARACTERISTICS (continued)T
A
= – 40 ° C to 85 ° C, V
IN
= 12 V
dc
, R
T
= 90.9 k Ω, I
KFF
= 300 µA, f
SW
= 500 kHz, all parameters at zero power dissipation(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SHORT-CIRCUIT CURRENT PROTECTION
I
ILIM
Current sink into current limit 80 105 125 µAV
ILIM(ofst)
Current limit offset voltage (V
SW
– V
ILIM
) V
ILIM
= 11.5 V, V
VDD
= 12 V – 75 – 50 – 30 mVt
HSC
Minimum HDRV pulse duration During short circuit 135 225 nsPropagation delay to output
(2)
50 nst
BLANK
Blanking time
(2)
50 nst
OFF
Off time during a fault (SS cycle times) 7 CyclesSwitching level to end preconditionV
SW
2 V(V
VDD
– V
SW
)
(2)
t
PC
Precondition time
(2)
100 nsV
ILIM
Current limit precondition voltage threshold
(2)
6.8 V
OUTPUT DRIVERS
t
HFALL
High-side driver fall time (HDRV – SW)
(2)
36 nsC
HDRV
= 2200 pFt
HRISE
High-side driver rise time (HDRV – SW)
(2)
48 nst
HFALL
High-side driver fall time (HDRV – SW)
(2)
72 nsC
HDRV
= 2200 pF, V
VDD
= 4.5 V,0.2 V ≤V
SS
≤4 Vt
HRISE
High-side driver rise time (HDRV – SW)
(2)
96 nst
LFALL
Low-side driver fall time
(2)
24 nsC
LDRV
= 2200 pFt
LRISE
Low-side driver rise time
(2)
48 nst
LFALL
Low-side driver fall time
(2)
48 nsC
LDRV
= 2200 pF, V
VDD
= 4.5 V,0.2 V ≤V
SS
≤4 Vt
LRISE
Low-side driver rise time
(2)
96 nsI
HDRV
= – 0.01 A 0.7 1High-level output voltage, HDRVV
OH
V(V
BOOST
– V
HDRV
)
I
HDRV
= – 0.1 A 0.95 1.3I
HDRV
= 0.01A 0.06 0.1V
OL
Low-level output voltage, HDRV (V
HDRV
– V
SW
) VI
HDRV
= 0.1 A 0.65 1I
LDRV
= – 0.01A 0.65 1High-level output voltage, LDRVV
OH
V(V
DBP
– V
LDRV
)
I
LDRV
= – 0.1 A 0.875 1.2I
LDRV
= 0.01 A 0.03 0.05V
OL
Low-level output voltage, LDRV VI
LDRV
= 0.1 A 0.3 0.5
BOOST REGULATOR
V
BOOST
Output voltage V
DD
= 12 V 15.2 17 V
UVLO
V
UVLO
Programmable UVLO threshold voltage R
KFF
= 90.9 k Ω, turn-on, V
VDD
rising 6.2 7.2 8.2Programmable UVLO hysteresis R
KFF
= 90.9 k Ω1.1 1.55 2 VFixed UVLO threshold voltage Turn-on, V
VDD
rising 4.15 4.3 4.45Fixed UVLO hysteresis 275 365 mV
POWER GOOD
V
PG
Power-good voltage I
PG
= 1 mA 370 500V
OH
High-level output voltage, FB 770 mVV
OL
Low-level output voltage, FB 630
THERMAL SHUTDOWN
Shutdown temperature threshold
(2)
165
° CHysteresis
(2)
15
(2) Ensured by design. Not production tested.
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TYPICAL CHARACTERISTICS
TJ − Junction Temperature − °C
VLVPP − LVBP Voltage − V
−50 −25 50 100 1250
4.15
4.10
4.30
4.20
4.25
4.05
4.00 25 75
VDD = 28 V
VDD = 12 V
−50 −25 50 100 1250
8.00
7.90
8.15
8.05
8.10
7.85
7.80 25 75
7.95
VDBP − DBP Voltage − V
VDD = 28 V
VDD = 12 V
TJ − Junction Temperature − °C
−50 −25 50 100 1250
4.46
4.43
4.50
4.48
4.49
4.41
4.40 25 75
4.44
4.42
4.47
4.45
VDBP − DBP Voltage − V
VDD = 4.5 V
ILOAD = 25 mA
TJ − Junction Temperature − °C
VDROP − Bootstrap Diode Voltage Drop − V
TJ − Junction Temperature − °C
−50 −25 50 100 1250
1.6
1.3
2.0
1.7
1.9
1.1
1.0 25 75
1.4
1.8
1.5
1.2
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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LVBP VOLTAGE DBP VOLTAGEvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 1. Figure 2.
DBP VOLTAGE BOOTSTRAP DIODE VOLTAGEvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 3. Figure 4.
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−50 −25 50 100 1250
115
150
140
100 25 75
135
125
110
105
120
145
130
IILIM − Current Limit Sink Current − µA
TJ − Junction Temperature − °C
VDD
28 V
12 V
4.5 V
VILIM(offst) – Current Limit Offset Voltage Drop – mV
TJ – Junction Temperature – °C
−50 −25 50 100 1250
−40
0
−10
−60 25 75
−20
−30
−50
Average
+3 S
−3 S
fSW − Switching Frequency − kHz
VVDD − Input Voltage − V
4 8 16 24 2812 20
500
490
497
491
493
498
496
494
499
495
492
RRT = 90.1kΩ
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
TYPICAL CHARACTERISTICS (continued)
CURRENT LIMIT OFFSET VOLTAGE CURRENT LIMIT SINK CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 5. Figure 6.
FEEDBACK REGULATION VOLTAGE SWITCHING FREQUENCYvs vsJUNCTION TEMPERATURE INPUT VOLTAGE
Figure 7. Figure 8.
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−50 −25 50 100 1250 25 75
4.35
3.90
4.20
3.95
4.30
4.15
4.05
4.00
4.25
4.10
TJ − Junction Temperature − °C
VUVLO − Undervoltage Lockout Threshold − V
VUVLO(on)
VUVLO(off)
TJ − Junction Temperature − °C
DMAX − Maximum Duty Cycle − %
−50 −25 50 100 1250 25 75
93
83
90
84
86
92
89
87
85
91
88
fSW = 100 kHZ
fSW = 500 kHZ
fSW = 1 MHZ
−50 −25 50 100 1250 25 75
1.10
0.90
1.04
0.92
0.96
1.08
1.02
0.98
0.94
1.06
1.00
TJ − Junction Temperature − °C
VUVLO − Relative Programmable UVLO Threshold − %
VUVLO(on)
VUVLO(off)
TJ − Junction Temperature − °C
ISS − Soft−Start Charging Current − µA
−50 −25 50 100 1250 25 75
14.0
10.0
10.5
11.0
13.5
12.5
11.5
13.0
12.0
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
MAXIMUM DUTY CYCLE UNDERVOLTAGE LOCKOUTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 9. Figure 10.
PROGRAMMABLE UVLO THRESHOLD SOFT-START CHARGING CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 11. Figure 12.
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100
1.5
0.5 200 300 400 500 600 700 800 900 1000
1.0
3.0
2.0
2.5
3.5
5.0
4.0
4.5
VIN = 28 V
VIN = 24 V
VIN = 18 V
VIN = 15 V
VIN = 12 V
VIN = 10 V
VIN = 8 V
VIN = 5 V
fOSC − Oscillator Frequency − kHz
VOUT − Output Voltage − V
TJ − Junction Temperature − °C
IBIAS − Error Amplifier Input Bias Current − nA
−50 −25 50 100 1250 25 75
0
−90
−80
−70
−10
−30
−60
−20
−40
−50
RKFF − Feedforward Impedance − kΩ
100 150 250 300 350 450200 400
4
2
8
6
10
14
12
18
16
20
VUVLO − Programmable UVLO Threshold − V
UVLOVON
fSW = 300 kHz
UVLOVOFF
fSW − Switching Frequency − kHz
0
100
0200 400 600 800 1000
200
300
400
500
600
RT − T iming Resistance − k Ω
G017
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
TYPICAL CHARACTERISTICS (continued)
ERROR AMPLIFIER INPUT BIAS CURRENT MINIMUM OUTPUT VOLTAGEvs vsJUNCTION TEMPERATURE FREQUENCY
Figure 13. Figure 14.
SWITCHING FREQUENCY UNDERVOLTAGE LOCKOUT THRESHOLDvs vsTIMING RESISTANCE FEED-FORWARD IMPEDANCE
Figure 15. Figure 16.
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60 90 150 180 210 270120 240
4
2
8
6
10
14
12
18
16
20
RKFF − Feedforward Impedance − kΩ
VUVLO − Programmable UVLO Threshold − V
UVLOVON
fSW = 500 kHz
UVLOVOFF
40 60 100 120 140 18080 160
4
2
8
6
10
14
12
18
16
20
RKFF − Feedforward Impedance − kΩ
VUVLO − Programmable UVLO Threshold − V
UVLOVON
fSW = 750 kHz
UVLOVOFF
VDD − Input Voltage − V
VDBP − Driver Bypass Voltage − V
0
5
45 10 15 20 25
7
6
9
8
10
G024
8 16 20 24 28124
40
20
30
70
50
60
100
80
90
VIN − Input Voltage − V
Duty Cycle − %
UVLO(on) = 8 V
UVLO(on) = 15 V
UVLO(on) = 4.5 V
UVLO(on) = 12 V
G023
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
UNDERVOLTAGE LOCKOUT THRESHOLD UNDERVOLTAGE LOCKOUT THRESHOLDvs vsFEED-FORWARD IMPEDANCE FEED-FORWARD IMPEDANCE
Figure 17. Figure 18.
TYPICAL MAXIMUM DUTY CYCLE DBP VOLTAGEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 19. Figure 20.
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255 10 2015 30
4.10
4.00
4.05
4.15
4.20
4.35
4.25
4.30
4.40
4.45
4.50
VDD − Input Voltage − V
VDBP − Low Voltage Bypass Voltage − V
G025
DEVICE INFORMATION
Terminal Configuration
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
KFF
RT
LVBP
PGD
SGND
SS
FB
COMP
ILIM
Thermal
Pad
VDD
BOOST
HDRV
SW
DBP
LDRV
PGND
PWP PACKAGE(1)
(TOP VIEW)
P0047-01
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
TYPICAL CHARACTERISTICS (continued)
INPUT VOLTAGE
vsLOW-VOLTAGE BYPASS VOLTAGE
Figure 21.
(1) For more information on the PWP package, see the PowerPAD Thermally Enhanced Package technical brief(SLMA002 ).
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Table 1. Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
The peak voltage on BOOST is equal to the SW node voltage plus the voltage present at DBP less the bootstrapBOOST 14 I diode drop. This drop can be 1.4 V for the internal bootstrap diode or 300 mV for an external Schottky diode. Thevoltage differential between this pin and SW is the available drive voltage for the high-side FET.Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to theCOMP 8 O
FB pin to compensate the overall loop. The COMP pin is internally clamped to 3.4 V.8-V reference used for the gate drive of the N-channel synchronous rectifier. This pin should be bypassed toDBP 11 O
ground with a 1- µF ceramic capacitor.Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal referenceFB 7 I
voltage, 0.7 V.Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SWHDRV 13 O
(MOSFET off).Short-circuit-protection programming pin. This pin is used to set the short circuit detection threshold. An internalcurrent sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD.The voltage on this pin is compared to the voltage drop (V
VDD
– V
SW
) across the high side N-channel MOSFETILIM 16 I during conduction. Just prior to the beginning of a switching cycle, this pin is pulled to approximately VDD/2 andreleased when SW is within 2 V of V
DD
or after a timeout (the precondition time), whichever occurs first. Placing acapacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch-on time,effectively programming the ILIM blanking time. See Application Information.A resistor connected from this pin to VIN programs the amount of feed-forward voltage. The current fed into thisKFF 1 I pin is internally divided by 25 and used to control the slope of the PWM ramp and program undervoltage lockout.Nominal voltage at this pin is maintained at 400 mV.Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to ground (MOSFETLDRV 10 O
off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50 nC.4.2-V reference used for internal device logic only. This pin should be bypassed by a 0.1- µF ceramic capacitor.LVBP 3 O
External loads that are less than 1 mA and electrically quiet may be applied.This is an open-drain output that pulls to ground when soft start is active, or when the FB pin is outside a ± 10%PGD 4 O
band around VREF.Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of thePGND 9 –
lower MOSFET(s).RT 2 I A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.Signal ground reference for the device. Low-level quiet circuitry around the IC should connect to this pin. This pinSGND 5 – should be connected to the thermal pad under the IC, and that thermal pad should connect to the PGND pin. Donot allow power currents to flow in the thermal pad or in the SGND part of the ground for best results.Soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. Thecapacitor is charged with an internal current source of 12 µA. The resulting voltage ramp on the SS pin is used asa second noninverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V lessthan that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on the SSSS 6 I
pin reaches the internal offset voltage of 1 V plus the internal reference voltage of 700 mV. If SS is pulled below225 mV, the device goes into a shutdown state where the power FETSs are turned off and the prebias circuitry isreset. If the programmed UVLO voltage is below 6 V, connect a 330-k Ωresistor in parallel with the SS capacitor.Also provides timing for fault recovery attempts.This pin is connected to the switched node of the converter. It is used for short-circuit sensing and gate-driveSW 12 I timing information and is the return for the high-side driver. A 1.5- Ωresistor is required in series with this pin forprotection against substrate current issues.VDD 15 I Supply voltage for the device.
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11
13
10
15
3
2
1
VDD
LVBP
RT
KFF
DBP
HDRV
LDRV
4
5
7
6
PGD
SGND
FB
SS
8
COMP
Oscillator
16 ILIM
SW
CLK
12 SW
CLK
ILIM OC
9PGND
14 BOOST
VDD
UVLO
770mV
FB
630mV
SS Active
PWM
OC
CLK
UVLO
FAULT
DBP
+
+
700mV
RAMP
OC
CLK
SW
PGND
B0150-01
LVBP SS Active
Reference
Regulator
Ramp
Generator
Power
Good
Logic
UVLO
Controller
Pulse
Control
SoftStart
and
FaultControl
Predictive
GateDrive
Control
Logic
Short-Circuit
Comparator
andControl
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
FUNCTIONAL BLOCK DIAGRAM
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APPLICATION INFORMATION
MINIMUM PULSE DURATION
SLEW RATE LIMIT ON VDD
15
9
16
13
12
10
ILIM
HDRV
SW
LDRV
VDD
PGND
TPS40077
C
R
VIN
S0203-01
+
_
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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The TPS40077 allows the user to construct synchronous voltage-mode buck converters with inputs ranging from4.5 V to 28 V and outputs as low as 700 mV. Predictive Gate Drive circuitry optimizes switching delays forincreased efficiency and improved converter output-power capability. Voltage feed-forward is employed to easeloop compensation for wide-input-range designs and provide better line transient response.
The TPS40077 incorporates circuitry to allow startup into a preexisting output voltage without sinking currentfrom the source of the preexisting output voltage. This avoids damaging sensitive loads at start-up. An integratedpower-good indicator is available for logic (open-drain) output of the condition of the output of the converter.
The TPS40077 devices have limitations on the minimum pulse duration that can be used to design a converter.Reliable operation is assured for nominal pulse durations of 150 ns and above. This places some restrictions onthe conversion ratio that can be achieved at a given switching frequency. Figure 14 shows minimum outputvoltage for a given input voltage and frequency.
The regulator that supplies power for the drivers on the TPS40077 requires a limited rising slew rate on VDD forproper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can overshoot anddamage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than0.12 V/ µs as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of thedevice. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor fromthe VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor innormal operation. This places some constraints on the R-C values that can be used. Figure 22 is a schematicfragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for Rand C that limit the slew rate in the worst-case condition.
Figure 22. Limiting the Slew Rate
14 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS40077
CuVIN *8 V
R SR
(1)
Rt0.2 V
fSW Qg(TOT) )IDD
(2)
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
RT+ǒ1
fSW(kHz) 17.82 10*6*23ǓkW
(3)
PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO
RKFF +0.131 RT VUVLO(on) *1.61 10*3 VUVLO(on)2)1.886 VUVLO *1.363 *0.02 RT*4.87 10*5 R2
T
TPS40077
www.ti.com
..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
where
•V
VIN
is the final value of the input voltage ramp•f
SW
is the switching frequency•Q
g(TOT)
is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet)•I
DD
is the TPS40077 input current (3.5 mA maximum)•SR is the maximum allowed slew rate [12 × 10
4
] (V/s)
The TPS40077 has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves asthe master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the switchingfrequency of the clock oscillator. The clock frequency is related to R
T
by:
The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator providesvoltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant rampmagnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations,because the PWM is not required to wait for loop delays before changing the duty cycle. (See Figure 23 ).
The PWM ramp must reach approximately 1 V in amplitude during a clock cycle, or the PWM is not allowed tostart. The PWM ramp time is programmed via a single resistor (R
KFF
) connected from KFF VDD. R
KFF
, V
START
,and R
T
are related by (approximately):
(4)
where
•R
T
and R
KFF
are in k Ω
•V
UVLO(on)
is in V
This yields typical numbers for the programmed startup voltage. The minimum and maximum values may vary upto ± 15% from this number. Figure 16 through Figure 18 show the typical relationship of V
UVLO(on)
, V
UVLO(off)
andR
KFF
at three common frequencies.
The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. Forexample, if the startup voltage is programmed to be 10 V, the controller starts when V
DD
reaches 10 V and shutsdown when V
DD
falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twicethe startup voltage. Below this point, the maximum duty cycle is as specified in the Electrical Characteristicstable. Note that with this scheme, the theoretical maximum output voltage that the converter can produce isapproximately two times the programmed startup voltage. For design, set the programmed startup voltage equalto or greater than the desired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz andbelow). For example, a 5-V output converter should not have a programmed startup voltage below 5.9 V.Figure 23 shows the theoretical maximum duty cycle (typical) for various programmed startup voltages.
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s) :TPS40077
VDG−03172
RAMP
COMP
SW
VIN
VIN
SW
COMP
RAMP
VPEAK
VVALLEY
T2
tON1 > tON2 and d1 > d2
tON2
tON1
d+tON
T
T1
PROGRAMMING SOFT START
tSTART w2p L COUT
Ǹ
(5)
CSS +tSS ISS
VFB
(6)
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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Figure 23. Voltage Feed-Forward and PWM Duty Cycle Waveforms
TPS40077 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft start isprogrammed by connecting an external capacitor (C
SS
) from the SS pin to GND. This capacitor is charged by afixed current, generating a ramp signal. The voltage on SS is level-shifted down approximately 1 V and fed into aseparate noninverting input to the error amplifier. The loop is closed on the lower of the level-shifted SS voltageor the 700-mV internal reference voltage. Once the level-shifted SS voltage rises above the internal referencevoltage, output-voltage regulation is based on the internal reference. To ensure a controlled ramp-up of theoutput voltage, the soft-start time should be greater than the L-C
OUT
time constant or:
Note that there is a direct correlation between t
START
and the input current required during start-up. The lowert
START
is, the higher the input current required during start-up, because the output capacitance must be chargedfaster. For a desired soft-start time, the soft-start capacitance, C
SS
, can be found from:
16 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
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PROGRAMMING SHORT-CIRCUIT PROTECTION
ILIM Threshold
T2
T1 ILIM Threshold
T3
T1
ILIM
ILIM
SW
SW
VIN − 2V
VIN − 2V
UDG−03173
Overcurrent
(A)
(B)
TPS40077
www.ti.com
..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
The TPS40077 uses a two-tier approach for short-circuit protection. The first tier is a pulse-by-pulse protectionscheme. Short-circuit protection is implemented on the high-side MOSFET by sensing the voltage drop acrossthe MOSFET when its gate is driven high. The MOSFET voltage is compared to the voltage dropped across aresistor (R
ILIM
) connected from V
VDD
to the ILIM pin when driven by a constant-current sink. If the voltage dropacross the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediatelyterminated. The MOSFET remains off until the next switching cycle is initiated. This is illustrated in Figure 24 .
Figure 24. Switching and Current-Limit Waveforms and Timing Relationship
In addition, just prior to the high-side MOSFET turning on, the ILIM pin is pulled down to approximately half ofV
VDD
. The ILIM pin is allowed to return to its nominal value after one of two events occurs. If the SW node risesto within approximately 2 V of V
VDD
, the device allows ILIM to go back to its nominal value. This is illustrated inFigure 24 (A). T1 is the delay time from the internal PWM signal being asserted and the rise of SW. This includesa driver delay of 50 ns, typical. T2 is the reaction time of the sensing circuit that allows ILIM to start to return toits nominal value, typically 20 ns. The second event that can cause ILIM to return to its nominal value is for aninternal timeout to expire. This is illustrated in Figure 24 (B) as T3. Here SW never rises to V
VDD
– 2 V, forwhatever reason, and the internal timer times out, releasing the ILIM pin.
Prior to ILIM starting back to its nominal value, overcurrent sensing is not enabled. In normal operation, thisensures that the SW node is at a higher voltage than ILIM when overcurrent sensing starts, avoiding false tripswhile allowing for a quicker blanking delay than would ordinarily be possible. Placing a capacitor across R
ILIMsets an exponential approach to the normal voltage at the ILIM pin. This exponential decay of the overcurrentthreshold can be used to compensate for ringing on the SW node after its rising edge and to help compensatefor slower-turnon FETs. Choosing the proper capacitance requires care. If the capacitance is too large, thevoltage at ILIM does not approach the desired overcurrent level quickly enough, resulting in an apparent shift inovercurrent threshold as pulse duration changes. As a general rule, it is best to make the time constant of theR-C at the ILIM pin 0.2 times or less of the nominal pulse duration of the converter as shown in Equation 11 .
Also, the comparator that uses ILIM and SW to determine if an overcurrent condition exists has a clamp on itsSW input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be asmuch as 2 V at – 40 ° C) below V
VDD
. When ILIM is more than 1.4 V below V
VDD
, the overcurrent circuit iseffectively disabled.
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s) :TPS40077
ISCP(min) uǒCOUT VOUT
tSTART Ǔ)ILOAD )ǒIRIPPLE
2Ǔ
(7)
RILIM +ISCP RDS(onMAX) )VILIM (offset)
IILIM
W
(8)
ISCP(max) +1.09 IILIM(max) RILIM *0.09 RVDD IRVDD *0.045 V )75 mV
RDS(ON)min (A)
(9)
ISCP(min) +1.09 IILIM(min) RILIM *0.09 RVDD IRVDD *0.045 V )30 mV
RDS(ON)max (A)
(10)
CILIM(max) +VOUT 0.2
VIN RILIM fSW (Farads)
(11)
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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The second-tier protection incorporates a fault counter. The fault counter is incremented on each cycle with anovercurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reachesseven (7), a fault condition is declared by the controller. When this happens, the outputs are placed in a statedefined in Table 2 . Seven soft-start cycles are initiated (without activity on the HDRV and LDRV outputs) and thePWM is disabled during this period. The counter is decremented on each soft-start cycle. When the counter isdecremented to zero, the PWM is re-enabled and the controller attempts to restart. If the fault has beenremoved, the output starts up normally. If the output is still present, the counter counts seven overcurrent pulsesand re-enters the second-tier fault mode. Refer to Figure 25 for typical fault-protection waveforms.
The minimum short-circuit limit setpoint (I
SCP(min)
) depends on t
START
, C
OUT
, V
OUT
, ripple current in the inductor(I
RIPPLE
), and the load current at turnon (I
LOAD
).
The short-circuit limit programming resistor (R
ILIM
) is calculated from:
where
•I
ILIM
is the current into the ILIM pin (110 µA, typical)•V
ILIM(offset)
is the offset voltage of the ILIM comparator ( – 50 mV, typical)•I
SCP
is the short-circuit protection current
To find the range of the overcurrent values, use the following equations:
The TPS40077 provides short-circuit protection only. Therefore, it is recommended that the minimum short-circuitprotection level be placed at least 20% above the maximum output current required from the converter. Themaximum output of the converter should be the steady state maximum output plus any transient specificationthat may exist.
The ILIM capacitor maximum value can be found from:
Note that this is a recommended maximum value. If a smaller value can be used, it should be. For mostapplications, consider using half the maximum value above.
18 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS40077
VDG−03174
tBLANKING
7 Current-Limit Trips
(HDRV Cycle Terminated by Current-Limit Trip) 7
Soft-Start
Cycles
HDRV
Clock
VILIM
VVIN − VSW
SS
LOOP COMPENSATION
SHUTDOWN AND SEQUENCING
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
Figure 25. Typical Fault Protection Waveforms
Voltage-mode, buck-type converters are typically compensated using Type III networks. Because the TPS40077uses voltage feed-forward control, the gain of the voltage feed-forward circuit must be included in the PWM gain.The gain of the voltage feed-forward circuit, combined with the PWM circuit and power stage for the TPS40077is:
K
PWM
≅V
UVLO(on)
The remainder of the loop compensation is performed as in a normal buck converter. Note that the voltagefeed-forward circuitry removes the input voltage term from the expression for PWM gain. PWM gain is strictly afunction of the programmed startup voltage.
The TPS40077 can be shut down by pulling the SS pin below 250 mV. In this state, both of the output drivers arein the low-output state, turning off both of the power FETs. This places the output of the converter in ahigh-impedance state. When shutting down the converter, a crisp pulldown of the SS pin is preferred to a slowpulldown. A slow pulldown could allow the output to be pulled low, possibly sinking current from the load. As ageneral rule of thumb, the fall time of SS when shutting down the converter should be no more than 1/10th of thecontrol loop crossover frequency. An example of a shutdown interface is shown in Figure 26 .
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s) :TPS40077
6SS
S0204-01
Shutdown
TPS40077
6
64
4SS
SS ToSystemPowerGood
PGD
PGD
S0205-01
TPS40077
TPS40077
BOOST AND LVBP BYPASS CAPACITANCE
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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Figure 26. TPS40077 Shutdown
In a similar manner, power supplies based on the TPS40077 can be sequenced by connecting the PGD pin ofthe first supply to come up to the SS pin of the second supply as shown in Figure 27 .
Figure 27. TPS40077 Sequencing
The BOOST capacitance provides a local, low-impedance flying source for the high-side driver. The BOOSTcapacitor should be a good-quality, high-frequency capacitor. A capacitor with a minimum value of 100-nF issuggested.
The LVBP pin must provide energy for both the synchronous MOSFET and the high-side MOSFET (via theBOOST capacitor). The suggested value for this capacitor is 1- µF ceramic, minimum.
20 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS40077
INTERNAL REGULATORS
TPS40077 POWER DISSIPATION
PT+ǒ2 PD
VDR )IQǓ VIN (Watts)
(14)
PT+ǒ2 Qg fSW )IQǓ VIN (Watts)
(15)
PT+TJ*TA
qJA (Watts)
(16)
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
The internal regulators are linear regulators that provide controlled voltages from which the drivers and theinternal circuitry operate. The DBP pin is connected to a nominal 8-V regulator that provides power for the drivercircuits. This regulator has two modes of operation. At V
DD
voltages below 8.5 V, the regulator is in a low-dropoutmode of operation and tries to provide as little impedance as possible from VDD to DBP. Above 10 V at V
DD
, theregulator regulates DBP to 8 V. Between these two voltages, the regulator remains in the state it was in whenV
DD
entered this region (see Figure 20 ). Small amounts of current can be drawn from this pin for other circuitfunctions, as long as power dissipation in the controller device remains at acceptable levels and junctiontemperature does not exceed 125 ° C.
The LVBP pin is connected to another internal regulator that provides 4.2 V (nom) for the operation oflow-voltage circuitry in the controller. This pin can be used for other circuit purposes, but extreme care must betaken to ensure that no extra noise is coupled onto this pin; otherwise, controller performance suffers. Currentdraw is not to exceed 1 mA. See Figure 21 for typical output voltage at this pin.
The power dissipation in the TPS40077 is largely dependent on the MOSFET driver currents and the inputvoltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power(neglecting external gate resistance) can be calculated from:
P
D
= Q
g
× V
DR
× f
SW
(Watts/driver)
where V
DR
is the driver output voltage
The total power dissipation in the TPS40077, assuming the same MOSFET is selected for both the high-side andsynchronous rectifier, is described in Equation 14 or Equation 15 .
or
where I
Q
is the quiescent operating current (neglecting drivers)
The maximum power capability of the TPS40077 PowerPAD package is dependent on the layout as well as airflow. The thermal impedance from junction to air, assuming 2-oz. copper trace and thermal pad with solder andno air flow, is 37 ° C/W. See the application report titled PowerPAD Thermally Enhanced Package (SLMA002 ) fordetailed information on PowerPAD package mounting and usage.
The maximum allowable package power dissipation is related to ambient temperature by Equation 16 . For θ
JA
,see the Package Dissipation Ratings table.
Substituting Equation 16 into Equation 15 and solving for f
SW
yields the maximum operating frequency for theTPS40077. The result is described in Equation 17 .
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s) :TPS40077
fSW +ǒƪǒTJ*TAǓ
ǒqJA VDDǓƫ*IQǓ
ǒ2 QgǓ(Hz)
(17)
BOOST DIODE
GROUNDING AND BOARD LAYOUT
SYNCHRONOUS RECTIFIER CONTROL
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
www.ti.com
The TPS40077 series has internal diodes to charge the boost capacitor connected from SW to BOOST. The dropacross these diodes is rather large, 1.4 V nominal, at room temperature. If this drop is too large for a particularapplication, an external diode may be connected from DBP (anode) to BOOST (cathode). This providessignificantly improved gate drive for the high-side FET, especially at lower input voltages.
The TPS40077 provides separate signal ground (SGND) and power ground (PGND) pins. Care should be givento proper separation of the circuit grounds. Each ground should consist of a plane to minimize its impedance, ifpossible. The high-power noisy circuits such as the output, synchronous rectifier, MOSFET driver decouplingcapacitor (DBP), and the input capacitor should be connected to PGND plane.
Sensitive nodes such as the FB resistor divider and RT should be connected to the SGND plane. The SGNDplane should only make a single-point connection to the PGND plane. It is suggested that the SGND pin be tiedto the copper area for the thermal pad underneath the chip. Tie the PGND to the thermal-pad copper area aswell, and make the connection to the power circuit ground from the PGND pin. Reference the output voltagedivider to the SGND pin.
Component placement should ensure that bypass capacitors (LVPB and DBP) are located as close as possibleto their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be locatednear high-dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow careful layoutpractices results in suboptimal operation. More detailed information can be found in the TPS40077EVM User'sGuide (SLVU192 ).
Table 2 describes the state of the rectifier MOSFET control under various operating conditions.
Table 2. Synchronous Rectifier MOSFET States
SYNCHRONOUS RECTIFIER OPERATION DURING
FAULTSOFT-START NORMAL (FAULT RECOVERY IS SAME OVERVOLTAGEAS SOFT-START)
Turns OFF only at start of nextOff until first high-side pulse is Turns off at the start of a new
cycle only if the pulse widthdetected, then on when high-side cycle. Turns on when the OFF
modulator duty cycle is greaterMOSFET is off high-side MOSFET is turned off
than zero. Otherwise, stays ON
For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50 nC.
22 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS40077
APPLICATION 1: BUCK REGULATOR 8-V TO 16-V INPUT, 1.8-V OUTPUT AT 10 A
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
Table 3. Specifications
PARAMETER NOTES AND CONDITIONS MIN NOM MAX UNITS
INPUT CHARACTERSTICS
V
IN
Input voltage 8 12 16 VI
IN
Input current V
IN
= NOM, I
OUT
= MAX 1.8 2 ANo-load input current V
IN
= NOM, I
OUT
= 0 A 62.6 3.6 mAV
IN_UVLO
Input UVLO I
OUT
= MIN to MAX 5.4 6 6.6 VV
IN_ONV
Input ONV I
OUT
= MIN to MAX 6.3 7 7.7 V
OUTPUT CHARACTERSTICS
V
OUT
Output voltage V
IN
= NOM, I
OUT
= NOM 1.75 1.8 1.85 VLine regulation
(1)
V
IN
= MIN to MAX, I
OUT
= NOM 0.5%Load regulation
(1)
V
IN
= NOM, I
OUT
= MIN to MAX 0.5%V
OUT_ripple
Output voltage ripple V
IN
= NOM, I
OUT
= MAX 100 mVppI
OUT
Output current V
IN
= MIN to MAX 0 5 10 AOutput overcurrentI
OCP
V
IN
= NOM, V
OUT
= V
OUT
– 5% 12.25 19.4 34 Ainception pointV
OVP
Output OVP I
OUT
= MIN to MAX NA NA NA
Transient response
ΔI Load step I
OUT_Max
to 0.2 × I
OUT _Max
8 ALoad slew rate 10 A/ µsOvershoot 200 mVSettling time 1 ms
SYSTEM CHARACTERSTICS
f
SW
Switching frequency 240 300 360 kHzη
pk
Peak efficiency V
IN
= NOM, I
OUT
= MIN to MAX 90%ηFull-load efficiency V
IN
= NOM, I
OUT
= MAX 90%Operating temperatureT
op
V
IN
= MIN to MAX, I
OUT
= MIN to MAX – 40 25 85 ° Crange
MECHANICAL CHARACTERSTICS
2 InchesL Width
5.08 cm3 InchesW Length
7.62 cm0.41 Inchh Component height
1.04 cm
(1) Voltage accuracy is dependent on resistor tolerance and reference accuracy. Line and load regulation are calculated with respect to theactual set point voltage.
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s) :TPS40077
Schematic and Performance Curves
RSET
CP2
RPGD
RT
CPZ1
RLIM
+
RPZ2
CSS
CBP5
+
RP1
RZ1
CDBP
CDELAY
LOUT
CBOOST
7FB
4PGD
1KFF
10
LDRV
13
HDRV
16
ILIM
8COMP
5SGND
2RT
3BP5
9
PGND
12
SW
15
VDD
14
BOOST
6SS 11
DBP
PWP
RKFF
CZ2
QSW
QSR
CVDD
V =1.8V
I upto10 A
OUT
OUT
R10
330kW
C11
0.1 Fm
0V
VOUT
C
ELCO
IN
C_OUT
MLCC
C
ELCO
OUT
C13
2.2nF
R4
0W
C_IN
MLCC
U1
TPS40077PWP
VIN
S0239-01
IOUT − Load Current − A
0
10
20
30
40
50
60
70
80
90
100
012345678910
η − Efficiency − %
G026
8 V 12 V 16 V
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
www.ti.com
Figure 28. Schematic Diagram
Figure 29. Module Efficiency, 8 V, 12 V, and 16 V In, 0 to 10 A Out
24 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS40077
f − Frequency − Hz
0
5
10
15
20
25
30
35
40
45
50
Gain − dB
Phase − °
Gain
Phase
100 1k 10k 1M100k
200
180
160
140
120
100
80
40
0
G027
20
60
Component Selection
LOUT +VOUT
VIN(max) VIN(max) *VOUT
fs IRIPPLE
(18)
ILOUT_RMS +IOUT2)IRIPPLE2
12
Ǹ+10.02 A
(19)
IPK +IOUT )IRIPPLE
2+11.03 A
(20)
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
Figure 30. Bode Plot Showing 57 ° Phase Margin at Crossover Frequency of 54 kHz
Power Train Components
Output Inductor, LOUT
The output inductor is one of the most important components to select. It stores the energy necessary to keepthe output regulated when the switch FET is turned off. The value of the output inductor dictates the peak andRMS currents in the converter. These currents are important when selecting other components. Equation (1) canbe used to calculate a value for LOUT for this module which operates at a switching frequency (f) of 300 kHz.
I
RIPPLE
is the allowable ripple in the inductor. Select I
RIPPLE
to be between 20% and 30% of maximum I
OUT
. Forthis design, I
RIPPLE
of 2.5 A was selected. Calculated LOUT is 2.13 µH. A standard inductor with value of 2.5 µHwas chosen. This will reduce I
RIPPLE
by about 17% to 2.07 A.
This I
RIPPLE
value can be used calculate the rms and peak current flowing in LOUT. Note that this peak current isalso seen by the switching FET and synchronous rectifier.
The power loss from the selected inductor DCR is 357 mW. The ac core loss for this Coilcraft inductor may befound from the Coilcraft Web site, where there is a loss calculator . The loss is 179 mW.
The inductor is selected with a saturation current higher than this current plus the current that is developedcharging the output capacitance during the soft-start interval.
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s) :TPS40077
COUT +LOUT ISTEP2
2 VUNDER Dmax (VIN *VOUT)
(21)
COUT +LOUT ISTEP2
2 VOVER VOUT
(22)
ESR +VRIPPLE
IRIPPLE
(23)
ICAP(RMS) +ƪǒIOUT *IIN(AVG)Ǔ2)IRIPPLE2
12 ƫ D)IIN(AVG)2 (1 *D)
Ǹ
(24)
IQSW(RMS) +VOUT
VIN(MIN) ƪIOUT(MAX)2)IRIPPLE2
12 ƫ
Ǹ
(25)
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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Output Capacitor, COUT, ELCO and MLCC
Several parameters must be considered when selecting the output capacitor. The capacitance value should beselected based on the output overshoot, V
OVER
, and undershoot, V
UNDER
, during a transient load, I
STEP
, on theconverter. The equivalent series resistance (ESR) is chosen to allow the converter to meet the output ripplespecification, V
RIPPLE
. The voltage rating must be greater than the maximum output voltage. Another parameterto consider is equivalent series inductance, which is important in fast-transient load situations. Also, size andtechnology can be factors when choosing the output capacitor. In this design, a large-capacitance electrolytictype capacitor, COUT ELCO, is used to meet the overshoot and undershoot specifications. Its ESR is chosen tomeet the output ripple specification. Smaller multiple-layer ceramic capacitors, COUT MLCC, are used to filterhigh-frequency noise.
The minimum required capacitance and maximum ESR can be calculated using the following equations.
From Equation 21 ,Equation 22 , and Equation 23 , the capacitance for COUT should be greater than 444 µF, andits ESR should be less than 12 m Ω. The 470- µF/6.3-V capacitor from Panasonic's FC series was chosen. ItsESR is 160 m Ω. MLCCs of 47 µF and 22 µF/16 V are also added in parallel to achieve the required ESR and toreduce high-frequency noise.
Input Capacitor, CIN ELCO and MLCC
The input capacitor is selected to handle the ripple current of the buck stage. Also, a relatively large capacitanceis used to keep the ripple voltage on the supply line low. This is especially important where the supply line hashigh impedance. It is recommended however, that the supply-line impedance be kept as low as possible.
The input-capacitor ripple current can be calculated using Equation 24 .
I
IN(AVG)
is the average input current. This is calculated simply by multiplying the output dc current by the dutycycle. The ripple current in the input capacitor is 3.3 A. An 1812 MLCC using X5R material has a typicaldissipation factor of 5%. For a 22- µF capacitor at 300 kHz, the ESR is approximately 4 m Ω. Two capacitors areused in parallel, so the power dissipation in each capacitor is less than 11 mW.
A 470- µF/16-V electrolytic is added to maintain the voltage on the input rail.
Switching MOSFET, QSW
The following key parameters must be met by the selected MOSFET.•Drain source voltage, V
ds
, must be able to withstand the input voltage plus spikes that may be on theswitching node. For this design a V
ds
rating of 30 volts is recommended.•Drain current, I
D
, at 25 ° C, must be greater than that calculated using Equation 25 .
•With the parameters specified, the calculation of I
QSW(RMS)
should be greater than 5 A.•Gate source voltage, V
gs
, must be able to withstand the gate voltage from the control IC. For the TPS40077,
26 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS40077
PQSW +PCON )PSW )PGATE
(26)
PCON +RDS(on) IQSW(RMS)2+RDS(on) VOUT
VIN ƪIout2)IRIPPLE2
12 ƫ
(27)
PSW +VIN fS ȧ
ȧ
ȧ
ȧ
ȱ
Ȳ
ǒIOUT )IRIPPLE
2Ǔ ǒQgs1 )QgdǓ
Ig)QOSS(SW) )QOSS(SR)
12 ȧ
ȧ
ȧ
ȧ
ȳ
ȴ
(28)
PGATE +Qg(TOT) Vg fSW
(29)
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
this is 11 V.
Once the above boundary parameters are defined, the next step in selecting the switching MOSFET is to selectthe key performance parameters. Efficiency is the performance characteristic which drives the other selectioncriteria. Target efficiency for this design is 90%. Based on 1.8-V output and 10 A, this equates to a power loss inthe converter of 1.8 W. Based on this figure, a target of 0.6 W dissipated in the switching FET was chosen.
The following equations can be used to calculate the power loss, P
QSW
, in the switching MOSFET.
where
P
CON
= conduction lossesP
SW
= switching lossesP
GATE
= gate-drive lossesQ
gd
= drain-source charge or Miller chargeQ
gs1
= gate-source post-threshold chargeI
g
= gate-drive currentQ
OSS(SW)
= switching MOSFET output chargeQ
OSS(SR)
= synchronous MOSFET output chargeQ
g(TOT)
= total gate charge from zero volts to the gate voltageV
g
= gate voltage
If the total estimated loss is split evenly between conduction and switching losses, Equation 27 and Equation 28yield preliminary values for R
DS(on)
and (Q
gs1
+ Q
gd
). Note output losses due to Q
OSS
and gate losses have beenignored here. Once a MOSFET is selected, these parameters can be added.
The switching MOSFET for this design should have an R
DS(on)
of less than 8 m Ω. The sum of Q
gd
and Q
gs
shouldbe approximately 4 nC.
It may not always be possible to get a MOSFET which meets both these criteria, so a compromise may benecessary. Also, by selecting different MOSFETs close to these criteria and calculating power loss, the finalselection can be made. It was found that the Si7860DP MOSFET from Vishay semiconductor gave reasonableresults. This device has an R
DS(on)
of 8 m Ωand a (Q
gs1
+ Q
gd
) of 5 nC. The estimated conduction losses are0.115 W and the switching losses are 0.276 W. This gives a total estimated power loss of 0.391 W versus 0.6 Wfor our initial boundary condition. Note this does not include gate losses of approximately 71 mW and outputlosses of 20 mW.
Rectifier MOSFET, QSR
Similar criteria to the foregoing can be used for the rectifier MOSFET. There is one significant difference: due tothe body diode conducting, the rectifier MOSFET switches with zero voltage across its drain and source, soeffectively with zero switching losses. However, there are some losses in the body diode. These are minimizedby reducing the delay time between the transition from the switching MOSFET turnoff to rectifier MOSFET turnonand vice-versa. The TPS40077 incorporates TI's proprietary Predictive Gate Drive circuitry (PGD), which helpsreduce these delays to around 10 ns.
The equations used to calculate the losses in the rectifier MOSFET are:
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 27
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PQSR +PCON )PBD )PGATE
(30)
PCON +RDS(on) ƪ1*VOUT
VIN *ǒt1)t2Ǔ fSƫ ƪIout2)IRIPPLE2
12 ƫ
(31)
PBD +Vf IOUT ǒt1)t2Ǔ fS
(32)
PGATE +Qg(TOTAL) Vg fS
(33)
RT+1
fS 17.82 10*6*23
(34)
RKFF +0.131 RT VUVLO(on) *1.61 10*3 VUVLO(on)2)1.886 VUVLO *1.363 *0.02 RT
*4.87 10*5 RT2
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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where
P
BD
= body diode lossest
1
= body diode conduction prior to turnon of channel = 12 ns for PGDt
2
= body diode conduction after turnoff of channel = 12 ns for PGDV
f
= body diode forward voltage
Estimating the body diode losses based on a forward voltage of 1 V gives 0.072 W. The gate losses areunknown at this time, so assume 0.1-W gate losses. This leaves 0.428 W for conduction losses. Using thisfigure, a target R
DS(on)
of 5 m Ωwas calculated.
The Si7336ADP from Vishay was chosen. Using the parameters from its data sheet, the actual expected powerlosses are calculated. Conduction loss is 0.317 W, body diode loss is 0.072 W, and the gate loss is 0.136W. Thistotals 0.525 W associated with the rectifier MOSFET.
Two other criteria should be verified before finalizing on the rectifier MOSFET. One is the requirement to ensurethat predictive gate drive functions correctly. The turnoff delay of the Si7336ADP is 97 ns. The minimum turnoffdelay of the Si7860DP is 25 ns. Together these devices meet the 130-ns requirement.
Secondly, the ratio between C
gs
and C
gd
should be greater than 1. The Si7336ADP easily meets this criterion.This helps reduce the risk of dv/dt-induced turnon of the rectifier MOSFET. If this is likely to be a problem, asmall resistor may be added in series with the boost capacitor, CBOOST.
Component Selection for TPS40077
Timing Resistor, R
T
The timing resistor is calculated using the following equation.
This gives a resistor value of 165 k Ω. The nominal frequency using this resistor is 300 kHz.
Feed-Forward and UVLO Resistor, R
KFF
A resistor connected to the KFF pin of the IC feeds into the ramp generator. This resistor provides current intothe ramp generator proportional to the input voltage. The ramp is then adjusted to compensate for different inputvoltages. This provides the voltage feed-forward feature of the TPS40077.
The same resistor also sets the undervoltage lockout point. The input start voltage should be used to calculate avalue for R
KFF
. For this module, the minimum input voltage is 8 V; however, due to tolerances in the IC, a startvoltage of 10% less than the minimum input voltage is selected. The start voltage for R
KFF
calculation is 7.2 V.Using Equation 35 , R
KFF
can be selected.
(35)
where R
KFF
and R
T
are in k Ω.
This equation gives an R
KFF
value of 156 k Ω. The closest lower standard value of 154 k Ωshould be selected.This gives a minimum start voltage of 7.1 V.
28 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS40077
tSTART w2p LOUT COUT
Ǹ
(36)
CSS +ISS
VFB tSTART
(37)
ISCP wCOUT VOUT
tSTART )IPK
(38)
RILIM +ISCP RDS(on)MAX )VILIM(Max)
ILIM(Min)
(39)
ISCP(MIN) +IILIM(MIN) RILIM(MIN) *VILIM(MAX)
RDS(on)MAX
(40)
ISCP(MAX) +IILIM(MAX) RILIM(MAX) *VILIM(MIN)
RDS(on)MIN
(41)
CILIM(Max) +VOUT 0.2
VIN RILIM fS
(42)
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
Soft-Start Capacitor, CSS
It is good practice to limit the rise time of the output voltage. This helps prevent output overshoot and possibledamage to the load. The selection of the soft-start time is arbitrary. It must meet one condition: it should begreater than the time constant of the output filter, LOUT and COUT. This time is given by
The soft-start time must be greater than 0.23 ms. A time of 0.75 ms was chosen. This time also helps limit theinitial input current during start-up so that the peak current plus the capacitor start-up current is less than theminimum short-circuit current. The value of CSS can be calculated using Equation 37 .
A standard 15-nF MLCC capacitor was chosen. The calculated start time using this capacitor is 0.875 ms.
Short-Circuit Protection, R
ILIM
and C
ILIM
Short-circuit protection is programmed using the R
ILIM
resistor. Selection of this resistor depends on the R
DS(on)
ofthe switching MOSFET selected and the required short-circuit current trip point, I
SCP
. The minimum I
SCP
is limitedby the inductor peak current, the output voltage, the output capacitor, and the soft-start time. Their relationship isgiven by Equation 38 . A short-circuit current trip point greater than that calculated by this equation should beused.
The minimum short-circuit current trip point for this design is 12.25 A. This value is used in Equation 39 tocalculate the minimum R
ILIM
value.
R
ILIM
is calculated to be 1.17 k Ω, and a 1.2-k Ωresistor is used to verify that the short-circuit current requirementsare met. The minimum and maximum short-circuit current can be calculated using Equation 40 and Equation 41 .
where: V
ILIM(MAX)
and V
ILIM(MIN)
are maximum and minimum voltages across the high side FET when it is turnedon, taking into account temperature variations.
The minimum I
SCP
is 12.25 A, and the maximum is 34 A.
It is also recommended to add a small capacitor, C
ILIM
, across R
ILIM
. The value of this capacitor should be abouthalf the value calculated in Equation 42 .
This equation yields a maximum C
ILIM
as 55 pF. A smaller value of 27 pF is chosen is chosen.
Boost Voltage, CBOOST and DBOOST (Optional)
To be able to drive an N-channel MOSFET in the switch location of a buck converter, a capacitor charge pumpor boost circuit is required. The TPS40077 contains the elements for this boost circuit. The designer must onlyadd a capacitor, CBOOST, from the switch node of the buck power stage to the BOOST pin of the IC. Selectionof this capacitor is based on the total gate charge of the switching MOSFET and the allowable ripple on theboost voltage, ΔV
BOOST
. A ripple of 0.2 V is assumed for this design. Using these two parameters andEquation 43 , the minimum value for CBOOST can be calculated.
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s) :TPS40077
CBOOST uQg(TOTAL)
DVBOOST
(43)
Closing the Feedback Loop, R
Z1
, R
P1
, R
PZ2
, R
SET1
, R
SET2
, C
Z2
, C
P2
, and C
PZ1
KPWM ^VUVLO
1 V
(44)
KLC +1)s ESR COUT
1)s LOUT
ROUT )s2 LOUT COUT
(45)
Gc(s) +KPWM KLC VUVLO
1 V 1)s ESR COUT
1)s LOUT
ROUT )s2 LOUT COUT
(46)
DCGAIN +20 logƪVUVLO
VRAMPƫ+20 log(7) +16.9 dB
(47)
fLC_Pole +1
2p LOUT COUT
Ǹ+4.3 kHz
(48)
fESR_Zero +1
2p ESR COUT +2.1 kHz
(49)
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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The total gate charge of the switching MOSFET is 23 nC. A minimum CBOOST of 0.092 µF is required. A 0.1 µFcapacitor was chosen. This capacitor must be able to withstand the maximum input voltage plus the maximumvoltage on DBP. This is 13.2 V plus 9.0 V, which is 22.2 V. A 50-V capacitor is used.
To reduce losses in the TPS40077 and to increase the available gate voltage for the switching MOSFET, anexternal diode can be added between the DBP pin and the BOOST pin of the IC. A small-signal Schottky diodeshould be used here, such as the BAT54.
A graphical method is used to select the compensation components. This is a standard feed-forward buckconverter. Its PWM gain is given by Equation 44 .
The ramp voltage is 1 V at the UVLO voltage. Because of the feed-forward compensation, the programmedUVLO voltage is the voltage that sets the PWM gain.
The gain of the output LC filter is given by Equation 45 .
The PWM and LC gain is
To plot this on a Bode plot, the dc gain must be expressed in dB. The dc gain is equal to KPWM. To express thisin dB, take its logarithm and multiply by 20. For this converter, the dc gain is
Also, the pole and zero frequencies should be calculated. A double pole is associated with the LC and a zero isassociated with the ESR of the output capacitor. The frequencies where these occur can be calculated usingequations,
These are shown in the Bode plot of Figure 31 .
30 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS40077
f − Frequency − kHz
−60
−50
−40
−30
−20
−10
0
10
20
30
Gain − dB
G028
0.1 1 10 1k100
ESR Zero
Double Pole
ESR = 0.16 Ω
Slope = –20 dB/Decade
FB
COMP
TPS40077
SS
6
7
8
VOUT
RP1
RZ1
RPZ2
RSET
CPZ1
CZ2
CP2
S0240-01
TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
Figure 31. PWM and LC Filter Gain
The next step is to establish the required compensation gain to achieve the desired overall system response.The target response is to have the crossover frequency between 1/9 and 1/5 times the switching frequency, inorder to have a phase margin greater than 45 ° and a gain margin greater than 6 dB.
A type-III compensation network, shown in Figure 32 , was used for this design. This network gives the bestoverall flexibility for compensating the converter.
Figure 32. Type-III Compensation With the TPS40077
A typical Bode plot for this type of compensation network is shown in Figure 33 .
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s) :TPS40077
f − Frequency − kHz
−20
−10
0
10
20
30
40
Gain − dB
G029
0.1 1 10 1k100
High-Frequency Gain
fZ1 fZ2 fP1 fP2
VOUT +VREF RZ1 )RSET
RSET
(50)
GAIN +RPZ2 RZ1 )RP1
RZ1 RP1
(51)
fP1 +1
2p RP1 CPZ1
(52)
fP2 +CP2 )CZ2
2p RPZ2 CP2 CZ2 [1
2p RPZ2 CP2
(53)
fZ1 +1
2p RZ1 CPZ1
(54)
fZ2 +1
2p ǒRPZ2 )RP1Ǔ CZ2 [1
2p RPZ2 CZ2
(55)
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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Figure 33. Type-III Compensation Typical Bode Plot
The high-frequency gain and the break (pole and zero) frequencies are calculated using the following equations.
Looking at the PWM and LC bode plot, there are a few things which must be done to achieve stability.1. Place two zeros close to the double pole, e.g., f
Z1
= f
Z2
= 4.3 kHz2. Place both poles well above the crossover frequency. The crossover frequency was selected as one sixth theswitching frequency, f
co1
= 50 kHz, f
P1
= 66 kHz3. Place the second pole at three times f
co1
. This ensures that the overall system gain falls off quickly to givegood gain margin, f
p2
= 150 kHz4. The high-frequency gain should be sufficient to ensure 0 dB at the required crossover frequency, GAIN = – 1× gain of PWM and LC at the crossover frequency, GAIN = 16.9 dB
Using these values and Equation 50 through Equation 55 , the Rs and Cs around the compensation network canbe calculated.
1. Set R
Z1
= 51 k Ω
2. Calculate R
SET
using Equation 50 , R
SET
= 32.4 k Ω
3. Using Equation 54 and f
z1
= 4.3 kHz, C
PZ1
can be calculated to be 726 pF, C
PZ1
= 680 pF4. f
P1
and Equation 52 yields R
P1
to be a standard value of 3.3 k Ω.
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TPS40077
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..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
5. The required gain of 16.9 dB and Equation 51 sets the value for R
PZ2
. R
PZ2
= 21.5 k Ω.6. C
Z2
is calculated using Equation 55 and the desired frequency for the second zero, C
Z2
= 1.7 nF, or usingstandard values, 1.8 nF.7. Finally, C
P2
is calculated using the second pole frequency and Equation 53 ; C
P2
= 47 pF.
Using these values, the simulated results are 57 ° of phase margin at 54 kHz.
Table 4. Bill of Materials
RefDes Count Value Description Size Part Number Mfr
C1 1 470 µF Capacitor, aluminum, 470- µF, 25-V, 20% 0.457 x 0.406 EEVFK1E471P PanasonicC2, C10 2 0.1 µF Capacitor, ceramic, 25-V, X7R, 20% 0603 Std VishayC3 1 15 nF Capacitor, ceramic, 25-V, X7R 20% 0603 Std VishayC4 1 47 pF Capacitor, ceramic, 25-V, X7R, 20% 0603 Std VishayC5 1 1.8 nF Capacitor, ceramic, 25-V, X7R 20% 0603 Std VishayC6 1 680 pF Capacitor, ceramic, 25-V, X7R 20% 0603 Std VishayC7 1 51 pF Capacitor, ceramic, 25-V, COG 20% 0603 Std VishayC8, C11 2 0.1 µF Capacitor, ceramic, 25-V, X7R, 20% 0603 Std VishayC9 1 1 µF Capacitor, ceramic, 25-V, X7R, 20% 0805 Std VishayC12, C14, 3 22 µF Capacitor, ceramic, 22- µF, 16-V, X5R, 20% 1812 C4532X5R1C226MT TDKC15
C13 1 2.2 nF Capacitor, ceramic, 25-V, X7R, 20% 0603 Std VishayC16 1 470 µF Capacitor, aluminum, SM, 6.3-V, 300-m Ω8 mm × 10 Std Panasonic(FC series) mmC17 1 47 µF Capacitor, ceramic, 47-uF, 6.3-V, X5R, 20% 1812 C4532X5R0J476MT TDKD1 1 BAT54 Diode, Schottky, 200-mA, 30-V SOT23 BAT54 VishayJ1, J2 2 ED1609-ND Terminal block, 2-pin, 15-A, 5,1-mm 0.40 × 0.35 ED1609 OSTJ3 1 PTC36SAAN Header, 2-pin, 100-mil spacing, (36-pin 0.100 × 2 PTC36SAAN Sullinsstrip)L1 1 2.5 µH Inductor, SMT, 2.5 µH, 16.5-A, 3.4- m Ω0.515 × 0.516 MLC1550-252ML CoilcraftQ1 1 Si7860DP MOSFET, N-channel, 30-V, 18-A, 8.0-m ΩPWRPAK Si7860DP VishayS0-8Q2 1 Si7336ADP MOSFET, N-channel, 30-V, 18-A, 40-m ΩPWRPAK Si7886ADP VishayS0-8Q3 1 FDV301N MOSFET, N-channel, 25-V, 220-mA, 5- ΩSOT23 FDV301N FairchildR1 1 10 k ΩResistor, chip, 1/16-W, 20% 0603 Std StdR2, R6 2 165 k ΩResistor, Chip, 1/16-W, 20% 0603 Std StdR3 1 32.4 k ΩResistor, chip, 1/16-W, 20% 0603 Std StdR4, R11 2 0 ΩResistor, chip, 1/16-W, 20% 0603 Std StdR5 1 21.5 k ΩResistor, chip, 1/16-W, 20% 0603 Std StdR7 1 51 k ΩResistor, chip, 1/16-W, 20% 0603 Std StdR8 1 3.3 k ΩResistor, chip, 1/16-W, 20% 0603 Std StdR9 1 1.8 k ΩResistor, chip, 1/16-W, 20% 0603 Std StdR10 1 330 k ΩResistor, chip, 1/16-W, 20% 0603 Std StdR12 1 51 ΩResistor, chip, 1/16-W, 20% 0603 Std StdR13 1 1 k ΩResistor, chip, 1/16-W, 20% 0603 Std StdU1 1 TPS40077PWP IC, Texas Instruments PWP16 TPS40077PWP TI
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s) :TPS40077
EXAMPLE APPLICATIONS
S0209-01
1
2
3
4
16
15
14
13
ILIM
VDD
BOOST
HDRV
KFF
RT
LVBP
PGD
TPS40077PWP
5
6
7
8
12
11
10
9
SW
DBP
LDRV
PGND
SGND
SS
FB
COMP
+
+
–
PWP
+ +
–
V
1.8V
10 A
OUT
C18
0.1 Fm
C12
22 Fm
C8
0.1 Fm
C7
10pF
C100.1 Fm
C91 Fm
R9
2kW
R8
226 W
R3
5.49kW
R5
10kW
R2
165kW
R6
165kW
V
12V
DD
R78.66kW
C14
22 Fm
C17
470 Fm
C16
470 Fm
C15
47 Fm
C6
4.7nF
C5
5.6nF
C4470pF
C322nF
C20.1 Fm
C13
4.7nF
L1
Pulse
PG0077.202
2 Hm
D1
BAT54
Q1
Si7840BDP
Q2
Si7856ADP
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
www.ti.com
Figure 34. 300 kHz, 12 V to 1.8 V
34 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS40077
S0210-01
1
2
3
4
16
15
14
13
ILIM
VDD
BOOST
HDRV
KFF
RT
LVBP
PGD
TPS40077PWP
5
6
7
8
12
11
10
9
SW
DBP
LDRV
PGND
SGND
SS
FB
COMP
+
+
–
PWP
+ +
–
V
1.8V
10 A
OUT
C18
0.1 Fm
C12
22 Fm
C8
0.1 Fm
C7
10pF
C100.1 Fm
C91 Fm
R9
2kW
R8
226 W
R3
5.49kW
R5
10kW
R2
165kW
R6
165kW
V
12V
DD
R78.66kW
C14
22 Fm
C17
470 Fm
C16
470 Fm
C15
47 Fm
C6
4.7nF
C5
5.6nF
C4470pF
C322nF
C20.1 Fm
C13
4.7nF
L1
Pulse
PG0077.202
2 Hm
D1
BAT54
Q1
Si7840BDP
Q2
Si7856ADP
TPS40077
www.ti.com
..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
See the Boost Diode section.
Figure 35. 300 kHz, 12 V to 1.8 V With Improved High-Side Gate Drive
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s) :TPS40077
S0211-01
1
2
3
4
16
15
14
13
ILIM
VDD
BOOST
HDRV
KFF
RT
LVBP
PGD
TPS40077PWP
5
6
7
8
12
11
10
9
SW
DBP
LDRV
PGND
SGND
SS
FB
COMP
+
+
–
PWP
+ +
–
Note:Resistoracrosssoftstartcapacitor.
V
1.2V
10 A
OUT
C18
0.1 Fm
C12
22 Fm
C8
0.1 Fm
C7
10pF
C100.1 Fm
C91 Fm
R9
2kW
R8
226 W
R3
12.1kW
R5
10kW
R2
90.1kW
R6
47kW
V
5V
DD
R78.66kW
R4330kW
C14
22 Fm
C17
470 Fm
C16
470 Fm
C15
47 Fm
C6
4.7nF
C5
5.6nF
C4470pF
C322nF
C20.1 Fm
C13
4.7nF
L1
Pulse
PG0077.202
2 Hm
D1
BAT54
Q1
Si7860DP
Q2
Si7860DP
REFERENCES
Related Parts
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
www.ti.com
See the Boost Diode section.
Figure 36. 500 kHz, 5 V to 1.2 V With Improved High-Side Gate Drive
The following parts are similar to the TPS40077 and may be of interest:•TPS40190 Low Pin Count Synchronous Buck Controller (SLUS658 )•TPS40100 Midrange Input Synchronous Buck Controller With Advanced Sequencing and Output Margining(SLUS601 )•TPS40075 Midrange Input Synchronous Buck Controller With Voltage Feed-Forward (SLUS676 )•TPS40057 Wide-Input Synchronous Buck Controller (SLUS593 )
36 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS40077
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS40077PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40077PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40077PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40077PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Mar-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS40077PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS40077PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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