PRELIMINARY Integrated Circuit Systems, Inc. ICS844051-11 FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS844051-11 is a Gigabit Ethernet Generator and a member of the HiPerClocks TM HiPerClockSTM family of high performance devices from ICS. The ICS844051-11 can synthesize 10 Gigabit Ethernet, SONET, or Serial ATA reference clock frequencies with the appropriate choice of crystal and output divider. The ICS844051-11 has excellent phase jitter performance and is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. * (1) Differential LVDS output ICS * Crystal oscillator interface designed for 18pF parallel resonant crystals * RMS phase jitter at 156.25MHz (1.875MHz - 20MHz): 0.45ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request FREQUENCY TABLE Inputs Crystal Frequency (MHz) FREQ_SEL Output Frequency (MHz) 25 0 150 25 1 75 26.041666 0 156.25 26.041666 1 78.125 26.5625 0 159.375 26.5625 1 79.675 BLOCK DIAGRAM PIN ASSIGNMENT FREQ_SEL XTAL_IN OSC XTAL_OUT Phase Detector VCO 0 /4 1 /8 (default) /24 (fixed) nQ0 Q0 VDD XTAL_OUT XTAL_IN GND 1 2 3 4 8 7 6 5 Q0 nQ0 VDD FREQ_SEL ICS844051-11 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 844051AG-11 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 28, 2005 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS844051-11 FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 6 4 VDD XTAL_OUT, XTAL_IN GND Power 5 FREQ_SEL Input 7, 8 nQ0, Q0 Output 2, 3 Type Description Power Power supply pins. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Power supply ground. Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. Differential clock outputs. LVDS interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k 844051AG-11 Test Conditions www.icst.com/products/hiperclocks.html 2 Minimum Typical Maximum Units REV. A FEBRUARY 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844051-11 FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 101.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C Symbol Parameter VDD Core Supply Voltage Test Conditions IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V TBD mA TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current FREQ_SEL VDD = VIN = 3.465V IIL Input Low Current FREQ_SEL VDD = 3.465V, VIN = 0V Minimum Typical 5 -150 A A TABLE 3C. LVDS DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C Symbol Parameter VOD Differential Output Voltage Test Conditions Minimum Typical Maximum Units 400 mV VOD VOD Magnitude Change 40 mV VOS Offset Voltage 1.3 V VOS VOS Magnitude Change 50 mV TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units 40 MHz Fundamental Frequency 12 Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Maximum Units TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C Symbol Parameter fOUT Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time tjit(O) tR / tF Test Conditions Integration Range: 1.875MHz - 20MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. 844051AG-11 www.icst.com/products/hiperclocks.html 3 Minimum Typical 156.25 MHz 0.45 ps 350 ps 50 % REV. A FEBRUARY 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844051-11 FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION VDD DD SCOPE out + Float GND - LVDS DC Input LVDS 100 Qx Power Supply VOD/ VOD nQx LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL OUTPUT VOLTAGE SETUP Phase Noise Plot Noise Power VDD DD out LVDS DC Input out out Phase Noise Mask VOS/ VOS f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot OFFSET VOLTAGE SETUP RMS PHASE JITTER nQ0 80% 80% Q0 VSW I N G Clock Outputs Pulse Width 20% 20% tR t PERIOD tF odc = t PW t PERIOD OUTPUT RISE/FALL TIME 844051AG-11 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 4 REV. A FEBRUARY 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844051-11 FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR APPLICATION INFORMATION LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 1. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - Differiential 100 Ohm 100 Differential Transmission TransmissionLine Line FIGURE 1. TYPICAL LVDS DRIVER TERMINATION CRYSTAL INPUT INTERFACE nant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS844051-11 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using an 18pF parallel reso- XTAL_OUT C1 12p X1 18pF Parallel Cry stal XTAL_IN C2 12p Figure 2. CRYSTAL INPUt INTERFACE 844051AG-11 www.icst.com/products/hiperclocks.html 5 REV. A FEBRUARY 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844051-11 FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR SCHEMATIC EXAMPLE Figure 3 shows an example of ICS844051-11 application schematic. In this example, the device is operated at VDD=3.3V. The decoupling capacitor should be located as close as possible to the power pin. The input is driven by a 25Mhz, 18pf, Quartz crystal. For the LVDS output drivers, place a 100 ohm resistor as close to the receiver as possible. VDD C3 10uF C4 0.01u Zo = 50 Ohm U1 C2 12pF 25 MHz 18pF 1 2 3 4 X1 Q VDD XTAL_OUT XTAL_IN GND Q0 nQ0 VDD FREQ_SEL 8 7 6 5 R1 100 + FREQ_SEL Zo = 50 Ohm - nQ 844051-1_tssop8_s ICS844051-11 C1 12pF FIGURE 3. APPLICATION SCHEMATIC EXAMPLE RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7C/W 90.5C/W 89.8C/W TRANSISTOR COUNT The transistor count for ICS844051-11 is: 2533 844051AG-11 www.icst.com/products/hiperclocks.html 6 REV. A FEBRUARY 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS844051-11 FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR 8 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 844051AG-11 www.icst.com/products/hiperclocks.html 7 REV. A FEBRUARY 28, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844051-11 FEMTOCLOCKSTM CRYSTAL-TO- LVDS CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS844051AG-11 51A11 8 lead TSSOP tube 0C to 70C ICS844051AG-11T 51A11 8 lead TSSOP 2500 tape & reel 0C to 70C The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844051AG-11 www.icst.com/products/hiperclocks.html 8 REV. A FEBRUARY 28, 2005