ICS844051AG-11 - Integrated Device Technology

844051AG-11 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 28, 2005

Integrated

Circuit

Systems, Inc.

ICS844051-11

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

GENERAL DESCRIPTION

The ICS844051-11 is a Gigabit Ethernet

Generator and a member of the HiPerClocksTM

family of high performance devices from ICS.

The ICS844051-11 can synthesize 10 Gigabit

Ethernet, SONET, or Serial ATA reference

clock frequencies with the appropriate choice of crystal

and output divider. The ICS844051-11 has excellent phase

jitter performance and is packaged in a small 8-pin TSSOP,

making it ideal for use in systems with limited board space.

FEATURES

•(1) Differential LVDS output

•Crystal oscillator interface designed for

18pF parallel resonant crystals

•RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):

0.45ps (typical)

•3.3V operating supply

•0°C to 70°C ambient operating temperature

•Industrial temperature information available upon request

HiPerClockS™

ICS

ICS844051-11

8-Lead TSSOP

4.40mm x 3.0mm x 0.925mm

package body

G Package

Top View

VDD

XTAL_OUT

XTAL_IN

GND

nQ0

VDD

FREQ_SEL

BLOCK DIAGRAM

OSC Phase

Detector VCO

0 ÷4

1 ÷8 (default)

÷24

(fixed)

XTAL_IN

XTAL_OUT

nQ0

FREQUENCY TABLE

stupnI ycneuqerFtuptuO

)zHM(

)zHM(ycneuqerFlatsyrCLES_QERF

520051

52157

666140.62052.651

666140.621521.87

5265.620573.95

5265.621576.97

PIN ASSIGNMENT

FREQ_SEL

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

844051AG-11 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 28, 2005

Integrated

Circuit

Systems, Inc.

ICS844051-11

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

TABLE 2. PIN CHARACTERISTICS

TABLE 1. PIN DESCRIPTIONS

rebmuNemaNepyTnoitpircseD

6,1V

rewoP.snipylppusrewoP

3,2 ,TUO_LATX

NI_LATX tupnI ,tupniehtsiNI_LATX.ecafretnirotallicsolatsyrC

.tuptuoehtsiTUO_LATX

4DNGrewoP.dnuorgylppusrewoP

5LES_QERFtupnIpulluP.slevelecafretniLTTVL/SOMCVL.niptcelesycneuqerF

8,70Q,0

QntuptuO.slevelecafretniSDVL.stuptuokcolclaitnereffiD

:ETON

pulluP

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

PULLUP

rotsiseRpulluPtupnI 15kΩ

844051AG-11 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 28, 2005

Integrated

Circuit

Systems, Inc.

ICS844051-11

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

tnerruCylppuSrewoP DBTAm

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI-0.5V to VDD + 0.5 V

Outputs, IO (LVDS)

Continuous Current 10mA

Surge Current 15mA

Package Thermal Impedance, θ

JA 101.7°C/W (0 mps)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the

DC Characteristics

AC Character-

istics

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI 2V

3.0+V

egatloVwoLtupnI 3.0-8.0V

tnerruChgiHtupnILES_QERFV

V564.3=5Aµ

tnerruCwoLtupnILES_QERFV

V,V564.3=

V0=051-Aµ

TABLE 3C. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVtuptuOlaitnereffiD 004Vm

∆V

egnahCedutingaM 04Vm

egatloVtesffO 3.1V

∆V

egnahCedutingaM 05Vm

TABLE 4. CRYSTAL CHARACTERISTICS

retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

noitallicsOfoedoM latnemadnuF

ycneuqerF 2104zHM

)RSE(ecnatsiseR

seireStnelaviuqE 05 Ω

ecnaticapaCtnuhS 7Fp

TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 52.651zHM

)Ø(tij ;)modnaR(rettiJesahPSMR

1ETON

:egnaRnoitargetnI

zHM02-zHM578.1 54.0sp

emiTllaF/esiRtuptuO%08ot%02053sp

cdoelcyCytuDtuptuO 05%

.tolPesioNesahPehtotreferesaelP:1ETON

844051AG-11 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 28, 2005

Integrated

Circuit

Systems, Inc.

ICS844051-11

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

PARAMETER MEASUREMENT INFORMATION

OFFSET VOLTAGE SETUP RMS PHASE JITTER

LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL OUTPUT VOLTAGE SETUP

OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

SCOPE

nQx

LVDS

Power Supply

Float GND

nQ0

➤

100

out

LVDS

DC Input VOD/∆ VOD

VDD

out

LVDS

DC Input

➤

/∆ V

VDD

Clock

Outputs 20%

80% 80%

20%

SWING

Pulse Width

tPERIOD

tPW

tPERIOD

odc =

Phase Noise Mas

Offset Frequency

Phase Noise Plot

RMS Jitter = Area Under the Masked Phase Noise Plot

Noise Power

844051AG-11 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 28, 2005

Integrated

Circuit

Systems, Inc.

ICS844051-11

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

APPLICATION INFORMATION

LVDS DRIVER TERMINATION

A general LVDS interface is shown in

Figure 1.

In a 100Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100Ω across near

100 Ohm Differiential Transmission Line

100

3.3V

LVDS_Driv er

3.3V

FIGURE 1. TYPICAL LVDS DRIVER TERMINATION

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate the

un-used outputs.

100ΩΩ

ΩΩ

Ω Differential Transmission Line

Figure 2. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The ICS844051-11 has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 2

below were determined using an 18pF parallel reso-

nant crystal and were chosen to minimize the ppm error. The

optimum C1 and C2 values can be slightly adjusted for different

board layouts.

18pF Parallel Cry stal

12p

XTA L_OU T

XTA L_ I N

12p

844051AG-11 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 28, 2005

Integrated

Circuit

Systems, Inc.

ICS844051-11

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS844051-11 is: 2533

TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP

θθ

θJA by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

SCHEMATIC EXAMPLE

Figure 3

shows an example of ICS844051-11 application sche-

matic. In this example, the device is operated at VDD=3.3V. The

decoupling capacitor should be located as close as possible to

the power pin. The input is driven by a 25Mhz, 18pf, Quartz

crystal. For the LVDS output drivers, place a 100 ohm resistor

as close to the receiver as possible.

FIGURE 3. APPLICATION SCHEMATIC EXAMPLE

Zo = 50 Ohm

FREQ_SEL

12pF

844051-1_tssop8_s

VDD

XTAL_OUT

XTAL_IN

GND

nQ0

VDD

FREQ_SEL

0.01u

Zo = 50 Ohm

25 MHz

100

VDD

18pF

10uF

12pF

ICS844051-11

844051AG-11 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 28, 2005

Integrated

Circuit

Systems, Inc.

ICS844051-11

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP

TABLE 7. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

LOBMYS sretemilliM

muminiMmumixaM

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D09.201.3

ECISAB04.6

1E03.405.4

eCISAB56.0

L54

.057.0

α°0°8

aaa--01.0

844051AG-11 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 28, 2005

Integrated

Circuit

Systems, Inc.

ICS844051-11

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

TABLE 8. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are

not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS

product for use in life support devices or critical medical instruments.

rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT

11-GA150448SCI11A15POSSTdael8ebutC°07otC°0

T11-GA150

448SCI11A15POSSTdael8leer&epat0052C°07otC°0

The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.