DM93L28N - Fairchild Semiconductor

March 1989

Revised August 1999

DM93L28 Dual 8-Bit Shift Register

DM93L28

Dual 8-Bit Shift Register

General Descript ion

The DM9 3L28 is a high speed seria l storage eleme nt pro-

viding 16 bits of storage in the form of two 8-bit registers.

The multifunctional capability of this device is provided by

several features: 1) additional gating is provided at the

input to both sh ift registe rs so th at t he inpu t is easi ly mult i-

plexed betwe en two sources; 2) the clock of each r egister

may be provided separately or together; 3) both the true

and complementary outputs are provided from each 8-bit

common input.

Features

■2-input multiplexer provided at data input of each

■Gated clock input circuitry

■Both true and complementary outputs provided from last

bit of each register

■Asynchronous master reset common to both registers

Ordering Code:

Logic Symbol

VCC = Pin 16 GND = Pin 8

Connection Diagram

Pin Descriptions

Order Number Package Number Package Description

DM93L28N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

S Data Select Input

D0, D1 Data Inputs

CP Clock Pulse Input (Active HIGH)

Common (Pin 9)

Separate (Pins 7 and 10)

MR Master Reset Input (Active LOW)

Q7 Last Stage Output

Q7 Complementary Output

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DM93L28

Functional Description

The two 8-bit shift registers have a common clock input

(pin 9) and separate clock inputs (pins 10 and 7). The

clocking of each register is controlled by the OR function of

the sepa rate a nd the commo n clock in put. Each registe r is

composed of eight clocked RS master/slave flip-flops and a

number of ga tes. T he cl ock OR g ate dr ives the eig ht clock

inputs of the flip-flops in parallel. When the two clock inputs

(the separate and the common) to the OR gate are LOW,

the sla ve latches are ste ad y, but data ca n en ter the m aste r

latches via the R and S input. During the first LOW-to-

HIGH transition of either, or both simultaneously, of the two

clock inputs, the data inputs (R and S) are inhibited so that

a later ch ange in in put data will not affect the maste r; then

the now trapped infor mation in the mast er is transferre d to

the slave. When the transfer is complete, both the master

and the slave are steady as long as either or both clock

inputs re main HIGH. Du rin g the HIGH- to- LOW t ran sition of

the la st remain ing HIG H clock inp ut, the tr ansfer path fro m

master to slave is inhibited first, leaving the slave steady in

its present state. The data inputs (R and S) are enabled so

that new data can enter the master. Either of the clock

inputs can be used as clock inhibit inputs by applying a

logic HIGH signal. Each 8-bit shift register has a 2-input

multiplexer in front of the serial data input. The two data

inputs D0 and D1 are controlled by the data select input (S)

following the Boolean expression:

Serial data in: SD = SD0 + SD1

An asynchronous master reset is provided which, when

activated by a LOW logic level, will clear all 16 stages inde-

pendently of any other input signal.

Shift Select Table

H = HIGH Voltage Lev el

L = LOW Voltage Level

X = Immaterial

n+8 = Indicates stat e after eight clock pulse

Logic Diagram

Inputs Output

SD0D1 Q7 (t

n+8)

LL X L

LH X H

HX L L

HX H H

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DM93L28

Absolute Maximum Ratings(Note 1)

Note 1: The “Abso lute Maxim um Ratings” ar e those value s beyond whic h

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “Re comm ended Operat ing Co ndition s” table will de fine the cond itions

for actu al device operation.

Recommended Operating Conditions

Electri cal Characteristics

over recommended operating free air temperature (unless otherwise noted)

Note 2: N ot m ore than one output sh ould be sh orted at a tim e, and the duration sh ould not ex c eed one sec ond.

Supply Voltage 7V

Input Voltage 5.5V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.5 5 5.5 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.7 V

IOH HIGH Level Output Current −400 µA

IOL LOW Level Output Current 4.8 mA

TAFree Air Operating Temperature 0 +7°°C

ts(H) Setup Time HIGH or LOW 30 ns

ts(L) Dn to CP 30

th(H) Hold Time HIGH or LOW 0 ns

th(L) Dn to CP 0

tw(H) Clock Pulse Width 55 ns

tw(L) HIGH or LOW 55

tw(L) MR Pulse Width with CP HIGH 60 ns

tw(L) MR Pulse Width with CP LOW 70 ns

Symbol Parameter Conditions Min Max Units

VIInput Clamp Voltage VCC = Min, II = −10 mA −1.5 V

VOH HIGH Level Output Voltage VCC = Mi n, I OH = Max, 2.4 V

VIL = Max, VIH = Min

VOL LOW Level Output Voltage VCC = Mi n, I OL = Max, 0.3 V

VIH = Min, VIL = Max

IIInput Current @ Max VCC = Max, VI = 5.5V 1 mA

Input Voltage

IIH HIGH Level VCC = Max, VI = 2.4V MR, Dx 20

Input Current CP (7, 10) 30 µA

S40

CP Com 60

IIL LOW Level VCC = Max, VI = 0.3V MR, Dx −400

Input Current CP (7, 10) −600 µA

S−800

CP Com −1200

IOS Short Circuit VCC = Max −2.5 −25 mA

Output Current (Note 2)

ICC Supply Current VCC = Max 25.3 mA

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DM93L28

Switching Characteri stics

VCC = +5.0V, TA = +25°C

Symbol Parameter CL = 15 pF Units

Min Max

fMAX Maximum Shift Right Frequency 5.0 MHz

tPLH Propagation Delay 45 ns

tPHL CP to Q7 or Q780

tPHL Propagation Delay MR to Q7110 ns

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DM93L28 Dual 8-Bit Shift Register

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16EUnits

Fairchild does not assume any responsibility for use of any circu itry described , no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the labe l ing, can be re a-

sonably expected to result in a significant injury to the

user.

2. A criti cal com ponen t in any compo nent o f a l ife supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t

device or system, or to affect its safety or effectiveness.