5962-9955701Q2A - Texas Instruments High-Performance Analog

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JUL Y 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

DDual 12-Bit Voltage Output DAC

DProgrammable Settling Time

– 3 µs in Fast Mode

– 10 µs in Slow Mode

DCompatible With TMS320 and SPI Serial

Ports

DDifferential Nonlinearity <0.5 LSB Typ

DMonotonic Over Temperature

DDirect Replacement for TLC5618A (C and I

Suffixes)

DAvailable in Q-Temp Automotive

HighRel Automotive Applications

Configuration Control/Print Support

Qualification to Automotive Standards

applications

DDigital Servo Control Loops

DDigital Offset and Gain Adjustment

DIndustrial Process Control

DMachine and Motion Control Devices

DMass Storage Devices

description

The TLV5618A is a dual 12-bit voltage output DAC

with a flexible 3-wire serial interface. The serial

interface is compatible with TMS320, SPI,

QSPI, and Microwireserial ports. It is

programmed with a 16-bit serial string containing

4 control and 12 data bits.

The resistor string output voltage is buffered by an

x2 gain rail-to-rail output buffer. The buffer

features a Class-AB output stage to improve

stability and reduce settling time. The program-

mable settling time of the DAC allows the designer

to optimize speed versus power dissipation.

Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It

is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges.

The TL V5618AC is characterized for operation from 0°C to 70°C. The TL V5618AI is characterized for operation

from –40°C to 85°C. The TLV5618AQ is characterized for operation from –40°C to 125°C. The TLV5618AM

is characterized for operation from –55°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

TAPLASTIC DIP

(P) SOIC

(D) CERAMIC DIP

(JG) 20 PAD LCCC

(FK)

0°C to 70°C TLV5618ACP TLV5618ACD — —

–40°C to 85°C TLV5618AIP TLV5618AID — —

–40°C to 125°C — TLV5618AQD

TLV5618AQDR — —

–55°C to 125°C — — TLV5618AMJG TLV5618AMFK

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

DIN

SCLK

OUTA

VDD

OUTB

REF

AGND

P, D OR JG PACKAGE

(TOP VIEW)

1920132

1312119 10

OUTB

REF

SCLK

DIN

OUTA

AGND

FK PACKAGE

(TOP VIEW)

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JULY 2002

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Serial

Interface

and

Control

12-Bit

DAC B

Latch

SCLK

DIN

OUTA

Power-On

Reset

Power and

Speed Control

12-Bit

DAC A

Latch

REF AGND VDD

12 12

OUTB

Buffer

Terminal Functions

TERMINAL

I/O/P

DESCRIPTION

NAME NO. I/O/P DESCRIPTION

AGND 5 P Ground

CS 3 I Chip select. Digital input active low, used to enable/disable inputs.

DIN 1 I Digital serial data input

OUTA 4 O DAC A analog voltage output

OUTB 7 O DAC B analog voltage output

REF 6 I Analog reference voltage input

SCLK 2 I Digital serial clock input

VDD 8 P Positive power supply

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JULY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5618AC 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5618AI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5618AQ –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5618AM –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

DISSIPATION RATING TABLE

PACKAGE

≤ 25°CDERATING F ACTOR T

= 70°C T

= 85°C T

= 125°C

PACKAGE

≤

25 C

POWER RATING

DERATING

FACTOR

ABOVE TA = 25°C‡

70 C

POWER RATING

85 C

POWER RATING

125 C

POWER RATING

D635 mW 5.08 mW/°C407 mW 330 mW 127 mW

FK 1375 mW 11.00 mW/°C 880 mW 715 mW 275 mW

JG 1050 mW 8.40 mW/°C672 mW 546 mW 210 mW

‡This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistances are not production tested and are for

informational purposes only.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage V

VDD = 5 V 4.5 5 5.5

Supply voltage, VDD VDD = 3 V 2.7 3 3.3 V

Power on reset 0.55 2 V

High level digital input voltage V

VDD = 2.7 V 2

High-level digital input voltage, VIH VDD = 5.5 V 2.4 V

Low level digital input voltage V

VDD = 2.7 V 0.6

Low-level digital input voltage, VIL VDD = 5.5 V 1V

Reference voltage V to REF terminal

VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5

Reference voltage, V ref to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

Load resistance, RL2 kΩ

Load capacitance, CL100 pF

Clock frequency, f(CLK) 20 MHz

TLV5618AC 0 70

erating free air tem

erature TA

TLV5618AI –40 85

°C

Operating free-air temperature, TATLV5618AQ –40 125 °C

TLV5618AM –55 125

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD–0.4 V)/2 causes clipping of the transfer function.

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JULY 2002

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VDD = 4.5 V to Fast 1.8 2.5

VDD

4.5

55V

5.5 V

C&I

Slow

Power supply current

No load, All inputs = AGND or VDD = 2.7 V to

suffixes Fast 1.6 2.2

IDD Power supply current

load

All

in uts

AGND

VDD DAC latch = All ones

VDD

2.7

33V

Slow

IDD

Power

su ly

current

DD,

DAC

All

ones

Slow 0.6 0.9

Fast

VDD = 2.7 V to M & Q Fast 1.8 2.3

VDD

2.7

5.5 V

suffixes Slow 0.8 1 mA

Power down supply current 1µA

PSRR

Power supply rejection ratio

Zero scale, See Note 2 –65

PSRR Power supply rejection ratio Full scale, See Note 3 –65 dB

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin)/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:

PSRR = 20 log [(EG(VDDmax) – EG(VDDmin)/VDDmax]

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 12 bits

INL Integral nonlinearity See Note 4 ±2±4LSB

DNL Differential nonlinearity See Note 5 ±0.5 ±1LSB

EZS Zero-scale error (offset error at zero

scale) See Note 6 ±12 mV

EZS (TC) Zero-scale-error temperature

coefficient See Note 7 3ppm/°C

C & I suffixes

VDD = 4.5 V – 5.5 V ±0.29

%f ll

EGGain error See Note 8 C & I suffixes VDD = 2.7 V – 3.3 V ±0.6 % full

scale V

Gain

error

See

Note

M & Q suffixes VDD = 2.7 V – 5.5 V ±0.6 sca

EG (TC) Gain-error temperature coefficient See Note 9 1ppm/°C

NOTES: 4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error , is the maximum deviation of the output

from the line between zero and full scale, excluding the effects of zero-code and full-scale errors.

5. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal

1-LSB amplitude change of any two adjacent codes.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/2Vref ×106/(Tmax – Tmin).

8. Gain error is the deviation from the ideal output (2V ref – 1 LSB) with an output load of 10 kΩ.

9. Gain temperature coefficient is given by: EG TC = [EG (Tmax) – Eg (Tmin)]/2Vref ×106/(Tmax – Tmin).

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOOutput voltage range RL = 10 kΩ0 VDD–0.4 V

Output load regulation accuracy VO = 4.096 V, 2.048 V,

RL = 2 kΩ to 10 kΩ±0.29 % FS

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JULY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions (unless otherwise noted)

(continued)

reference input

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIInput voltage range 0 VDD–1.5 V

RIInput resistance 10 MΩ

CIInput capacitance 5 pF

Reference in

ut bandwidth

REF=02V +1024Vdc

Fast 1.3 MHz

Reference input bandwidth REF = 0.2 Vpp + 1.024 V dc Slow 525 kHz

Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IIH High-level digital input current VI = VDD 1µA

IIL Low-level digital input current VI = 0 V –1µA

CiInput capacitance 8 pF

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output settling time full scale

R10kΩC 100 pF See Note 11

Fast 1 3

ts(FS) Output settling time, full scale RL = 10 kΩ,C

L = 100 pF, See Note 11 Slow 3 10 µs

Output settling time code to code

R10kΩC 100 pF See Note 12

Fast 1

ts(CC) Output settling time, code to code RL = 10 kΩ,C

L = 100 pF, See Note 12 Slow 2 µs

Slew rate

R10kΩC 100 pF See Note 13

Fast 3

V/ s

SR Slew rate RL = 10 kΩ,C

L = 100 pF, See Note 13 Slow 0.5 V/µs

Glitch energy DIN = 0 to 1, FCLK = 100 kHz, CS = VDD 5 nV–s

SNR Signal-to-noise ratio 76

SINAD Signal-to-noise + distortion f

= 102 kSPS, f

out

= 1 kHz, R

= 10 kΩ,68

THD Total harmonic distortion

102

kSPS

fout

kHz

kΩ

CL = 100 pF –68 dB

SFDR Spurious free dynamic range

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change

of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JULY 2002

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

digital input timing requirements

MIN NOM MAX UNIT

C and I suffixes

VDD = 5 V 5

tsu

(

CS-CK

)

Setup time, CS low before first negative SCLK edge C and I suffixes VDD = 3 V 10 ns

tsu(CS

CK)

Setu

time,

low

before

first

negative

SCLK

edge

Q and M suffixes 10 ns

tsu(C16-CS) Setup time, 16th negative SCLK edge before CS rising edge 10 ns

tw(H) SCLK pulse width high 25 ns

tw(L) SCLK pulse width low 25 ns

C and I suffixes

VDD = 5 V 5

tsu

(

)

Setup time, data ready before SCLK falling edge C and I suffixes VDD = 3 V 10 ns

tsu(D)

Setu

time,

data

ready

before

SCLK

falling

edge

Q and M suffixes 8

C and I suffixes

VDD = 5 V 5

th(D) Hold time, data held valid after SCLK falling edge C and I suffixes VDD = 3 V 10 ns

h(D)

Q and M suffixes 10

th(CSH)

Hold time CS high between cycles

VDD = 5 V 25

th(CSH) Hold time, CS high between cycles VDD = 3 V 50 ns

timing requirements

tw(L)

SCLK

DIN D15 D14 D13 D12 D1 D0 XX

X2 3 4 5 15 16 X

tw(H)

tsu(D) th(D)

tsu(CS-CK)

tsu(C16-CS)

Figure 1. Timing Diagram

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JULY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 2

2.046

2.044

2.040

2.038

2.036

2.050

2.042

2.048

Load Current – mA

OUTPUT VOLTAGE

LOAD CURRENT

– Output Voltage – V

VDD = 3 V

VREF = 1 V

Full Scale

3 V Slow Mode, SOURCE

3 V Fast Mode, SOURCE

0–0.01 –0.02 –0.5 –0.1 –0.2 –0.5 –1–2–0.8

Figure 3

4.095

4.090

4.080

4.075

4.070

4.105

4.085

4.100

OUTPUT VOLTAGE

LOAD CURRENT

– Output Voltage – V

VDD = 5 V

VREF = 2 V

Full Scale

5 V Slow Mode, SOURCE

5 V Fast Mode, SOURCE

Load Current – mA

0–0.02 –0.04 –0.1 –0.2 –0.4 –1–2–4–0.8

Figure 4

0.16

0.14

0.10

0.08

0.06

0.20

0.12

0.18

Load Current – mA

OUTPUT VOLTAGE

LOAD CURRENT

– Output Voltage – V

3 V Slow Mode, SINK

3 V Fast Mode, SINK

0.04

0.02

0.00

VDD = 3 V

VREF = 1 V

Zero Scale

0 0.01 0.02 0.05 0.1 0.2 0.5 1 20.8

Figure 5

0.25

0.20

0.10

0.05

0.00

0.35

0.15

0.30

Load Current – mA

OUTPUT VOLTAGE

LOAD CURRENT

– Output Voltage – V

5 V Slow Mode, SINK

5 V Fast Mode, SINK

VDD = 5 V

VREF = 2 V

Zero Scale

0 0.02 0.04 0.1 0.2 0.4 1 2 40.8

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JULY 2002

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 6

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

–40 –20 0 20 40 60 80 100 120

SUPPLY CURRENT

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – C

VDD = 3 V

VREF = 1 V

Full Scale Fast Mode

Slow Mode

IDD – Supply Current – mA

Figure 7

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

–40 –20 0 20 40 60 80 100 120

SUPPLY CURRENT

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – C

VDD = 5 V

VREF = 2 V

Full Scale

Fast Mode

Slow Mode

IDD – Supply Current – mA

–90

–80

–70

–60

–50

–40

–30

–20

–10

1 10 100

TOTAL HARMONIC DISTORTION

FREQUENCY

VREF = 1 V + 1 VP/P Sinewave,

Output Full Scale

3 V Fast Mode

5 V Fast Mode

THD – Total Harmonic Distortion – dB

Figure 8

f – Frequency – kHz

–90

–80

–70

–60

–50

–40

–30

–20

–10

1 10 100

TOTAL HARMONIC DISTORTION

FREQUENCY

VREF = 1 V + 1 VP/P Sinewave,

Output Full Scale

5 V Slow Mode

THD – Total Harmonic Distortion – dB

3 V Slow Mode

f – Frequency – kHz

Figure 9

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JULY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0 512 1024 1536 2048 2560 3072 3584 4096

INL – Integral Nonlinearity Error – LSB

INTEGRAL NONLINEARITY ERROR

DIGITAL CODE

Digital Code

Figure 10

Figure 11

–1.00

–0.75

–0.50

–0.25

0.00

0.25

0.50

0.75

1.00

0 4096

Digital Code

DIFFERENTIAL NONLINEARITY ERROR

DIGITAL CODE

20481024 3072

DNL – Differential Nonlinearity Error – LSB

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JULY 2002

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

general function

The TL V5618A is a dual 12-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial

interface, a speed and power down control logic, a resistor string, and a rail-to-rail output buffer.

The output voltage (full scale determined by the reference) is given by:

2REFCODE

2n[V]

Where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n–1, where

n=12 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data

format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).

serial interface

A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling

edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the

target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.

Figure 12 shows examples of how to connect the TLV5618A to TMS320, SPI, and Microwire.

TMS320

DSP FSX

CLKX

TLV5618A

SCLK

DIN

CS SPI I/O

SCK

MOSI

TLV5618A

SCLK

DIN

CS Microwire

I/O

TLV5618A

SCLK

DIN

Figure 12. Three-Wire Interface

Notes on SPI and Microwire: Before the controller starts the data transfer , the software has to generate a falling

edge on the pin connected to CS. If the word width is 8 bits (SPI and Microwire) two write operations must be

performed to program the TLV5618A. After the write operation(s), the holding registers or the control register

are updated automatically on the next positive clock edge following the 16th falling clock edge.

serial clock frequency and update rate

The maximum serial clock frequency is given by:

fsclkmax +1

twhmin )twlmin +20 MHz

The maximum update rate is:

fupdatemax +1

16 ǒtwhmin )twlminǓ+1.25 MHz

Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the

TLV5618A should also be considered.

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JULY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

data format

The 16-bit data word for the TLV5618A consists of two parts:

DProgram bits (D15..D12)

DNew data (D11..D0)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

R1 SPD PWR R0 MSB 12 Data bits LSB

SPD: Speed control bit 1 → fast mode 0 →slow mode

PWR: Power control bit 1 → power down 0 → normal operation

On power up, SPD and PWD are reset to 0 (slow mode and normal operation)

The following table lists all possible combinations of register-select bits:

R1 R0 REGISTER

0 0 Write data to DAC B and BUFFER

0 1 Write data to BUFFER

1 0 Write data to DAC A and update DAC B with BUFFER content

1 1 Reserved

The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,

then the 12 data bits determine the new DAC value:

examples of operation

DSet DAC A output, select fast mode:

Write new DAC A value and update DAC A output:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1100 New DAC A output value

The DAC A output is updated on the rising clock edge after D0 is sampled.

DSet DAC B output, select fast mode:

Write new DAC B value to BUFFER and update DAC B output:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0100 New BUFFER content and DAC B output value

The DAC A output is updated on the rising clock edge after D0 is sampled.

DSet DAC A value, set DAC B value, update both simultaneously, select slow mode:

1. Write data for DAC B to BUFFER:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0001 New DAC B value

2. Write new DAC A value and update DAC A and B simultaneously:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1000 New DAC A value

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

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APPLICATION INFORMATION

examples of operation (continued)

Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.

DSet power-down mode:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

XX1XXXXXXXXXXXXX

X = Don’t care

linearity, offset, and gain error using single ended supplies

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With

a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage

may not change with the first code, depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative

supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage

to overcome the negative offset voltage, resulting in the transfer function shown in Figure 13.

DAC Code

Output

Voltage

0 V

Negative

Offset

Figure 13. Effect of Negative Offset (Single Supply)

This offset error , not the linearity error , produces this breakpoint. The transfer function would have followed the

dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after

offset and full scale are adjusted out or accounted for in some way. However , single supply operation does not

allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity

is measured between full-scale code and the lowest code that produces a positive output voltage.

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230H – JULY 1999 – REVISED JULY 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

definitions of specifications and terminology

integral nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum

deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale

errors.

differential nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the

measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage

changes in the same direction (or remains constant) as a change in the digital input code.

zero-scale error (EZS)

Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.

gain error (EG)

Gain error is the error in slope of the DAC transfer function.

total harmonic distortion (THD)

THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal.

The value for THD is expressed in decibels.

signal-to-noise ratio + distortion (S/N+D)

S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below

the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

spurious free dynamic range (SFDR)

Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of

the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

5962-9955701Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

9955701Q2A

TLV5618

AMFKB

5962-9955701QPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI -55 to 125 9955701QPA

TLV5618AM

TLV5618ACD ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TV5618

TLV5618ACDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TV5618

TLV5618ACDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TV5618

TLV5618ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TV5618

TLV5618ACP ACTIVE PDIP P 8 50 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TLV5618AC

TLV5618ACPE4 ACTIVE PDIP P 8 50 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TLV5618AC

TLV5618AID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TY5618

TLV5618AIDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TY5618

TLV5618AIDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TY5618

TLV5618AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TY5618

TLV5618AIP ACTIVE PDIP P 8 50 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TLV5618AI

TLV5618AIPE4 ACTIVE PDIP P 8 50 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TLV5618AI

TLV5618AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

9955701Q2A

TLV5618

AMFKB

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TLV5618AMJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 TLV5618AMJG

TLV5618AMJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9955701QPA

TLV5618AM

TLV5618AQD ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V5618A

TLV5618AQDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V5618A

TLV5618AQDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 V5618A

TLV5618AQDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V5618A

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 3

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLV5618A, TLV5618AM :

•Catalog: TLV5618A

•Enhanced Product: TLV5618A-EP, TLV5618A-EP

•Military: TLV5618AM

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

•Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TLV5618ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLV5618AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLV5618AQDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLV5618AQDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Mar-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV5618ACDR SOIC D 8 2500 367.0 367.0 35.0

TLV5618AIDR SOIC D 8 2500 367.0 367.0 35.0

TLV5618AQDR SOIC D 8 2500 367.0 367.0 35.0

TLV5618AQDRG4 SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Mar-2013

Pack Materials-Page 2

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.310 (7,87)

0.290 (7,37)

0.014 (0,36)

0.008 (0,20)

Seating Plane

4040107/C 08/96

0.065 (1,65)

0.045 (1,14)

0.020 (0,51) MIN

0.400 (10,16)

0.355 (9,00)

0.015 (0,38)

0.023 (0,58)

0.063 (1,60)

0.015 (0,38)

0.200 (5,08) MAX

0.130 (3,30) MIN

0.245 (6,22)

0.280 (7,11)

0.100 (2,54)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

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