PC BOARD LAYOUT TECHNIQUES FOR
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
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add a pole and/or a zero below 400 MHz that canOPTIMAL PERFORMANCE effect circuit operation. Keep resistor values aslow as possible, consistent with load drivingAchieving optimum performance with a high
considerations.frequency amplifier-like devices in the THS4500
•Connections to other wideband devices on thefamily requires careful attention to board layout
board may be made with short direct traces orparasitic and external component types.
through onboard transmission lines. For shortRecommendations that optimize performance include:
connections, consider the trace and the input tothe next device as a lumped capacitive load.•Minimize parasitic capacitance to any ac ground
Relatively wide traces (50 mils to 100 mils) shouldfor all of the signal I/O pins. Parasitic capacitance
be used, preferably with ground and power planeson the output and input pins can cause instability.
opened up around them. Estimate the totalTo reduce unwanted capacitance, a window
capacitive load and determine if isolation resistorsaround the signal I/O pins should be opened in all
on the outputs are necessary. Low parasiticof the ground and power planes around those
capacitive loads (< 4 pF) may not need an R
Spins. Otherwise, ground and power planes should
since the THS4500 family is nominallybe unbroken elsewhere on the board.
compensated to operate with a 2-pF parasitic•Minimize the distance (< 0.25 ” ) from the
load. Higher parasitic capacitive loads without anpower-supply pins to high-frequency 0.1- µF
R
S
are allowed as the signal gain increasesdecoupling capacitors. At the device pins, the
(increasing the unloaded phase margin). If a longground and power-plane layout should not be in
trace is required, and the 6-dB signal loss intrinsicclose proximity to the signal I/O pins. Avoid
to a doubly-terminated transmission line isnarrow power and ground traces to minimize
acceptable, implement a matched impedanceinductance between the pins and the decoupling
transmission line using microstrip or striplinecapacitors. The power-supply connections should
techniques (consult an ECL design handbook foralways be decoupled with these capacitors.
microstrip and stripline layout techniques).Larger (6.8 µF or more) tantalum decoupling
•A 50- Ωenvironment is normally not necessarycapacitors, effective at lower frequency, should
onboard, and in fact, a higher impedancealso be used on the main supply pins. These may
environment improves distortion as shown in thebe placed somewhat farther from the device and
distortion versus load plots. With a characteristicmay be shared among several devices in the
board trace impedance defined based on boardsame area of the PC board. The primary goal is to
material and trace dimensions, a matching seriesminimize the impedance seen in the
resistor into the trace from the output of thedifferential-current return paths.
THS4500 family is used as well as a terminating•Careful selection and placement of external
shunt resistor at the input of the destinationcomponents preserve the high frequency
device.performance of the THS4500 family. Resistors
•Remember also that the terminating impedance isshould be a very low reactance type.
the parallel combination of the shunt resistor andSurface-mount resistors work best and allow a
the input impedance of the destination device: thistighter overall layout. Metal-film and carbon
total effective impedance should be set to matchcomposition, axially-leaded resistors can also
the trace impedance. If the 6-dB attenuation of aprovide good high frequency performance. Again,
doubly terminated transmission line iskeep their leads and PC board trace length as
unacceptable, a long trace can beshort as possible. Never use wirewound type
series-terminated at the source end only. Treatresistors in a high-frequency application. Since the
the trace as a capacitive load in this case. Thisoutput pin and inverting input pins are the most
does not preserve signal integrity as well as asensitive to parasitic capacitance, always position
doubly-terminated line. If the input impedance ofthe feedback and series output resistors, if any, as
the destination device is low, there is some signalclose as possible to the inverting input pins and
attenuation due to the voltage divider formed byoutput pins. Other network components, such as
the series output into the terminating impedance.input termination resistors, should be placed closeto the gain-setting resistors. Even with a low
•Socketing a high speed part like the THS4500parasitic capacitance shunting the external
family is not recommended. The additional leadresistors, excessively high resistor values can
length and pin-to-pin capacitance introduced bycreate significant time constants that can degrade
the socket can create an extremely troublesomeperformance. Good axial metal-film or
parasitic network which can make it almostsurface-mount resistors have approximately
impossible to achieve a smooth, stable frequency0.2 pF in shunt with the resistor. For resistor
response. Best results are obtained by solderingvalues > 2.0 k Ω, this parasitic capacitance can
the THS4500 family parts directly onto the board.
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