DGK-8DGN-8 D-8
1
FEATURES APPLICATIONS
1
2
3
4
8
7
6
5
VIN− VIN+
VOCM
VS+
VOUT+
PD
VS−
VOUT−
RELATED DEVICESDESCRIPTION
-
+-
+
VOCM 12 Bit/80 MSps
IN
IN
5 V
Vref
5 V
VS
0.1 µF10 µF
499 Ω
8.2 pF
1 µF
53.6 ΩADC
487 Ω
50 Ω
523 Ω
499 Ω
8.2 pF
24.9 Ω
24.9 Ω
THS4504
THS4505
www.ti.com
......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
WIDEBAND, LOW-DISTORTION, FULLY DIFFERENTIAL AMPLIFIERS
•High Linearity Analog-to-Digital Converter23
•Fully Differential Architecture
Preamplifier•Bandwidth: 260 MHz
•Wireless Communication Receiver Chains•Slew Rate: 1800 V/ µs
•Single-Ended to Differential Conversion•IMD
3
: – 73 dBc at 30 MHz
•Differential Line Driver•OIP
3
: 29 dBm at 30 MHz
•Active Filtering of Differential Signals•Output Common-Mode Control•Wide Power-Supply Voltage Range: 5 V, ± 5 V,12 V, 15 V•Input Common-Mode Range Shifted to Includethe Negative Power-Supply Rail•Power-Down Capability (THS4504)•Evaluation Module Available
DEVICE
(1)
DESCRIPTIONThe THS4504 and THS4505 are high-performance,fully differential amplifiers from Texas Instruments.
THS4504/5 260 MHz, 1800 V/ µs, V
ICR
Includes V
S –The THS4504, featuring power-down capability, and
THS4500/1 370 MHz, 2800 V/ µs, V
ICR
Includes V
S –the THS4505, without power-down capability, set new
THS4502/3 370 MHz, 2800 V/ µs, Centered V
ICRperformance standards for fully differential amplifiers
THS4120/1 3.3 V, 100 MHz, 43 V/ µs, 3.7 nV/ √Hzwith unsurpassed linearity, supporting 12-bit
THS4130/1 15 V, 150 MHz, 51 V/ µs, 1.3 nV/ √Hzoperation through 40 MHz. Package options includethe SOIC-8 and the MSOP-8 with PowerPAD™ for a
THS4140/1 15 V, 160 MHz, 450 V/ µs, 6.5 nV/ √Hzsmaller footprint, enhanced ac performance, and
THS4150/1 15 V, 150 MHz, 650 V/ µs, 7.6 nV/ √Hzimproved thermal dissipation capability.
(1) Even numbered devices feature power-down capability
APPLICATION CIRCUIT DIAGRAM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments, Incorporated.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
PACKAGE DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
Over operating free-air temperature range, unless otherwise noted.
UNIT
Supply voltage, V
S
16.5 VInput voltage, V
I
± V
S
Output current, I
O
150 mADifferential input voltage, V
ID
4 VContinuous power dissipation See Package Dissipation Ratings tableMaximum junction temperature, T
J
+150 °CMaximum junction temperature, continuous operation, long-term reliability, T
J
(2)
+125 °CStorage temperature range, T
stg
– 65 °C to +150 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds +300 °C
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings maycause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature mayresult in reduced reliability and/or lifetime of the device.
POWER RATING
(2)PACKAGE θ
JC
(°C/W) θ
JA
(°C/W)
(1)
T
A
≤+25 °C T
A
= +85 °C
D (8-pin) 38.3 97.5 1.02 W 410 mWDGN (8-pin) 4.7 58.4 1.71 W 685 mWDGK (8-pin) 54.2 260 385 mW 154 mW
(1) This data was taken using the JEDEC standard High-K test PCB.(2) Power rating is determined with a junction temperature of +125 °C. This is the point where distortion starts to substantially increase.Thermal management of the final PCB should strive to keep the junction temperature at or below +125 °C for best performance and longterm reliability.
MIN NOM MAX UNIT
Dual supply ± 5 ± 7.5Supply voltage VSingle supply 4.5 5 15Operating free-air temperature, T
A
– 40 +85 °C
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Product Folder Link(s): THS4504 THS4505
PIN ASSIGNMENTS
THS4505
(TOPVIEW)
VIN- 1
2
3
4
8
7
6
5
VOCM
VS+
VOUT+
VIN+
VS-
VOUT-
PD
D,DGK,ANDDGN
THS4504
(TOPVIEW)
D,DGK,ANDDGN
VIN- 1
2
3
4
8
7
6
5
VOCM
VS+
VOUT+
VIN+
VS-
VOUT-
NC
NC=NoInternalConnectionSeeNote A.
THS4504
THS4505
www.ti.com
......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
ORDERING INFORMATION
(1)
PACKAGED DEVICES PACKAGE TYPE PACKAGE MARKINGS TRANSPORT MEDIA, QUANTITY
Power-down
THS4504D Rails, 75SOIC-8 —THS4504DR Tape and Reel, 2500THS4504DGK Rails, 100MSOP-8 ASZTHS4504DGKR Tape and Reel, 2500THS4504DGN Rails, 80MSOP-8-PP
(2)
BDBTHS4504DGNR Tape and Reel, 2500Non-power-down
THS4505D Rails, 75SOIC-8 —THS4505DR Tape and Reel, 2500THS4505DGK Rails, 100MSOP-8 ATATHS4505DGKR Tape and Reel, 2500THS4505DGN Rails, 80MSOP-8-PP
(2)
BDCTHS4505DGNR Tape and Reel, 2500
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) The PowerPAD is electrically isolated from all other pins.
A. The devices with the power-down option default to the ON state if no signal is applied to the PD pin.
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): THS4504 THS4505
ELECTRICAL CHARACTERISTICS: V
S
= ± 5 V
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
www.ti.com
V
S
= ± 5 V, R
F
= R
G
= 499 Ω, R
L
= 800 Ω, G = +1, and single-ended input, unless otherwise noted.
THS4504 AND THS4505
TYP OVER TEMPERATURE
MIN/PARAMETER TEST CONDITIONS
TYP/0°C to – 40 °C to+25 °C +25 °C UNIT
MAX+70 °C +85 °C
AC PERFORMANCE
G = 1, P
IN
= – 20 dBm,
260 MHz TypR
F
= 499 Ω
G = 2, P
IN
= – 20 dBm,
110 MHz TypR
F
= 499 ΩSmall-signal bandwidth
G = 5, P
IN
= – 20 dBm,
40 MHz TypR
F
= 499 Ω
G = 10, P
IN
= – 20 dBm,
20 MHz TypR
F
= 499 Ω
Gain-bandwidth product G > +10 210 MHz TypBandwidth for 0.1-dB flatness P
IN
= – 20 dBm 65 MHz TypLarge-signal bandwidth G = 1, V
P
= 2 V 250 MHz TypSlew rate 4 V
PP
Step 1800 V/ µs TypRise time 2 V
PP
Step 0.8 ns TypFall time 2 V
PP
Step 1 ns TypSettling time to 0.01% V
O
= 4 V
PP
100 ns Typ0.1% V
O
= 4 V
PP
20 ns TypHarmonic distortion G = 1, V
O
= 2 V
PP
Typf = 8 MHz – 79 dBc Typ2nd harmonic
f = 30 MHz – 66 dBc Typf = 8 MHz – 93 dBc Typ3rd harmonic
f = 30 MHz – 65 dBc TypV
O
= 2 V
PP
, f
C
= 30 MHz,Third-order intermodulation
R
F
= 499 Ω, – 73 dBc Typdistortion
200 kHz tone spacingf
C
= 30 MHz, R
f
= 499 Ω,Third-order output intercept point 29 dBm TypReferenced to 50 Ω
Input voltage noise f > 1 MHz 8 nV/ √Hz TypInput current noise f > 100 kHz 2 pA/ √Hz TypOverdrive recovery time Overdrive = 5.5 V 60 ns Typ
DC PERFORMANCE
Open-loop voltage gain 55 52 50 50 dB MinInput offset voltage – 4 – 7/ – 1 – 8/0 – 9/+1 mV MaxAverage offset voltage drift ± 10 ± 10 µV/ °C TypInput bias current 4 4.6 5 5.2 µA MaxAverage bias current drift ± 10 ± 10 nA/ °C TypInput offset current 0.5 1 2 2 µA MaxAverage offset current drift ± 40 ± 40 nA/ °C Typ
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Product Folder Link(s): THS4504 THS4505
THS4504
THS4505
www.ti.com
......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: V
S
= ± 5 V (continued)V
S
= ± 5 V, R
F
= R
G
= 499 Ω, R
L
= 800 Ω, G = +1, and single-ended input, unless otherwise noted.
THS4504 AND THS4505
TYP OVER TEMPERATURE
MIN/PARAMETER TEST CONDITIONS
TYP/0°C to – 40 °C to+25 °C +25 °C UNIT
MAX+70 °C +85 °C
INPUT
Common-mode input range – 5.7/2.6 – 5.4/2.3 – 5.1/2 – 5.1/2 V MinCommon-mode rejection ratio 80 74 70 70 dB MinInput impedance 10
7
|| 1 Ω|| pF Typ
OUTPUT
Differential output voltage swing R
L
= 1 k Ω± 8 ± 7.6 ± 7.4 ± 7.4 V MinDifferential output current drive R
L
= 20 Ω130 110 100 100 mA MinOutput balance error P
IN
= – 20 dBm, f = 100 kHz – 65 dB TypClosed-loop output impedance
f = 1 MHz 0.1 ΩTyp(single-ended)
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth R
L
= 400 Ω200 MHz TypSlew rate 2 V
PP
Step 92 V/ µs TypMinimum gain 1 0.98 0.98 0.98 V/V MinMaximum gain 1 1.02 1.02 1.02 V/V MaxCommon-mode offset voltage – 0.4 – 4.6/+3.8 – 6.6/+5.8 – 7.6/+6.8 mV MaxInput bias current V
OCM
= 2.5 V 100 150 170 170 µA MaxInput voltage range ± 4 ± 3.7 ± 3.4 ± 3.4 V MinInput impedance 25 || 1 k Ω|| pF TypMaximum default voltage V
OCM
left floating 0 0.05 0.10 0.10 V MaxMinimum default voltage V
OCM
left floating 0 – 0.05 – 0.10 – 0.10 V Min
POWER SUPPLY
Specified operating voltage ± 5 ± 7.5 ± 7.5 ± 7.5 V MaxMaximum quiescent current 16 20 23 25 mA MaxMinimum quiescent current 16 13 11 9 mA MinPower-supply rejection ( ± PSRR) 80 76 73 70 dB Min
POWER-DOWN (THS4504 ONLY)
Enable voltage threshold Device enabled ON above – 2.9 V – 2.9 V MinDevice disabled OFF belowDisable voltage threshold – 4.3 V Max– 4.3 VPower-down quiescent current 800 1000 1200 1200 µA MaxInput bias current 200 240 260 260 µA MaxInput impedance 50 || 1 k Ω|| pF TypTurn-on time delay 1000 ns TypTurn-off time delay 800 ns Typ
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): THS4504 THS4505
ELECTRICAL CHARACTERISTICS: V
S
= 5 V
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
www.ti.com
V
S
= 5 V, R
F
= R
G
= 499 Ω, R
L
= 800 Ω, G = +1, and single-ended input, unless otherwise noted.
THS4504 AND THS4505
TYP OVER TEMPERATUREPARAMETER TEST CONDITIONS
MIN/TYP/– 40 °C0°C to
MAX+25 °C +25 °C to UNIT+70 °C
+85 °C
AC PERFORMANCE
G = 1, P
IN
= – 20 dBm, R
F
= 499 Ω210 MHz TypG = 2, P
IN
= – 20 dBm, R
F
= 499 Ω120 MHz TypSmall-signal bandwidth
G = 5, P
IN
= – 20 dBm, R
F
= 499 Ω40 MHz TypG = 10, P
IN
= – 20 dBm, R
F
= 499 Ω20 MHz TypGain-bandwidth product G > +10 200 MHz TypBandwidth for 0.1-dB
P
IN
= – 20 dBm 100 MHz Typflatness
Large-signal bandwidth G = 1, V
P
= 1 V 200 MHz TypSlew rate 2 V
PP
Step 900 V/ µs TypRise time 2 V
PP
Step 1.1 ns TypFall time 2 V
PP
Step 1 ns TypSettling time to 0.01% V
O
= 2 V Step 100 ns Typ0.1% V
O
= 2 V Step 20 ns TypHarmonic distortion G = 1, V
O
= 2 V
PP
Typf = 8 MHz, – 77 dBc Typ2nd harmonic
f = 30 MHz – 56 dBc Typf = 8 MHz – 74 dBc Typ3rd harmonic
f = 30 MHz – 57 dBc TypV
O
= 2 V
PP
, f
C
= 30 MHz,Third-order intermodulation
R
F
= 499 Ω, – 72 dBc Typdistortion
200 kHz tone spacingThird-order output f
C
= 30 MHz, R
F
= 499 Ω,
28 dBm Typintercept point Referenced to 50 Ω
Input voltage noise f > 1 MHz 8 nV/ √Hz TypInput current noise f > 100 kHz 2 pA/ √Hz TypOverdrive recovery time Overdrive = 5.5 V 60 ns Typ
DC PERFORMANCE
Open-loop voltage gain 54 51 49 49 dB MinInput offset voltage – 4 – 7/ – 1 – 8/0 – 9/+1 mV MaxAverage offset voltage drift ± 10 ± 10 µV/ °C TypInput bias current 4 4.6 5 5.2 µA MaxAverage bias current drift ± 10 ± 10 nA/ °C TypInput offset current 0.5 0.7 1.2 1.2 µA MaxAverage offset current drift ± 20 ± 20 nA/ °C Typ
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Product Folder Link(s): THS4504 THS4505
THS4504
THS4505
www.ti.com
......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: V
S
= 5 V (continued)V
S
= 5 V, R
F
= R
G
= 499 Ω, R
L
= 800 Ω, G = +1, and single-ended input, unless otherwise noted.
THS4504 AND THS4505
TYP OVER TEMPERATUREPARAMETER TEST CONDITIONS
MIN/TYP/– 40 °C0°C to
MAX+25 °C +25 °C to UNIT+70 °C
+85 °C
INPUT
Common-mode input range – 0.7/2.6 – 0.4/2.3 – 0.1/2 – 0.1/2 V MinCommon-mode rejection ratio 80 74 70 70 dB MinInput impedance 10
7
|| 1 Ω|| pF Typ
OUTPUT
Differential output voltage swing R
L
= 1 k Ω, Referenced to 2.5 V ± 3.3 ± 3 ± 2.8 ± 2.8 V MinOutput current drive R
L
= 20 Ω110 90 80 80 mA MinOutput balance error P
IN
= – 20 dBm, f = 100 kHz – 38 dB TypClosed-loop output
f = 1 MHz 0.1 ΩTypimpedance (single-ended)
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth R
L
= 400 Ω160 MHz TypSlew rate 2 V
PP
Step 80 V/ µs TypMinimum gain 1 0.98 0.98 0.98 V/V MinMaximum gain 1 1.02 1.02 1.02 V/V MaxCommon-mode offset
0.4 – 2.6/3.4 – 4.2/5.4 – 5.6/6.4 mV Maxvoltage
Input bias current V
OCM
= 2.5 V 1 2 3 3 µA MaxInput voltage range 1/4 1.2/3.8 1.3/3.7 1.3/3.7 V MinInput impedance 25 || 1 k Ω|| pF TypMaximum default voltage V
OCM
left floating 2.5 2.55 2.6 2.6 V MaxMinimum default voltage V
OCM
left floating 2.5 2.45 2.4 2.4 V Min
POWER SUPPLY
Specified operating voltage 5 15 15 15 V MaxMaximum quiescent current 14 17 19 21 mA MaxMinimum quiescent current 14 11 10 8 mA MinPower-supply rejection (+PSRR) 75 72 69 66 dB Min
POWER-DOWN (THS4504 ONLY)
Enable voltage threshold Device enabled ON above 2.1 V 2.1 V MinDevice disabled OFF belowDisable voltage threshold 0.7 V Max0.7 VPower-down quiescent
600 800 1200 1200 µA Maxcurrent
Input bias current 100 125 140 140 µA MaxInput impedance 50 || 1 k Ω|| pF TypTurn-on time delay 1000 ns TypTurn-off time delay 800 ns Typ
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): THS4504 THS4505
TYPICAL CHARACTERISTICS
Table of Graphs ( ± 5 V)
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
www.ti.com
FIGURE
Small-signal unity-gain frequency response 1Small-signal frequency response 20.1-dB gain flatness frequency response 3Large-signal frequency response 4Harmonic distortion (single-ended input to differential output) vs Frequency 5Harmonic distortion (single-ended input to differential output) vs Output voltage swing 6, 7Harmonic distortion (single-ended input to differential output) vs Load resistance 8Third order intermodulation distortion (single-ended input to differential output) vs Frequency 9Third order output intercept point vs Frequency 10Slew rate vs Differential output voltage step 11Settling time 12, 13Large-signal transient response 14Small-signal transient response 15Overdrive recovery 16, 17Voltage and current noise vs Frequency 18Rejection ratios vs Frequency 19Rejection ratios vs Case temperature 20Output balance error vs Frequency 21Open-loop gain and phase vs Frequency 22Open-loop gain vs Case temperature 23Input bias offset current vs Case temperature 24Quiescent current vs Supply voltage 25Input offset voltage vs Case temperature 26Common-mode rejection ratio vs Input common-mode range 27Output voltage vs Load resistance 28Closed-loop output impedance vs Frequency 29Harmonic distortion (single-ended and differential input to differential output) vs Output common-mode voltage 30Small-signal frequency response at V
OCM
31Output offset voltage at V
OCM
vs Output common-mode voltage 32Quiescent current vs Power-down voltage 33Turn-on and turn-off delay times 34Single-ended output impedance in power-down vs Frequency 35Power-down quiescent current vs Case temperature 36Power-down quiescent current vs Supply voltage 37
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Product Folder Link(s): THS4504 THS4505
Table of Graphs (5 V)
THS4504
THS4505
www.ti.com
......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
FIGURE
Smal-signal unity-gain frequency response 38Small-signal frequency response 390.1-dB gain flatness frequency response 40Large signal frequency response 41Harmonic distortion (single-ended input to differential output) vs Frequency 42Harmonic distortion (single-ended input to differential output) vs Output voltage swing 43, 44Harmonic distortion (single-ended input to differential output) vs Load resistance 45Third-order intermodulation distortion vs Frequency 46Third-order intercept point vs Frequency 47Slew rate vs Differential output voltage step 48Settling time 49, 50Overdrive recovery 51, 52Large-signal transient response 53Small-signal transient response 54Voltage and current noise vs Frequency 55Rejection ratios vs Frequency 56Rejection ratios vs Case temperature 57Output balance error vs Frequency 58Open-loop gain and phase vs Frequency 59Open-loop gain vs Case temperature 60Input bias offset current vs Case temperature 61Quiescent current vs Supply voltage 62Input offset voltage vs Case temperature 63Common-mode rejection ratio vs Input common-mode range 64Output voltage vs Load resistance 65Closed-loop output impedance vs Frequency 66Harmonic distortion (single-ended and differential input) vs Output common-mode voltage 67Small-signal frequency response at V
OCM
68Output offset voltage vs Output common-mode voltage 69Quiescent current vs Power-down voltage 70Turn-on and turn-off delay times 71Single-ended output impedance in power-down vs Frequency 72Power-down quiescent current vs Case temperature 73Power-down quiescent current vs Supply voltage 74
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): THS4504 THS4505
TYPICAL CHARACTERISTICS: ± 5 V
−4
−3.5
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
0.1 1 10 100 1000
f − Frequency − MHz
Small Signal Unity Gain − dB
Gain = 1
RL = 800 Ω
Rf = 499 Ω
PIN = −20 dBm
VS = ±5 V
−2
0
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000
f − Frequency − MHz
Small Signal Gain − dB
Gain = 10
Gain = 5
Gain = 2
RL = 800 Ω
Rf =499 Ω
PIN = −20 dBm
VS = ±5 V
110 100 1000
Rf = 499 Ω
f − Frequency − MHz
0.1 dB Gain Flatness − dB
−0.3
−0.25
−0.2
−0.15
−0.1
−0.05
0
0.05
Gain = 1
RL = 800 Ω
PIN = −20 dBm
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
0.1 1 10 100 1000
f − Frequency − MHz
Large Signal Gain − dB
RL = 800 Ω
VO = 2 VPP
VS = ±5 V
−5
0
5
10
15
20
25
Gain = 10, Rf = 1.8 kΩ
Gain = 5, Rf = 1.8 kΩ
Gain = 2, Rf = 1.8 kΩ
Gain = 1, Rf = 499 Ω
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Single Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 30 MHz
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 400 800 1200 1600
Harmonic Distortion − dBc
RL − Load Resistance − Ω
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
VS = ±5 V
HD3, 8 MHz
HD3, 30 MHz HD2, 30 MHz
HD2, 8 MHz
−100
−90
−80
−70
−60
−50
10 100
Third-Order Intermodulation Distortion − dBc
f − Frequency − MHz
−40
−30 Single-Ended Input to
Differential Output
VO = 2 VPP
VO = 1 VPP
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VS = ±5 V
200 kHz Tone Spacing
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
www.ti.com
SMALL-SIGNAL UNITY-GAIN SMALL-SIGNAL FREQUENCY 0.1-dB GAIN FLATNESSFREQUENCY RESPONSE FREQUENCY RESPONSE
Figure 1. Figure 2. Figure 3.
HARMONIC DISTORTION HARMONIC DISTORTIONLARGE-SIGNAL FREQUENCY vs vsRESPONSE FREQUENCY OUTPUT VOLTAGE SWING
Figure 4. Figure 5. Figure 6.
THIRD-ORDER INTERMODULATIONHARMONIC DISTORTION HARMONIC DISTORTION DISTORTIONvs vs vsOUTPUT VOLTAGE SWING LOAD RESISTANCE FREQUENCY
Figure 7. Figure 8. Figure 9.
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Product Folder Link(s): THS4504 THS4505
10
20
30
40
50
60
0 20 40 60 80 100
OIP Third-OrderOutputInterceptPoint dBm- -
3
f Frequency MHz- -
200 kHz Tone Spacing
0
Normalized to 50 W
RL= 800 W
Normalized to 200 W
Gain W
±
=1,R =499
V =2V V = 5V
200kHzToneSpacing
F
O PP S
,
−3
−2
−1
0
1
2
3
0 5 10 15 20 25 30 35 40
t − Time − ns
− Output Voltage − VVO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = ±5 V
Rising Edge
Falling Edge
−100 0 100 200 300 400 500
t − Time − ns
− Output Voltage − VVO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
−100 0 100 200 300 400 500
t − Time − ns
− Output Voltage − VVO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
t − Time − µs
0
−1
−4
0 0.1 0.2 0.3 0.4 0.5 0.6
Single-Ended Output Voltage − V
1
2
4
0.7 0.8 0.9 1
3
−3
−5
−2
5
0
−0.5
−2
0.5
1
2
1.5
−1.5
−2.5
−1
2.5
− Input Voltage − VVI
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 4.5 V
VS = ±5 V
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 −3
−2
−1
0
1
2
3
t − Time − µs
Single-Ended Output Voltage − V
− Input Voltage − VVI
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 5.5 V
VS = ±5 V
1
10
100
0.01 0.1 1 10 100
Vn
In
f − Frequency − kHz
− Voltage Noise − nV/ Hz
Vn
− Current Noise − pA/ Hz
In
1000 10 k
THS4504
THS4505
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......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
TYPICAL CHARACTERISTICS: ± 5 V (continued)
THIRD-ORDER OUTPUT INTERCEPT SLEW RATEPOINT vsvs DIFFERENTIAL OUTPUT VOLTAGEFREQUENCY STEP SETTLING TIME
Figure 10. Figure 11. Figure 12.
LARGE-SIGNAL TRANSIENT SMALL-SIGNAL TRANSIENTSETTLING TIME RESPONSE RESPONSE
Figure 13. Figure 14. Figure 15.
VOLTAGE AND CURRENT NOISEvsOVERDRIVE RECOVERY OVERDRIVE RECOVERY FREQUENCY
Figure 16. Figure 17. Figure 18.
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
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−10
0
10
20
30
40
50
60
70
80
90
0.1 1 10 100
Rejection Ratios − dB
f − Frequency − MHz
PSRR+
PSRR− CMMR
RL = 800 Ω
VS = ±5 V
0
20
40
60
80
100
120
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Rejection Ratios − dB
Case Temperature − °C
PSRR+
CMMR
RL = 800 Ω
VS = ±5 V
0.1 1 10 100
Output Balance Error − dB
f − Frequency − MHz
PIN = 16 dBm
RL = 800 Ω
Rf = 499 Ω
VS = ±5 V
−80
−70
−60
−50
−40
−30
−20
−10
0
10
−40−30−20−100 10 20 30 40 50 60 70 80 90
− Input Bias Current −
VS = ±5 V
− Input Offset Current −
IIB Aµ
IOS Aµ
IIB+
IOS
Case Temperature − °C
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
−0.09
−0.08
−0.07
−0.06
−0.05
−0.04
−0.03
−0.02
−0.01
0
IIB−
58
49
50
51
52
53
54
55
56
57
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Open-Loop Gain − dB
Case Temperature − °C
RL = 800 Ω
VS = ±5 V
0
10
20
30
40
50
60
0.01 0.1 1 10 100 1000
−150
−120
−90
−60
−30
0
30
Open-Loop Gain − dB
f − Frequency − MHz
PIN = −30 dBm
RL = 800 Ω
VS = ±5 V
Phase −
Gain
Phase
°
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
− Input Offset Voltage − mV
VOS
VS = ±5 V
0
1
2
3
4
5
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
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TYPICAL CHARACTERISTICS: ± 5 V (continued)
REJECTION RATIOS REJECTION RATIOS OUTPUT BALANCE ERRORvs vs vsFREQUENCY CASE TEMPERATURE FREQUENCY
Figure 19. Figure 20. Figure 21.
INPUT BIAS AND OFFSETOPEN-LOOP GAIN AND PHASE OPEN-LOOP GAIN CURRENTvs vs vsFREQUENCY CASE TEMPERATURE CASE TEMPERATURE
Figure 22. Figure 23. Figure 24.
QUIESCENT CURRENT INPUT OFFSET VOLTAGE COMMON-MODE REJECTION RATIOvs vs vsSUPPLY VOLTAGE CASE TEMPERATURE INPUT COMMON-MODE RANGE
Figure 25. Figure 26. Figure 27.
12 Submit Documentation Feedback Copyright © 2002 – 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
−5
−4
−3
−2
−1
0
1
2
3
4
5
10 100 1000 10000
RL − Load Resistance − Ω
− Output Voltage − VVO
VS = ±5 V
TA = −40 to 85°C
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Harmonic Distortion − dBc
VOCM − Output Common-Mode Voltage − V
Single-Ended to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
VS = ±5 V
HD3, 30 MHz
−3.5 −2.5 −1.5 −0.5 0.5 1.5 2.5 3.5
HD2, 30 MHz
HD2, 8 MHz
HD2, 3 MHz
0.1
1
10
100
0.1 1 10 100
f − Frequency − MHz
− Closed Loop Output Impedance −
ZOΩ
Gain = 1
RL = 400 Ω
Rf = 499 Ω
VI = −4 dBm
VS = ±5 V
−5
0
5
10
15
20
25
30
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0
Power-Down Voltage − V
Quiescent Current − mA
−600
−400
−200
0
200
400
600
−5 −4 −3 −2 −1 0 1 2 3 4 5
VOC − Output Common-Mode Voltage − V
− Output Offset Voltage − mV
VOS
−3
−2
−1
0
1
2
3
1 10 100 1000
f − Frequency − MHz
Gain = 1
RL = 400 Ω
Rf = 499 Ω
PIN= −20 dBm
VS = ±5 V
Small Signal Frequency Response at VOCM− dB
0.1 1 10 100 1000
− Single-Ended Output Impedance
ZOin Powerdown −
f − Frequency − MHz
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VI = −1 dBm
VS = ±5 V
Ω
0
300
600
900
1200
1500
−1
−2
−5
0 0.5 1 2
0
100.5101 102 103
−3
−6
−4
0
0.01
0.03
0.02
t − Time − ms
Powerdown Voltage Signal − V
Quiescent Current − mA
1.5 2.5 3
Current
THS4504
THS4505
www.ti.com
......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
TYPICAL CHARACTERISTICS: ± 5 V (continued)
CLOSED-LOOP OUTPUT HARMONIC DISTORTIONOUTPUT VOLTAGE IMPEDANCE vsvs vs OUTPUT COMMON-MODELOAD RESISTANCE FREQUENCY VOLTAGE
Figure 28. Figure 29. Figure 30.
OUTPUT OFFSET VOLTAGE AT V
OCMvs QUIESCENT CURRENTSMALL-SIGNAL FREQUENCY OUTPUT COMMON-MODE vsRESPONSE AT V
OCM
VOLTAGE POWER-DOWN VOLTAGE
Figure 31. Figure 32. Figure 33.
SINGLE-ENDED OUTPUT IMPEDANCEIN POWER-DOWNTURN-ON AND vsTURN-OFF DELAY TIME FREQUENCY
Figure 34. Figure 35.
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): THS4504 THS4505
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Power-Down Quiescent Current −
Case Temperature − °C
RL = 800 Ω
VS = ±5 V
0
100
200
300
400
500
600
700
800
900
1000
Aµ
TYPICAL CHARACTERISTICS: 5 V
−4
−3
−2
−1
0
1
0.1 1 10 100 1000
f − Frequency − MHz
Gain = 1
RL = 800 Ω
Rf = 499 Ω
PIN = −20 dBm
VS = 5 V
Small Signal Unity Gain − dB
110 100 1000
Rf = 499 Ω
f − Frequency − MHz
0.1 dB Gain Flatness − dB
Gain = 1
RL = 800 Ω
PIN = −20 dBm
VS = 5 V
−0.3
−0.25
−0.2
−0.15
−0.1
−0.05
0
0.05
−2
0
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000
f − Frequency − MHz
Small Signal Gain − dB
Gain = 10
Gain = 5
Gain = 2
RL = 800 Ω
Rf = 499 Ω
PIN = −20 dBm
VS = 5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
HD3
HD2
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = 5 V
00 0.5 1 1.5 2 2.5 3 3.5 4
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
0.1 1 10 100 1000
f − Frequency − MHz
RL = 800 Ω
VO = 2 VPP
VS = 5 V
−5
0
5
10
15
20
25
Gain = 10, Rf = 1.8 kΩ
Gain = 5, Rf = 1.8 kΩ
Gain = 2, Rf = 1.8 kΩ
Gain = 1, Rf = 1.8 kΩ
Large Signal Gain − dB
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
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TYPICAL CHARACTERISTICS: ± 5 V (continued)
POWER-DOWN QUIESCENT CURRENT POWER-DOWN QUIESCENT CURRENTvs vsCASE TEMPERATURE SUPPLY VOLTAGE
Figure 36. Figure 37.
SMALL-SIGNAL UNITY-GAIN SMALL-SIGNAL FREQUENCY 0.1-dB GAIN FLATNESSFREQUENCY RESPONSE RESPONSE FREQUENCY RESPONSE
Figure 38. Figure 39. Figure 40.
HARMONIC DISTORTION HARMONIC DISTORTIONLARGE-SIGNAL FREQUENCY vs vsRESPONSE OUTPUT VOLTAGE SWING FREQUENCY
Figure 41. Figure 42. Figure 43.
14 Submit Documentation Feedback Copyright © 2002 – 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 30 MHz
VS = 5 V
0 0.5 1 1.5 2 2.5 3 3.5 4
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 400 800 1200 1600
Harmonic Distortion − dBc
RL − Load Resistance − Ω
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
VS = ±5 V
HD3, 30 MHz
HD3, 8 MHz HD2, 8 MHz
HD2, 30 MHz
−100
−90
−80
−70
−60
−50
10 100
Third-Order Intermodulation Distortion − dBc
f − Frequency − MHz
−40
−30 Single-Ended Input to
Differential Output
VO = 2 VPP
VO = 1 VPP
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VS = 5 V
200 kHz Tone Spacing
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
t Time ns- -
V OutputVoltage V-- O
Gain=1
R =800
R =499
f=1MHz
V =5V
L
F
S
W
W
Rising Edge
Falling Edge
05 10 15 20 25 30
10
20
30
40
50
60
0 20 40 60 80 100
f − Frequency − MHz
0
Normalized to 50 Ω
Gain = 1
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
200 kHz Tone Spacing
RL = 800 Ω
OIP − Third-Order Output Intersept Point − dBm
3
Normalized to 200 Ω
−3
−2
−1
0
1
2
3
0 5 10 15 20 25 30 35 40
t − Time − ns
− Output Voltage − VVO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = 5 V
Rising Edge
Falling Edge
t − Time − µs
0
−1
−4
0 0.1 0.2 0.3 0.4 0.5 0.6
Single-Ended Output Voltage − V
1
2
4
0.7 0.8 0.9 1
3
−3
−5
−2
5
0
−0.5
−2
0.5
1
2
1.5
−1.5
−2.5
−1
2.5
− Input Voltage − VVI
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 4.5 V
VS = ±5 V
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 −3
−2
−1
0
1
2
3
t − Time − µs
Single-Ended Output Voltage − V
− Input Voltage − VVI
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 5.5 V
VS = ±5 V
THS4504
THS4505
www.ti.com
......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
TYPICAL CHARACTERISTICS: 5 V (continued)
THIRD-ORDER INTERMODULATIONHARMONIC DISTORTION HARMONIC DISTORTION DISTORTIONvs vs vsOUTPUT VOLTAGE SWING LOAD RESISTANCE FREQUENCY
Figure 44. Figure 45. Figure 46.
THIRD-ORDER OUTPUT INTERCEPT SLEW RATEPOINT vsvs DIFFERENTIAL OUTPUT VOLTAGEFREQUENCY STEP SETTLING TIME
Figure 47. Figure 48. Figure 49.
SETTLING TIME OVERDRIVE RECOVERY OVERDRIVE RECOVERY
Figure 50. Figure 51. Figure 52.
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
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−100 0 100 200 300 400 500
t − Time − ns
− Output Voltage − VVO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
−100 0 100 200 300 400 500
t − Time − ns
− Output Voltage − VVO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
1
10
100
0.01 0.1 1 10 100
Vn
In
f − Frequency − kHz
− Voltage Noise − nV/ Hz
Vn
− Current Noise − pA/ Hz
In
1000 10 k
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Rejection Ratios − dB
Case Temperature − °C
PSRR+
PSRR−
CMMR
RL = 800 Ω
VS = 5 V
0
20
40
60
80
100
120
−10
0
10
20
30
40
50
60
70
80
90
0.1 1 10 100
Rejection Ratios − dB
f − Frequency − MHz
PSRR+
PSRR− CMMR
RL = 800 Ω
VS = 5 V
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
Output Balance Error − dB
f − Frequency − MHz
PIN = 16 dBm
RL = 800 Ω
Rf = 499 Ω
VS = 5 V
-40
-30
-20-10 0 10 20 30 40 50 60 70 80 90
Case Temperature C- °
VS= 5 V
IIB-
IIB InputBiasCurrent A
-- m
I InputOffsetCurrent - m
OS-A
IIB+
IOS
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
−40−30−20−100 10 20 30 40 50 60 70 80 90
Open-Loop Gain − dB
Case Temperature − °C
RL = 800 Ω
VS = 5 V
46
47
48
49
50
51
52
53
54
55
56
57
0
10
20
30
40
50
60
0.01 0.1 1 10 100 1000
−150
−120
−90
−60
−30
0
30
Open-Loop Gain − dB
f − Frequency − MHz
PIN = −30 dBm
RL = 800 Ω
VS = 5 V
Gain
Phase
Phase − °
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
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TYPICAL CHARACTERISTICS: 5 V (continued)
VOLTAGE AND CURRENT NOISELARGE-SIGNAL TRANSIENT SMALL-SIGNAL TRANSIENT vsRESPONSE RESPONSE FREQUENCY
Figure 53. Figure 54. Figure 55.
REJECTION RATIOS REJECTION RATIOS OUTPUT BALANCE ERRORvs vs vsFREQUENCY CASE TEMPERATURE FREQUENCY
Figure 56. Figure 57. Figure 58.
INPUT BIAS AND OFFSETOPEN-LOOP GAIN AND PHASE OPEN-LOOP GAIN CURRENTvs vs vsFREQUENCY CASE TEMPERATURE CASE TEMPERATURE
Figure 59. Figure 60. Figure 61.
16 Submit Documentation Feedback Copyright © 2002 – 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
− Input Offset Voltage − mV
VOS
VS = 5 V
0
1
2
3
4
5
−5
−4
−3
−2
−1
0
1
2
3
4
5
10 100 1000 10000
RL − Load Resistance − Ω
− Output Voltage − VVO
VS = ±5 V
TA = −40 to 85°C
−80
−70
−60
−50
−40
−30
−20
−10
0
VOC − Output Common-Mode Voltage − V
Harmonic Distortion − dBc
Single-Ended to
Differential Output
Gain = 1, VO = 2 VPP
Rf = 499 Ω, VS = 5 V
11.5 22.5 33.5 4
HD3, 30 MHz
HD2, 30 MHz
HD3, 8 MHz
HD2,
8 MHz
0.1
1
10
100
0.1 1 10 100
f − Frequency − MHz
− Closed Loop Output Impedance −
ZOΩ
Gain = 1
RL = 400 Ω
Rf = 499 Ω
VIN = −4 dBm
VS = 5 V
0
5
10
15
20
25
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Power-down Voltage − V
Quiescent Current − mA
VS = 5 V
−800
−600
−400
−200
0
200
400
600
800
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOC − Output Common-Mode Voltage − V
− Output Offset Voltage − mV
VOS
−3
−2
−1
0
1
2
3
1 10 100 1000
f − Frequency − MHz
Gain = 1
RL = 400 Ω
Rf = 499 Ω
PIN= −20 dBm
VS = 5 V
Small Signal Frequency Response at VOCM− dB
THS4504
THS4505
www.ti.com
......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
TYPICAL CHARACTERISTICS: 5 V (continued)
QUIESCENT CURRENT INPUT OFFSET VOLTAGE COMMON-MODE REJECTION RATIOvs vs vsSUPPLY VOLTAGE CASE TEMPERATURE INPUT COMMON-MODE RANGE
Figure 62. Figure 63. Figure 64.
CLOSED-LOOP OUTPUT HARMONIC DISTORTIONOUTPUT VOLTAGE IMPEDANCE vsvs vs OUTPUT COMMON-MODELOAD RESISTANCE FREQUENCY VOLTAGE
Figure 65. Figure 66. Figure 67.
OUTPUT OFFSET VOLTAGESMALL-SIGNAL FREQUENCY vs QUIESCENT CURRENTRESPONSE OUTPUT COMMON-MODE vsAT V
OCM
VOLTAGE POWER-DOWN VOLTAGE
Figure 68. Figure 69. Figure 70.
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): THS4504 THS4505
0
300
600
900
1200
1500
0.1 1 10 100 1000
− Single-Ended Output ImpedanceZOin Power Down −
f − Frequency − MHz
Gain = 1
RL = 800 Ω
Rf = 499 Ω
PIN = −1 dBm
VS = 5 V
Ω
−1
−2
−5
0 0.5 1 2
0
100.5101 102 103
−3
−6
−4
0
0.01
0.03
0.02
t − Time − ms
Power-Down Voltage Signal − V
Quiescent Current − mA
1.5 2.5 3
Current
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
RL = 800 Ω
VS = 5 V
0
100
200
300
400
500
600
700
800
Power-Down Quiescent Current − Aµ
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: 5 V (continued)
SINGLE-ENDED OUTPUTIMPEDANCE POWER-DOWN QUIESCENTIN POWER-DOWN CURRENTTURN-ON AND TURN-OFF vs vsDELAY TIME FREQUENCY CASE TEMPERATURE
Figure 71. Figure 72. Figure 73.
POWER-DOWN QUIESCENT
CURRENT
vsSUPPLY VOLTAGE
Figure 74.
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Product Folder Link(s): THS4504 THS4505
APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIERS
FULLY DIFFERENTIAL AMPLIFIER
VIN-1
2
3
4
8
7
6
5
VOCM
VS+
VOUT+
VIN+
VS-
VOUT-
PD
Applications Section
INPUT COMMON-MODE VOLTAGE RANGE
THS4504
THS4505
www.ti.com
......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
•Additional Reference Material
Differential signaling offers a number of performance
TERMINAL FUNCTIONSadvantages in high-speed analog signal processingsystems, including immunity to external Fully differential amplifiers are typically packaged incommon-mode noise, suppression of even-order eight-pin packages as shown in the diagram. Thenonlinearities, and increased dynamic range. Fully device pins include two inputs (V
IN+
,V
IN –
), two outputsdifferential amplifiers not only serve as the primary (V
OUT –
,V
OUT+
), two power supplies (V
S+
, V
S –
), anmeans of providing gain to a differential signal chain, output common-mode control pin (V
OCM
), and anbut also provide a monolithic solution for converting optional power-down pin ( PD).single-ended signals into differential signals foreasier, higher performance processing. The THS4500family of amplifiers contains the flagship products inTexas Instruments' expanding line ofhigh-performance fully differential amplifiers.Information on fully differential amplifierfundamentals, as well as implementation-specificinformation, is presented in the applications section ofthis data sheet to provide a better understanding ofthe operation of the THS4500 family of devices, andto simplify the design process for designs using theseamplifiers.
Figure 75. Fully Differential Amplifier Pin DiagramThe THS4504 and THS4505 are intended to below-cost alternatives to the THS4500/1/2/3 devices.
A standard configuration for the device is shown inFrom a topology standpoint, the THS4504/5 have the
the figure. The functionality of a fully differentialsame architecture as the THS4500/1. Specifically, the
amplifier can be imagined as two inverting amplifiersinput common-mode range is designed to include the
that share a common noninverting terminal (thoughnegative power supply rail.
the voltage is not necessarily fixed). For moreinformation on the basic theory of operation for fullydifferential amplifiers, refer to the Texas Instrumentsapplication note titled Fully Differential Amplifiers•Fully Differential Amplifier Terminal Functions
(SLOA054 ).•Input Common-Mode Voltage Range and theTHS4500 Family•Choosing the Proper Value for the Feedback and
AND THE THS4500 FAMILYGain Resistors
The key difference between the THS4500/1 and the•Application Circuits Using Fully Differential
THS4502/3 is the input common-mode range for theAmplifiers
four devices. The input common-mode range of the•Key Design Considerations for Interfacing to an
THS4504/5 is the same as the THS4500/1. TheAnalog-to-Digital Converter
THS4502 and THS4503 have an input•Setting the Output Common-Mode Voltage With
common-mode range that is centered around midrail,the V
OCM
Input
and the THS4500 and THS4501 have an input•Saving Power with Power-Down Functionality
common-mode range that is shifted to include thenegative power supply rail. Selection of one or the•Linearity: Definitions, Terminology, Circuit
other is determined by the nature of the application.Techniques, and Design Tradeoffs
Specifically, the THS4500 and THS4501 are•An Abbreviated Analysis of Noise in Fully
designed for use in single-supply applications whereDifferential Amplifiers
the input signal is ground-referenced, as depicted in•Printed-Circuit Board Layout Techniques for
Figure 76 . The THS4502 and THS4503 are designedOptimal Performance
for use in single-supply or split-supply applications•Power Dissipation and Thermal Considerations
where the input signal is centered between the•Power-Supply Decoupling Techniques and
power-supply voltages, as depicted in Figure 77 .Recommendations
•Evaluation Fixtures, Spice Models, andApplications Support
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): THS4504 THS4505
V =
OUT+
V (1 ) V (1 )+2V b
IN+ IN OCM-
- b - - b
2b
(1)
V =
OUT-
- bV (1 )+V (1 )+2V
IN+ IN OCM-
- b - b
2b
(2)
V =V (1 )+V- b
N IN OUT+-b
(3)
VOCM
+VS
VS
RSRG1
RG2
RF1
RF2
+
RT
+
-
-
b=RG
R +R
F G
(4)
V =V (1 )+V- b
P IN+ OUT-b
(5)
VOCM
+VS
VS
RSRG1
RG2
RF1
RF2
+
RT
+
-VS
-
-
VOCM
RG
RG
RF
RF
+
+
VP
VN
VOUT-
VOUT+
VIN+
VIN-
-
-
THS4504
THS4505
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Where:
Figure 76. Application Circuit for the THS4500 andTHS4501, Featuring Single-Supply Operation witha Ground-Referenced Input Signal
NOTE:
The equations denote thedevice inputs as V
N
andV
P
, and the circuit inputsas V
IN+
and V
IN –
.
Figure 77. Application Circuit for the THS4500 andTHS4501, Featuring Split-Supply Operation withan Input Signal Referenced at the Midrail
Equation 1 to Equation 5 allow calculation of the
Figure 78. Diagram for Input Common-Moderequired input common-mode range for a given set of
Range Equationsinput conditions.
The equations allow calculation of the input common-
Table 1 and Table 2 show the input common-modemode range requirements given information about the
range requirements for two different input scenarios,input signal, the output voltage swing, the gain, and
an input referenced around the negative rail and anthe output common-mode voltage. Calculating the
input referenced around midrail. The tables highlightmaximum and minimum voltage required for V
N
and
the differing requirements on input common-modeV
P
(the amplifier input nodes) determines whether or
range, and illustrate reasoning for choosing either thenot the input common-mode range is violated or not.
THS4500/1 or the THS4502/3. For signals referencedFour equations are required. Two calculate the output
around the negative power supply, the THS4500/1voltages and two calculate the node voltages at V
N
should be chosen since its input common-modeand V
P
(note that only one of these needs calculation,
range includes the negative supply rail. For all otheras the amplifier forces a virtual short between the two
situations, the THS4502/3 offers slightly improvednodes).
distortion and noise performance for applications withinput signals centered between the power-supplyrails.
Table 1. Negative-Rail Referenced
Gain (V/V) V
IN+
(V) V
IN –
(V) V
IN
(V
PP
) V
OCM
(V) V
OD
(V
PP
) V
NMIN
(V) V
NMAX
(V)
1 – 2.0 to 2.0 0 4 2.5 4 0.75 1.752 – 1.0 to 1.0 0 2 2.5 4 0.5 1.1674 – 0.5 to 0.5 0 1 2.5 4 0.3 0.78 – 0.25 to 0.25 0 0.5 2.5 4 0.167 0.389
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CHOOSING THE PROPER VALUE FOR THE
APPLICATION CIRCUITS USING FULLY
Gain VOD
VIN
THS4504
THS4505
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......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
requirements, determine the value of the gainFEEDBACK AND GAIN RESISTORS resistors, directly impacting the input impedance ofthe entire circuit. While there are no strict rules aboutThe selection of feedback and gain resistors impacts
resistor selection, these trends can provide qualitativecircuit performance in a number of ways. The values
design guidance.in this section provide the optimum high-frequencyperformance (lowest distortion, flat frequencyresponse). Since the THS4500 family of amplifiers is
DIFFERENTIAL AMPLIFIERSdeveloped with a voltage-feedback architecture, thechoice of resistor values does not have a dominant
Fully differential amplifiers provide designers with aeffect on bandwidth, unlike a current-feedback
great deal of flexibility in a wide variety ofamplifier. However, resistor choices do have
applications. This section provides an overview ofsecond-order effects. For optimal performance, the
some common circuit configurations and gives somefollowing feedback resistor values are recommended.
design guidelines. Designing the interface to an ADC,In higher gain configurations (gain greater than two),
driving lines differentially, and filtering with fullythe feedback resistor values have much less effect on
differential amplifiers are a few of the circuits that arethe high-frequency performance. Example feedback
covered.and gain resistor values are given in the section onbasic design considerations (Table 3 ).
Amplifier loading, noise, and the flatness of thefrequency response are three design parameters thatshould be considered when selecting feedbackresistors. Larger resistor values contribute more noiseand can induce peaking in the ac response in lowgain configurations, and smaller resistor values canload the amplifier more heavily, resulting in areduction in distortion performance. In addition,feedback resistor values, coupled with gain
Table 2. Midrail Referenced
Gain (V/V) V
IN+
(V) V
IN –
(V) V
IN
(V
PP
) V
OCM
(V) V
OD
(V
PP
) V
NMIN
(V) V
NMAX
(V)
1 0.5 to 4.5 2.5 4 2.5 4 2 32 1.5 to 3.5 2.5 2 2.5 4 2.16 2.834 2.0 to 3.0 2.5 1 2.5 4 2.3 2.78 2.25 to 2.75 2.5 0.5 2.5 4 2.389 2.61
Table 3. Resistor Values for Balanced Operation in Various Gain Configurations
R2 & R4 ( Ω) R1 ( Ω) R3 ( Ω) R
T
(Ω)
1 392 412 383 54.91 499 523 487 53.62 392 215 187 60.42 1.3 k 665 634 52.35 1.3 k 274 249 56.25 3.32 k 681 649 52.310 1.3 k 147 118 64.910 6.81 k 698 681 52.3
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
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BASIC DESIGN CONSIDERATIONS
1
R =
T
1-K
2(1+K)
R3
-
1
RS
K= R2
R1 R2=R4
R3=R1 (R ||R )-S T
R1
R1+R2
b=
1
R3+R ||R
T S
R3+R || +R4
T S
R
b=
2
(7)
VOD
VS
=2 1- b2
b b21 +
RT
R RST +
(8)
VOD
VIN
=2 1- b2
b b21 +
(9)
INTERFACING TO AN ANALOG-TO-DIGITAL
THS4504
THS4505
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•Use separate analog and digital power suppliesand grounds. Noise (bounce) in the powerThe circuits in Figure 76 through Figure 78 are used
supplies (created by digital switching currents) canto highlight basic design considerations for fully
couple directly into the signal path, anddifferential amplifier circuit designs.
power-supply noise can create higher distortionproducts as well.Equations for calculating fully differential amplifierresistor values in order to obtain balanced operation
•Use care when filtering. While an RC low-passin the presence of a 50- Ωsource impedance are
filter may be desirable on the output of thegiven in Equation 6 through Equation 9 .
amplifier to filter broadband noise, the excessloading can negatively impact the amplifierlinearity. Filtering in the feedback path does nothave this effect.•AC-coupling allows easier circuit design. Ifdc-coupling is required, be aware of the excess(6)
power dissipation that can occur due tolevel-shifting the output through the outputcommon-mode voltage control.•Do not terminate the output unless required. Manyopen-loop, class-A amplifiers require 50- Ωtermination for proper operation, but closed-loopfully differential amplifiers drive a specific outputvoltage regardless of the load impedance present.Terminating the output of a fully differentialamplifier with a heavy load adversely effects theamplifier's linearity.For more detailed information about balance in fully
•Comprehend the V
OCM
input drive requirements.differential amplifiers, see the Fully Differential
Determine if the ADC voltage reference canAmplifiers, referenced at the end of this data sheet.
provide the required amount of current to moveV
OCM
to the desired value. A buffer may beneeded.CONVERTER
•Decouple the V
OCM
pin to eliminate the antennaThe THS4500 family of amplifiers are designed
effect. V
OCM
is a high-impedance node that canspecifically to interface to today's
act as an antenna. A large decoupling capacitorhighest-performance analog-to-digital converters.
on this node eliminates this problem.This section highlights the key concerns when
•Be cognizant of the input common-mode range. Ifinterfacing to an ADC and provides example
the input signal is referenced around the negativeADC/fully differential amplifier interface circuits.
power supply rail (e.g., around ground on a singleKey design concerns when interfacing to an
5 V supply), then the THS4500/1 accommodatesanalog-to-digital converter:
the input signal. If the input signal is referenced•Terminate the input source properly. In around midrail, choose the THS4502/3 for thehigh-frequency receiver chains, the source best operation.feeding the fully differential amplifier requires a
•Packaging makes a difference at higherspecific load impedance (for example, 50 Ω).
frequencies. If possible, choose the smaller,•Design a symmetric printed-circuit board (PCB) thermally-enhanced MSOP package for the bestlayout. Even-order distortion products are heavily performance. As a rule, lower junctioninfluenced by layout, and careful attention to a temperatures provide better performance. Ifsymmetric layout will minimize these distortion possible, use a thermally-enhanced package,products. even if the power dissipation is relatively smallcompared to the maximum power dissipation•Minimize inductance in power-supply decoupling
rating to achieve the best results.traces and components. Poor power-supplydecoupling can have a dramatic effect on circuit •Comprehend the effect of the load impedanceperformance. Since the outputs are differential, seen by the fully differential amplifier whendifferential currents exist in the power-supply pins. performing system-level intercept pointThus, decoupling capacitors should be placed in a calculations. Lighter loads (such as thosemanner that minimizes the impedance of the presented by an ADC) allow smaller interceptcurrent loop. points to support the same level of intermodulationdistortion performance.
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EXAMPLE ANALOG-TO-DIGITAL
VOCM
15V
VS
RSRGRF
RF
+
RT
+
RG
CG
0.1 mF
CG
THS4504 VDD
CS
CS
RL
VOD PP
=26V
RISO
RISO
-
-
FILTERING WITH FULLY DIFFERENTIAL
+
+
VOCM 12-Bit/80MSPS
IN
IN
5 V
CM
5 V
5 V
VS
10 mF 0.1 mF
10 mF 0.1 mF
THS4503
RF
RF
CF
CF
1mF
RG
RG0.1 mF
RT
RS
ADS5410
RISO
RISO
-
-
+
+
VOCM 14-Bit/40MSPS
IN
IN
5 V
CM
5 V
VS
10 mF0.1 mF
THS4501
RF
RF
CF
CF
1mF
RG
RG
RT
RS
ADS5421
0.1 Fm
RISO
RISO
-
-
VS
RSRG1 RF1
RF2
+
RT
+
VO
RISO
C
CF2
CF1
RG2 RISO
-
-
FULLY DIFFERENTIAL LINE DRIVERS
THS4504
THS4505
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......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
Figure 81 illustrates the THS4500 family of devicesCONVERTER DRIVER CIRCUITS used as high speed line drivers. For line driverapplications, close attention must be paid to thermalThe THS4500 family of devices is designed to drive
design constraints due to the typically high level ofhigh-performance ADCs with extremely high linearity,
power dissipation.allowing for the maximum effective number of bits atthe output of the data converter. Two representativecircuits shown below highlight single-supply operationand split supply operation. Specific feedback resistor,gain resistor, and feedback capacitor values are notspecified, as their values depend on the frequency ofinterest. Information on calculating these values canbe found in the applications material above.
Figure 81. Fully Differential Line Driver with HighOutput Swing
AMPLIFIERS
Similar to their single-ended counterparts, fullydifferential amplifiers have the ability to couplefiltering functionality with voltage gain. Numerous filtertopologies can be based on fully differentialamplifiers. Several of these are outlined in AFigure 79. Using the THS4503 with the ADS5410
Differential Circuit Collection (SLOA064 ), referencedat the end of this data sheet. The circuit in Figure 82depicts a simple two-pole low-pass filter applicable tomany different types of systems. The first pole is setby the resistors and capacitors in the feedback paths,and the second pole is set by the isolation resistorsand the capacitor across the outputs of the isolationresistors.
Figure 80. Using the THS4501 with the ADS5421
Figure 82. A Two-Pole, Low-Pass Filter DesignThe THS4500 family of amplifiers can be used as
Using a Fully Differential Amplifier with Poleshigh-frequency, high-swing differential line drivers.
Located at P1 = (2 ×R
F
C
F
)
– 1
in Hz andTheir high power supply voltage rating (16.5 V
P2 = (4 ×R
ISO
C)
– 1
in Hzabsolute maximum) allows operation on a single 12-Vor a single 15-V supply. The high supply voltage,coupled with the ability to provide differential outputsenables the ability to drive 26 V
PP
into reasonablyheavy loads (250 Ωor greater). The circuit in
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SETTING THE OUTPUT COMMON-MODE
VOCM =2.5V
5V
VS
RSRG1
RG2
RF1
RF2
+
RT
+RS
2.5-VDC
2.5-VDC
DCCurrentPathtoGround
DCCurrentPathtoGround
I2=VOCM
RF2 G2
+R
I1=
VOCM
RF1 G1 S T
+R +R ||R
-
-
R =50kW
R =50kW
VS+
VS-
VOCM
IIN
IIN =2V V V- -
OCM S
S+ -
R
THS4504
THS4505
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Often times, filters like these are used to eliminate for the sole purpose of filtering any high frequencybroadband noise and out-of-band distortion products noise that could couple into the signal path throughin signal acquisition systems. It should be noted that the V
OCM
circuitry. A 0.1- µF or 1- µF capacitance is athe increased load placed on the output of the reasonable value for eliminating a great deal ofamplifier by the second low-pass filter has a broadband interference, but additional, tuneddetrimental effect on the distortion performance. The decoupling capacitors should be considered if apreferred method of filtering is using the feedback specific source of electromagnetic or radio frequencynetwork, as the typically smaller capacitances interference is present elsewhere in the system.required at these points in the circuit do not load the Information on the ac performance (bandwidth, slewamplifier nearly as heavily in the pass-band. rate) of the V
OCM
circuitry is included in thespecification table and graph section.
Since the V
OCM
pin provides the ability to set anVOLTAGE WITH THE V
OCM
INPUT
output common-mode voltage, the ability forincreased power dissipation exists. While this doesThe output common-mode voltage pin provides a
not pose a performance problem for the amplifier, itcritical function to the fully differential amplifier; it
can cause additional power dissipation of which theaccepts an input voltage and reproduces that input
system designer should be aware. The circuit shownvoltage as the output common-mode voltage. In other
in Figure 84 demonstrates an example of thiswords, the V
OCM
input provides the ability to level-shift
phenomenon. For a device operating on a single 5-Vthe outputs to any voltage inside the output voltage
supply with an input signal referenced around groundswing of the amplifier.
and an output common-mode voltage of 2.5 V, a dcA description of the input circuitry of the V
OCM
pin is
potential exists between the outputs and the inputs ofshown below to facilitate an easier understanding of
the device. The amplifier sources current into thethe V
OCM
interface requirements. The V
OCM
pin has
feedback network in order to provide the circuit withtwo 50-k Ωresistors between the power supply rails to
the proper operating point. While there are no seriousset the default output common-mode voltage to
effects on the circuit performance, the extra powermidrail. A voltage applied to the V
OCM
pin alters the
dissipation may need to be included in the systemoutput common-mode voltage as long as the source
power budget.has the ability to provide enough current to overdrivethe two 50-k Ωresistors. This phenomenon isdepicted in the V
OCM
equivalent circuit diagram.Current drive is especially important when using thereference voltage of an analog-to-digital converter todrive V
OCM
. Output current drive capabilities differfrom part to part, so a voltage buffer may benecessary in some applications.
Figure 84. Depiction of DC Power DissipationFigure 83. Equivalent Input Circuit for V
OCM
Caused by Output Level-Shifting in a DC-CoupledCircuitBy design, the input signal applied to the V
OCM
pinpropagates to the outputs as a common-mode signal.As shown in the equivalent circuit diagram, the V
OCMinput has a high impedance associated with it,dictated by the two 50-k Ωresistors. While the highimpedance allows for relaxed drive requirements, italso allows the pin and any associated printed-circuitboard traces to act as an antenna. For this reason, adecoupling capacitor is recommended on this node
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SAVING POWER WITH POWER-DOWN
LINEARITY: DEFINITIONS, TERMINOLOGY,
IMD3 = PS − PO
PS
PO
PO
∆fc = fc − f1
∆fc = f2 − fc
PS
fc − 3∆f f1 fcf2 fc + 3∆f
Power
f − Frequency − MHz
THS4504
THS4505
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......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
Amplifiers are generally thought of as linear devices.FUNCTIONALITY In other words, the output of an amplifier is a linearlyscaled version of the input signal applied to it. InThe THS4500 family of fully differential amplifiers
reality, however, amplifier transfer functions arecontains devices that come with and without the
nonlinear. Minimizing amplifier nonlinearity is apower-down option. Even-numbered devices have
primary design goal in many applications.power-down capability, which is described in detailhere. Intercept points are specifications that have longbeen used as key design criteria in the RFThe power-down pin of the amplifiers defaults to the
communications world as a metric for thepositive supply voltage in the absence of an applied
intermodulation distortion performance of a device involtage (i.e. an internal pullup resistor is present),
the signal chain (for example, amplifiers, mixers,putting the amplifier in the power-on mode of
etc.). Use of the intercept point, rather than strictly theoperation. To turn off the amplifier in an effort to
intermodulation distortion, allows for simplerconserve power, the power-down pin can be driven
system-level calculations. Intercept points, like noisetowards the negative rail. The threshold voltages for
figures, can be easily cascaded back and forthpower-on and power-down are relative to the supply
through a signal chain to determine the overallrails and given in the specification tables. Above the
receiver chain intermodulation distortion performance.enable threshold voltage, the device is on. Below the
The relationship between intermodulation distortiondisable threshold voltage, the device is off. Behavior
and intercept point is depicted in Figure 85 andin between these threshold voltages is not specified.
Figure 86 .Note that this power-down functionality is just that;the amplifier consumes less power in power-downmode. The power-down mode is not intended toprovide a high-impedance output. In other words, thepower-down functionality is not intended to allow useas a 3-state bus driver. When in power-down mode,the impedance looking back into the output of theamplifier is dominated by the feedback and gainsetting resistors.
The time delays associated with turning the device onand off are specified as the time it takes for theamplifier to reach 50% of the nominal quiescentcurrent. The time delays are on the order ofmicroseconds because the amplifier moves in and outof the linear mode of operation in these transitions.
CIRCUIT TECHNIQUES, AND DESIGNTRADEOFFS
Figure 85. 2-Tone and 3rd-Order IntermodulationThe THS4500 family of devices features
Productsunprecedented distortion performance for monolithicfully differential amplifiers. This section focuses on
Due to the intercept point's ease of use in systemthe fundamentals of distortion, circuit techniques for
level calculations for receiver chains, it has becomereducing nonlinearity, and methods for equating
the specification of choice for guidingdistortion of fully differential amplifiers to desired
distortion-related design decisions. Traditionally,linearity specifications in RF receiver chains.
these systems use primarily class-A, single-ended RFamplifiers as gain blocks. These RF amplifiers aretypically designed to operate in a 50- Ωenvironment,just like the rest of the receiver chain. Since interceptpoints are given in dBm, this implies an associatedimpedance (50 Ω).
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 25
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IMD3
OIP3
IIP3
3X
PIN
(dBm)
1X
POUT
(dBm)
PO
PS
10
20
30
40
50
60
0 20 40 60 80 100
OIP − Third-Order Output Intersept Point − dBm
f − Frequency − MHz
0
Normalized to 50 Ω
Gain = 1
Rf = 499 Ω
VO = 2 VPP
VS = ± 5 V
200 kHz Tone Spacing
RL = 800 Ω
Normalized to 200 Ω
3
AN ANALYSIS OF NOISE IN FULLY
OIP =P +
3 O
|IMD |
3
2
(10)
P =10log
O
2
VPdiff
2R x0.001
L
(11)
THS4504
THS4505
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As can be seen in the equation, when a higherimpedance is used, the same level of intermodulationdistortion performance results in a lower interceptpoint. Therefore, it is important to comprehend theimpedance seen by the output of the fully differentialamplifier when selecting a minimum intercept point.The graphic below shows the relationship betweenthe strict definition of an intercept point with anormalized, or equivalent, intercept point for theTHS4504.
Figure 86. Graphical Representation of 2-Toneand 3rd-Order Intercept Point
However, with a fully differential amplifier, the outputdoes not require termination as an RF amplifier
Figure 87. Equivalent 3rd-Order Intercept Point forwould. Because closed-loop amplifiers deliver signals
the THS4504to their outputs regardless of the impedance present,it is important to comprehend this when evaluating
Comparing specifications between different devicethe intercept point of a fully differential amplifier. The
types becomes easier when a common impedanceTHS4500 series of devices yields optimum distortion
level is assumed. For this reason, the intercept pointsperformance when loaded with 200 Ωto 1 k Ω, very
on the THS4500 family of devices are reportedsimilar to the input impedance of an analog-to-digital
normalized to a 50- Ωload impedance.converter over its input frequency band. As a result,terminating the input of the ADC to 50 Ωcan actuallybe detrimental to system performance.
DIFFERENTIAL AMPLIFIERSThis discontinuity between open-loop, class-A
Noise analysis in fully differential amplifiers isamplifiers and closed-loop, class-AB amplifiers
analogous to noise analysis in single-endedbecomes apparent when comparing the intercept
amplifiers. The same concepts apply. Below, apoints of the two types of devices. Equation 10 gives
generic circuit diagram consisting of a voltage source,the definition of an intercept point, relative to the
a termination resistor, two gain setting resistors, twointermodulation distortion.
feedback resistors, and a fully differential amplifier isshown, including all the relevant noise sources. Fromthis circuit, the noise factor (F) and noise figure (NF)are calculated. The figures indicate the appropriatescaling factor for each of the noise sources in twodifferent cases. The first case includes thetermination resistor, and the second, simplified caseNOTE: P
o
is the output power of a single tone, R
L
is
assumes that the voltage source is properlythe differential load resistance, and V
P(diff)
is the
terminated by the gain-setting resistors. With thesedifferential peak voltage for a single tone.
scaling factors, the amplifier's input noise power (N
A
)can be calculated by summing each individual noisesource with its scaling factor. The noise delivered tothe amplifier by the source (N
I
) and input noise powerare used to calculate the noise factor and noise figureas shown in Equation 23 through Equation 27 .
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Scaling Factors for Individual
(e )
ni
2
2
RG
R +
G
RS
2
RG
RF
+
(18)
(i )
ni
2RG
2
(19)
(i )
ii
2RG
2
(20)
2
4kTRF2´RG
RF
(21)
NiNARgRf
egef
es
Rs
enNo
ini
iii
Rt
et
Ni
Si
No
So
+
−
fully-diff
amp
RgRf
egef
2
4kTRG2´RG
R +
G
RS
2
(22)
Scaling Factors for Individual
Ni S
=4kTR
R +
S
2RT G
R
RT G
+2R
2RT G
R
RT G
+2R
2
(23)
(e )
ni
2
2
RG
R +
G
RSRT
2( )R +R
S T
RG
RF
+
(12)
Ni S
=4kTR 2RG
RS G
+2R
2
(24)
(i )
ni
2RG
2
(13)
Noise Factor and Noise Figure Calculations
(i )
ii
2RG
2
(14)
N = (NoiseSource ScaleFactor)S ´
A
(25)
F=1+ NA
NI
(26)
NF=10log(F)
(27)
R +
T
2RS G
R
RS G
+2R
2RS G
R
RS G
+2R
2
4kTRF
(15)
2
4kTRF2´RG
RF
(16)
4kTRG
2
RG
R +
G
RSRT
2( )R +R
S T
2´
(17)
THS4504
THS4505
www.ti.com
......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
Noise Sources Assuming No TerminationResistance is Used (for example, R
T
is open)
Figure 88. Noise Sources in a FullyDifferential Amplifier Circuit
Input Noise With a Termination Resistor:
Noise Sources Assuming a FiniteValue Termination Resistor
Input Noise Assuming No Termination Resistor:
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): THS4504 THS4505
PC BOARD LAYOUT TECHNIQUES FOR
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
www.ti.com
add a pole and/or a zero below 400 MHz that canOPTIMAL PERFORMANCE effect circuit operation. Keep resistor values aslow as possible, consistent with load drivingAchieving optimum performance with a high
considerations.frequency amplifier-like devices in the THS4500
•Connections to other wideband devices on thefamily requires careful attention to board layout
board may be made with short direct traces orparasitic and external component types.
through onboard transmission lines. For shortRecommendations that optimize performance include:
connections, consider the trace and the input tothe next device as a lumped capacitive load.•Minimize parasitic capacitance to any ac ground
Relatively wide traces (50 mils to 100 mils) shouldfor all of the signal I/O pins. Parasitic capacitance
be used, preferably with ground and power planeson the output and input pins can cause instability.
opened up around them. Estimate the totalTo reduce unwanted capacitance, a window
capacitive load and determine if isolation resistorsaround the signal I/O pins should be opened in all
on the outputs are necessary. Low parasiticof the ground and power planes around those
capacitive loads (< 4 pF) may not need an R
Spins. Otherwise, ground and power planes should
since the THS4500 family is nominallybe unbroken elsewhere on the board.
compensated to operate with a 2-pF parasitic•Minimize the distance (< 0.25 ” ) from the
load. Higher parasitic capacitive loads without anpower-supply pins to high-frequency 0.1- µF
R
S
are allowed as the signal gain increasesdecoupling capacitors. At the device pins, the
(increasing the unloaded phase margin). If a longground and power-plane layout should not be in
trace is required, and the 6-dB signal loss intrinsicclose proximity to the signal I/O pins. Avoid
to a doubly-terminated transmission line isnarrow power and ground traces to minimize
acceptable, implement a matched impedanceinductance between the pins and the decoupling
transmission line using microstrip or striplinecapacitors. The power-supply connections should
techniques (consult an ECL design handbook foralways be decoupled with these capacitors.
microstrip and stripline layout techniques).Larger (6.8 µF or more) tantalum decoupling
•A 50- Ωenvironment is normally not necessarycapacitors, effective at lower frequency, should
onboard, and in fact, a higher impedancealso be used on the main supply pins. These may
environment improves distortion as shown in thebe placed somewhat farther from the device and
distortion versus load plots. With a characteristicmay be shared among several devices in the
board trace impedance defined based on boardsame area of the PC board. The primary goal is to
material and trace dimensions, a matching seriesminimize the impedance seen in the
resistor into the trace from the output of thedifferential-current return paths.
THS4500 family is used as well as a terminating•Careful selection and placement of external
shunt resistor at the input of the destinationcomponents preserve the high frequency
device.performance of the THS4500 family. Resistors
•Remember also that the terminating impedance isshould be a very low reactance type.
the parallel combination of the shunt resistor andSurface-mount resistors work best and allow a
the input impedance of the destination device: thistighter overall layout. Metal-film and carbon
total effective impedance should be set to matchcomposition, axially-leaded resistors can also
the trace impedance. If the 6-dB attenuation of aprovide good high frequency performance. Again,
doubly terminated transmission line iskeep their leads and PC board trace length as
unacceptable, a long trace can beshort as possible. Never use wirewound type
series-terminated at the source end only. Treatresistors in a high-frequency application. Since the
the trace as a capacitive load in this case. Thisoutput pin and inverting input pins are the most
does not preserve signal integrity as well as asensitive to parasitic capacitance, always position
doubly-terminated line. If the input impedance ofthe feedback and series output resistors, if any, as
the destination device is low, there is some signalclose as possible to the inverting input pins and
attenuation due to the voltage divider formed byoutput pins. Other network components, such as
the series output into the terminating impedance.input termination resistors, should be placed closeto the gain-setting resistors. Even with a low
•Socketing a high speed part like the THS4500parasitic capacitance shunting the external
family is not recommended. The additional leadresistors, excessively high resistor values can
length and pin-to-pin capacitance introduced bycreate significant time constants that can degrade
the socket can create an extremely troublesomeperformance. Good axial metal-film or
parasitic network which can make it almostsurface-mount resistors have approximately
impossible to achieve a smooth, stable frequency0.2 pF in shunt with the resistor. For resistor
response. Best results are obtained by solderingvalues > 2.0 k Ω, this parasitic capacitance can
the THS4500 family parts directly onto the board.
28 Submit Documentation Feedback Copyright © 2002 – 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
PowerPAD DESIGN CONSIDERATIONS PowerPAD PCB LAYOUT CONSIDERATIONS
DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
0.060
0.040
0.075 0.025
0.205
0.010
vias
Pin 1
Top View
0.017
0.035
0.094
0.030
0.013
THS4504
THS4505
www.ti.com
......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
1. Prepare the PCB with a top side etch pattern asThe THS4500 family is available in a
shown in Figure 90 . There should be etch for thethermally-enhanced PowerPAD family of packages.
leads as well as etch for the thermal pad.These packages are constructed using a downsetleadframe upon which the die is mounted [see
2. Place five holes in the area of the thermal pad.Figure 89 (a) and Figure 89 (b)]. This arrangement
These holes should be 13 mils in diameter. Keepresults in the lead frame being exposed as a thermal
them small so that solder wicking through thepad on the underside of the package [see
holes is not a problem during reflow.Figure 89 (c)]. Because this thermal pad has direct
3. Additional vias may be placed anywhere alongthermal contact with the die, excellent thermal
the thermal plane outside of the thermal padperformance can be achieved by providing a good
area. This helps dissipate the heat generated bythermal path away from the thermal pad.
the THS4500 family IC. These additional viasmay be larger than the 13-mil diameter viasThe PowerPAD package allows for both assembly
directly under the thermal pad. They can beand thermal management in one manufacturing
larger because they are not in the thermal padoperation. During the surface-mount solder operation
area to be soldered so that wicking is not a(when the leads are being soldered), the thermal pad
problem.can also be soldered to a copper area underneath thepackage. Through the use of thermal paths within this
4. Connect all holes to the internal ground plane.copper area, heat can be conducted away from the
5. When connecting these holes to the groundpackage into either a ground plane or other heat
plane, do not use the typical web or spoke viadissipating device.
connection methodology. Web connections havea high thermal resistance connection that isThe PowerPAD package represents a breakthrough
useful for slowing the heat transfer duringin combining the small area and ease of assembly of
soldering operations. This makes the soldering ofsurface mount with the, heretofore, awkward
vias that have plane connections easier. In thismechanical methods of heatsinking.
application, however, low thermal resistance isdesired for the most efficient heat transfer.Therefore, the holes under the THS4500 familyPowerPAD package should make theirconnection to the internal ground plane with acomplete connection around the entirecircumference of the plated-through hole.6. The top-side solder mask should leave theterminals of the package and the thermal padarea with its five holes exposed. The bottom-sideFigure 89. Views of Thermally Enhanced Package
solder mask should cover the five holes of thethermal pad area. This prevents solder fromAlthough there are many ways to properly heatsink
being pulled away from the thermal pad areathe PowerPAD package, the following steps illustrate
during the reflow process.the recommended approach.
7. Apply solder paste to the exposed thermal padarea and all of the IC terminals.8. With these preparatory steps in place, the IC issimply placed in position and run through thesolder reflow operation as any standardsurface-mount component. This results in a partthat is properly installed.
Figure 90. View of Thermally Enhanced Package
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): THS4504 THS4505
POWER DISSIPATION AND THERMAL
2
1.5
1
0
−40 −20 0 20
− Maximum Power Dissipation − W
2.5
3
3.5
40 60 80
TA − Ambient Temperature − °C
PD
8-Pin DGN Package
θJA = 170°C/W for 8-Pin SOIC (D)
θJA = 58.4°C/W for 8-Pin MSOP (DGN)
ΤJ = 150°C, No Airflow
0.5
8-Pin D Package
PDmax =Tmax A
T-
qJA
(28)
DRIVING CAPACITIVE LOADS
VS
RSRG
RF
RF
+
RT
RISO
CL
RG
R =10 25- W
ISO
VS
-VS
RISO
+
-
-
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
www.ti.com
CONSIDERATIONS
The THS4500 family of devices does not incorporateautomatic thermal shutoff protection, so the designermust take care to ensure that the design does notviolate the absolute maximum junction temperature ofthe device. Failure may result if the absolutemaximum junction temperature of +150 °C isexceeded. For best performance, design for amaximum junction temperature of +125 °C. Between+125 °C and +150 °C, damage does not occur, but theperformance of the amplifier begins to degrade.
The thermal characteristics of the device are dictatedby the package and the PC board. Maximum powerdissipation for a given package can be calculatedusing the following formula.
Figure 91. Maximum Power Dissipation vsAmbient Temperature
Where:
When determining whether or not the device satisfiesP
Dmax
is the maximum power dissipation in the
the maximum power dissipation requirement, it isamplifier (W).
important to not only consider quiescent powerT
MAX
is the absolute maximum junction
dissipation, but also dynamic power dissipation. Oftentemperature ( °C).
times, this is difficult to quantify because the signalpattern is inconsistent, but an estimate of the RMST
A
is the ambient temperature ( °C).
power dissipation can provide visibility into a possibleθ
JA
=θ
JC
+θ
CA
problem.θ
JC
is the thermal coefficient from the siliconjunctions to the case ( °C/W).θ
CA
is the thermal coefficient from the case to
High-speed amplifiers are typically not well-suited forambient air ( °C/w).
driving large capacitive loads. If necessary, however,For systems where heat dissipation is more critical,
the load capacitance should be isolated by twothe THS4500 family of devices is offered in an
isolation resistors in series with the output. TheMSOP-8 with PowerPAD. The thermal coefficient for
requisite isolation resistor size depends on the valuethe MSOP PowerPAD package is substantially
of the capacitance, but 10 Ωto 25 Ωis a good placeimproved over the traditional SOIC. Maximum power
to begin the optimization process. Larger isolationdissipation levels are depicted in the graph for the
resistors decrease the amount of peaking in thetwo packages. The data for the DGN package
frequency response induced by the capacitive load,assumes a board layout that follows the PowerPAD
but this comes at the expense of larger voltage droplayout guidelines referenced above and detailed in
across the resistors, increasing the output swingthe PowerPAD application notes in the Additional
requirements of the system.Reference Materialsection at the end of the datasheet.
Figure 92. Use of Isolation Resistors with aCapacitive Load
30 Submit Documentation Feedback Copyright © 2002 – 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
POWER-SUPPLY DECOUPLING
_
+
4
5
3
7
26
VOCMVS
PwrPad
VSPD
1
8
R0805
R4
C4 C0805
R5 R0805
C3
C0805
R6
R7
R0805
R0805
C5
C6
C0805
C0805
C7
C0805
J2
J3
J2
J3
R2
R0805
R3
R0805
C1
C0805
C2
C0805
R1
R1206
J1
3
1
4
5
6
R11
R1206
R9
R0805
R8
R9
R0805
R0805
J2
J3
J4
T1
U1
THS450X
EVALUATION FIXTURES, SPICE MODELS,
THS4504
THS4505
www.ti.com
......................................................................................................................................................... SLOS363D – AUGUST 2002 – REVISED MAY 2008
TECHNIQUES AND RECOMMENDATIONS
Power-supply decoupling is a critical aspect of anyhigh-performance amplifier design process. Carefuldecoupling provides higher quality ac performance(most notably improved distortion performance). Thefollowing guidelines ensure the highest level ofperformance.
1. Place decoupling capacitors as close to thepower-supply inputs as possible, with the goal ofminimizing the inductance of the path fromground to the power supply.2. Placement priority should be as follows: smallercapacitors should be closer to the device.3. Use of solid power and ground planes isrecommended to reduce the inductance alongpower-supply return current paths.
Figure 93. Simplified Schematic of the Evaluation4. Recommended values for power supply Board. Power-Supply Decoupling, V
OCM
, andPower-Down Circuitry not Showndecoupling include 10- µF and 0.1- µF capacitorsfor each supply. A 1000-pF capacitor can beused across the supplies as well for extremely
Computer simulation of circuit performance usinghigh-frequency return currents, but often is not
SPICE is often useful when analyzing therequired.
performance of analog circuits and systems. This isparticularly true for video and RF amplifier circuitswhere parasitic capacitance and inductance can haveAND APPLICATIONS SUPPORT
a major effect on circuit performance. A SPICE modelfor the THS4500 family of devices is availableTexas Instruments is committed to providing its
through the Texas Instruments web site (www.ti.com ).customers with the highest quality of applications
The Product Information Center (PIC) is available forsupport. To support this goal, an evaluation board
design assistance and detailed product information.has been developed for the THS4500 family of fully
These models do a good job of predictingdifferential amplifiers. The evaluation board can be
small-signal ac and transient performance under aobtained by ordering through the Texas Instruments
wide variety of operating conditions. They are notweb site, www.ti.com , or through your local Texas
intended to model the distortion characteristics of theInstruments sales representative. The schematic for
amplifier, nor do they attempt to distinguish betweenthe evaluation board is shown in Figure 93 with
the package types in their small-signal acdefault component values. Unpopulated footprints are
performance. Detailed information about what is andshown to provide insight into design flexibility.
is not modeled is contained in the model file itself.
Copyright © 2002 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): THS4504 THS4505
ADDITIONAL REFERENCE MATERIAL
THS4504
THS4505
SLOS363D – AUGUST 2002 – REVISED MAY 2008 .........................................................................................................................................................
www.ti.com
•PowerPAD Made Easy, application brief, (SLMA004 ).•PowerPAD Thermally-Enhanced Package, technical brief, (SLMA002 ).•Karki, James. Fully Differential Amplifiers.application report, (SLOA054D ).•Karki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High-Speed ADCs, andDifferential Transmission Lines. Texas Instruments Analog Applications Journal, February 2001.•Carter, Bruce. A Differential Op-Amp Circuit Collection. application report, (SLOA064 ).•Carter, Bruce. Differential Op-Amp Single-Supply Design Technique, application report, (SLOA072 ).•Karki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments AnalogApplications Journal, July 2001.
Revision History
Changes from Revision C (March 2004) to Revision D .................................................................................................. Page
•Updated document format ..................................................................................................................................................... 1•Added footnote 1 to Ordering Information table .................................................................................................................... 3•Changed x-axis of Figure 12 ................................................................................................................................................ 11•Changed x-axis of Figure 49 ................................................................................................................................................ 15•Changed two to four in first sentece of the Input Common-Mode Voltage Range and the THS4500 Family section ........ 19•Deleted figure from Basic Design Considerations section ................................................................................................... 22•Changed cross-references in first sentence of Basic Design Considerations section to Figure 76 through Figure 78 ...... 22•Changed below to in Figure 82 in first paragraph of Filtering with Fully Differential Amplifiers section .............................. 23•Removed reference to nonexistant table in second paragraph of Setting the Output Common-Mode Voltage with theV
OCM
Input section ................................................................................................................................................................ 24•Added titles to Figure 85 ,Figure 86 , and Figure 87 ............................................................................................................ 25•Changed THS4502 to THS4504 in last sentence of eighth paragraph in the Linearity: Definitions, Terminology,Circuit Techniques, and Design Tradeoffs section .............................................................................................................. 25
32 Submit Documentation Feedback Copyright © 2002 – 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4504 THS4505
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4504D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4504DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4504DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4504DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4504DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4504DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4504DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4504DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4504DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4504DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4505D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4505DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4505DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4505DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4505DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4505DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4505DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4505DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4505DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4505DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4504DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4504DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4505DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4505DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4504DGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4504DR SOIC D 8 2500 367.0 367.0 35.0
THS4505DGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4505DR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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