Low Cost P Supervisory Circuits ADM705/ADM706/ADM707/ADM708 FUNCTIONAL BLOCK DIAGRAMS WATCHDOG INPUT (WDI) WATCHDOG TRANSITION DETECTOR VCC 250A MR 4.65V* ADM705/ ADM706 POWER-FAIL INPUT (PFI) WATCHDOG OUTPUT (WDO) RESET AND WATCHDOG TIMEBASE RESET GENERATOR VCC 1.25V RESET POWER-FAIL OUTPUT (PFO) * VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706) Figure 1. APPLICATIONS Microprocessor systems Computers Controllers Intelligent instruments Critical P monitoring Automotive systems Critical P power monitoring WATCHDOG TIMER VCC 250A MR RESET RESET GENERATOR VCC 4.65V* POWER-FAIL INPUT (PFI) RESET ADM707/ ADM708 POWER-FAIL OUTPUT (PFO) 1.25V * VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708) 00088-002 Guaranteed RESET valid with VCC = 1 V 190 A quiescent current Precision supply-voltage monitor 4.65 V (ADM705/ADM707) 4.40 V (ADM706/ADM708) 200 ms reset pulse width Debounced TTL/CMOS manual reset input (MR) Independent watchdog timer 1.6 sec timeout (ADM705/ADM706) Active-high reset output (ADM707/ADM708) Voltage monitor for power-fail or low battery warning Superior upgrade for MAX705-MAX708 00088-001 FEATURES Figure 2. GENERAL DESCRIPTION The ADM705/ADM706/ADM707/ADM708 are low cost P supervisory circuits. They are suitable for monitoring the 5 V power supply/battery and can also monitor microprocessor activity. The ADM705/ADM706 provide the following functions: The ADM707/ADM708 differ in that: * A watchdog timer function is not available. * An active-high reset output in addition to the active-low output is available. * Power-on reset output during power-up, power-down, and brownout conditions. The RESET output remains operational with VCC as low as 1 V. Two supply-voltage monitor levels are available. The ADM705/ADM707 generate a reset when the supply voltage falls below 4.65 V, while the ADM706/ADM708 require that the supply fall below 4.40 V before a reset is issued. * Independent watchdog timeout, WDO, that goes low if the watchdog input has not been toggled within 1.6 seconds. All parts are available in 8-lead DIP and SOIC packages. * A 1.25 V threshold detector for power-fail warning, low battery detection, or to monitor a power supply other than 5 V. * An active-low debounced manual reset input (MR). Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2005 Analog Devices, Inc. All rights reserved. ADM705/ADM706/ADM707/ADM708 TABLE OF CONTENTS Features .............................................................................................. 1 Power-Fail RESET Output ...........................................................8 Applications....................................................................................... 1 Manual Reset (ADM707/ADM708) ...........................................8 Functional Block Diagrams............................................................. 1 Watchdog Timer (ADM705/ADM706) .....................................8 General Description ......................................................................... 1 Power-Fail Comparator ................................................................8 Revision History ............................................................................... 2 Valid RESET Below 1 V VCC ........................................................9 Specifications..................................................................................... 3 Applications..................................................................................... 10 Absolute Maximum Ratings............................................................ 4 Monitoring Additional Supply Levels...................................... 10 ESD Caution.................................................................................. 4 Ps with Bidirectional RESET .................................................. 10 Pin Configurations and Function Descriptions ........................... 5 Outline Dimensions ....................................................................... 11 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 12 Circuit Information .......................................................................... 8 REVISION HISTORY 11/05--Rev. C to Rev. D Updated Format..................................................................Universal Deleted Figure 2................................................................................ 4 Updated Outline Dimensions ....................................................... 11 Changes to Ordering Guide .......................................................... 12 8/02--Rev. B to Rev. C Removed RM-8 (SOIC) Package....................................Universal Updated N-8 and R-8 Packages ...................................................... 8 Rev. D | Page 2 of 12 ADM705/ADM706/ADM707/ADM708 SPECIFICATIONS VCC = 4.75 V to 5.5 V, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter VCC Operating Voltage Range Supply Current Reset Threshold Reset Threshold Hysteresis Reset Pulse Width RESET Output Voltage Min 1.0 4.5 4.25 160 VCC - 1.5 Typ 190 4.65 4.40 40 200 Max 5.5 250 4.75 4.50 280 0.4 0.3 0.3 RESET Output Voltage VCC - 1.5 Watchdog Timeout Period (tWD) WDI Pulse Width (tWP) WDI Input Threshold Logic Low Logic High WDI Input Current 1.00 50 WDO Output Voltage MR Pull-Up Current MR Pulse Width MR Input Threshold 1.60 0.4 2.25 0.8 3.5 -150 VCC - 1.5 100 150 50 -50 250 150 0.4 600 0.8 2.0 250 MR to Reset Output Delay PFI Input Threshold PFI Input Current PFO Output Voltage 1.2 -25 VCC - 1.5 1.25 +0.01 1.3 +25 0.4 Rev. D | Page 3 of 12 Unit V A V V mV ms V V V V V V sec ns V V A A V V A ns V V ns V nA V V Test Conditions/Comments ADM705, ADM707 ADM706, ADM708 ISOURCE = 800 A ISINK = 3.2 mA VCC = 1 V, ISINK = 50 A VCC = 1.2 V, ISINK = 100 A ADM707, ADM708, ISOURCE = 800 A ADM707, ADM708, ISINK = 1.2 mA VIL = 0.4 V, VIH = VCC x 0.8 WDI = VCC WDI = 0 V WDI = 0 V ISOURCE = 800 A ISINK = 1.2 mA MR = 0 V ISOURCE = 800 A ISINK = 3.2 mA ADM705/ADM706/ADM707/ADM708 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 2. Parameter VCC All Other Inputs Input Current VCC GND Digital Output Current Power Dissipation, N-8 PDIP JA Thermal Impedance Power Dissipation, R-8 SOIC JA Thermal Impedance Operating Temperature Range Industrial (A Version) Lead Temperature (Soldering, 10 sec) Vapor Phase (60 sec) Infrared (15 sec) Storage Temperature Range ESD Rating Rating -0.3 V to +6 V -0.3 V to VCC + 0.3 V 20 mA 20 mA 20 mA 727 mW 135C/W 470 mW 110C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -40C to +85C 300C 215C 220C -65C to +150C >5 kV ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 4 of 12 ADM705/ADM706/ADM707/ADM708 ADM705/ ADM706 WDO 7 RESET 6 WDI TOP VIEW PFI 4 (Not to Scale) 5 PFO GND 3 MR 1 8 VCC 2 GND 3 ADM707/ ADM708 8 RESET 7 RESET 6 NC TOP VIEW PFI 4 (Not to Scale) 5 PFO 00088-003 MR 1 VCC 2 NC = NO CONNECT Figure 3.ADM705/ADM706 Pin Configuration 00088-004 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4.ADM707/ADM708 Pin Configuration Table 3. Pin Function Descriptions Mnemonic MR Pin Number ADM705 ADM707 ADM706 ADM708 PDIP, SOIC PDIP, SOIC 1 1 VCC GND PFI 2 3 4 2 3 4 PFO 5 5 WDI 6 NC RESET 7 7 WDO 8 RESET 8 6 Function Manual Reset Input. When taken below 0.8 V, a RESET is generated. MR can be driven from TTL, CMOS logic, or from a manual reset switch as it is internally debounced. An internal 250 A pullup current holds the input high when floating. 5 V Power Supply Input. 0 V Ground Reference for All Signals. Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected to GND or VCC. Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is less than 1.25 V. Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog timeout period, the watchdog output WDO goes low. The timer resets with each transition at the WDI input. Either a high-to-low or a low-to-high transition clears the counter. The internal timer is also cleared whenever reset is asserted. The watchdog timer is disabled when WDI is left floating or connected to a three-state buffer. No Connect. Logic Output. RESET goes low for 200 ms when triggered. It can be triggered either by VCC being below the reset threshold or by a low signal on the manual reset (MR) input. RESET remains low whenever VCC is below the reset threshold (4.65 V in ADM705, 4.4 V in ADM706). It remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is connected to MR. Watchdog Output. WDO remains low until the watchdog timer is cleared. WDO also goes low during low line conditions. Whenever VCC is below the reset threshold, WDO goes low if the internal WDO remains low. As soon as VCC goes above the reset threshold, WDO goes high immediately. Logic Output. RESET is an active-high output suitable for systems that use active-high RESET logic. It is the inverse of RESET. Rev. D | Page 5 of 12 ADM705/ADM706/ADM707/ADM708 TYPICAL PERFORMANCE CHARACTERISTICS A1 VCC VCC = 5V TA = 25C 4.50V 100 1.3V 90 PFI 1.2V 4.4V PFO 10 0% RESET 500msH O 0V 00088-015 1V 00088-012 1V 500ns/DIV Figure 5. RESET Output Voltage vs. Supply Voltage A1 VCC = VRT TA = 25C 4.50V 5V 100 RESET 5V 90 RESET RESET 10 0V 0% 1V 0V 00088-013 1V 500msH O 00088-016 VCC Figure 8. PFI Comparator Deassertion Response Time 100ns/DIV Figure 6. ADM707/ADM708 RESET Output Voltage vs. Supply Voltage VCC = 5V TA = 25C Figure 9. RESET, RESET Assertion VCC = VRT TA = 25C 5V RESET 1.3V PFI 5V RESET 1.2V 5V PFO 500ns/DIV 0V 00088-017 00088-014 0V 0V 100ns/DIV Figure 7. PFI Comparator Assertion Response Time Figure 10. RESET, RESET Deassertion Rev. D | Page 6 of 12 ADM705/ADM706/ADM707/ADM708 TA = 25C 5V VCC 4V 5V 0V 00088-018 RESET 2s/DIV Figure 11. ADM705/ADM707 RESET Response Time Rev. D | Page 7 of 12 ADM705/ADM706/ADM707/ADM708 CIRCUIT INFORMATION POWER-FAIL RESET OUTPUT RESET is an active-low output that provides a RESET signal to the microprocessor whenever the VCC input is below the reset threshold. An internal timer holds RESET low for 200 ms after the voltage on VCC rises above the threshold. This is intended as a power-on RESET signal for the microprocessor. It allows time for both the power supply and the microprocessor to stabilize after power-up. The RESET output is guaranteed to remain valid (low) with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shutdown condition as the power supply voltage ramps up. In addition to RESET, an active-high RESET output is also available on the ADM707/ADM708. This is the complement of RESET and is useful for processors requiring an active-high RESET signal. tWD tWD tWD WDO 00088-008 RESET EXTERNALLY TRIGGERED BY MR RESET tRS Figure 13. Watchdog Timing POWER-FAIL COMPARATOR tRS RESET 00088-007 MR EXTERNALLY DRIVEN LOW WDO Figure 12. RESET , MR , and WDO Timing WATCHDOG TIMER (ADM705/ADM706) The watchdog timer circuit may be used to monitor the activity of the microprocessor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the watchdog input (WDI) line. If this line is not toggled within the timeout period (1.6 sec), then the watchdog output (WDO) goes low. The WDO may be connected to a nonmaskable interrupt (NMI) on the processor; therefore, if the watchdog timer times out, then an interrupt is generated. The interrupt service routine should then be used to rectify the problem. The power-fail comparator is an independent comparator that may be used to monitor the input power supply. The comparator's inverting input is internally connected to a 1.25 V reference voltage. The noninverting input is available at the PFI input. This input may be used to monitor the input power supply via a resistive divider network. When the voltage on the PFI input drops below 1.25 V, the comparator output (PFO) goes low, indicating a power failure. For early warning of power failure, the comparator may be used to monitor the preregulator input simply by choosing an appropriate resistive divider network. The PFO output can be used to interrupt the processor so that a shutdown procedure is implemented before the power is lost. INPUT POWER If a RESET signal is required when a timeout occurs, then the WDO should be connected to the manual reset input (MR). Rev. D | Page 8 of 12 R1 R2 1.25V PFO POWER-FAIL PFI INPUT ADM705/ADM706/ ADM707/ADM708 Figure 14. Power-Fail Comparator POWER-FAIL OUTPUT 00088-009 VRT tRS MR The watchdog monitor can be deactivated by floating the watchdog input (WDI). The WDO can now be used as a low line output because it only goes low when VCC falls below the reset threshold. WDI The manual reset input (MR) allows other reset sources, such as a manual reset switch, to generate a processor reset. The input is effectively debounced by the timeout period (200 ms typical). The MR input is TTL/CMOS compatible, so it may also be driven by any logic reset output. VRT When VCC falls below the reset threshold, WDO is forced low whether or not the watchdog timer has timed out. Normally, this would generate an interrupt, but it is overridden by RESET going low. tWP MANUAL RESET (ADM707/ADM708) VCC The watchdog timer is cleared by either a high-to-low or by a low-to-high transition on WDI. It is also cleared by RESET going low; therefore, the watchdog timeout period begins after RESET goes high. ADM705/ADM706/ADM707/ADM708 R2 + R3 VH = 1.251 + R1 R2 x R3 1.25 VCC - 1.25 - VL = 1.25 + R1 RE R2 R1 + R2 VMID = 1.25 R2 Adding Hysteresis to the Power-Fail Comparator For increased noise immunity, hysteresis may be added to the power-fail comparator. Because the comparator circuit is noninverting, hysteresis can be added simply by connecting a resistor between the PFO output and the PFI input as shown in Figure 15. When PFO is low, Resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, Resistor R3 sources current into the PFI summing junction. This results in differing trip levels for the comparator. Further noise immunity may be achieved by connecting a capacitor between PFI and GND. 5V ADM663 VCC R1 1.25V - PFO + TO P NMI The ADM705/ADM706/ADM707/ADM708 are guaranteed to provide a valid reset level with VCC as low as 1 V; please refer to the Typical Performance Characteristics section. As VCC drops below 1 V, the internal transistor does not have sufficient drive to hold it on so the voltage on RESET is no longer held at 0 V. A pull-down resistor as shown in Figure 16 may be connected externally to hold the line low if required. PFI ADM705/ADM706/ ADM707/ADM708 ADM705/ADM706/ ADM707/ADM708 R2 RESET R3 GND R1 5V Figure 16. RESET Valid Below 1 V 0V 0V VL VIN VH 00088-010 PFO Figure 15. Adding Hysteresis to the Power-Fail Comparator Rev. D | Page 9 of 12 00088-0011 7V TO 15V INPUT POWER VALID RESET BELOW 1 V VCC ADM705/ADM706/ADM707/ADM708 APPLICATIONS A typical operating circuit is shown in Figure 17. The unregulated dc input supply is monitored using the PFI input via the resistive divider network. Resistors R1 and R2 should be selected so that when the supply voltage drops below the desired level (e.g., 8 V), the voltage on PFI drops below the 1.25 V threshold thereby generating an interrupt to the P. Monitoring the preregulator input gives additional time to execute an orderly shutdown procedure before power is lost. RESET ADM705/ ADM706 VX 5V P VCC RESET I/O LINE WDO If, in the event of inactivity on the WDI line, a system reset is required, the WDO output should be connected to the MR input as shown in Figure 18. WDI MR MR R2 Microprocessor activity is monitored using the WDI input. This is driven using an output line from the processor. The software routines should toggle this line at least once every 1.6 seconds. If a problem occurs and this line is not toggled, WDO goes low and a nonmaskable interrupt is generated. This interrupt routine may be used to clear the problem. RESET RESET P PFI Figure 17. Typical Application Circuit ADM705/ ADM706 RESET ADM705/ ADM706 R1 00088-020 GND PFO GND 00088-021 WDI MR It is possible to use the power-fail comparator to monitor a second supply as shown in Figure 19. The two sensing resistors, R1 and R2, are selected so that the voltage on PFI drops below 1.25 V at the minimum acceptable input supply. The PFO output may be connected to the MR input so that a RESET is generated when the supply drops out of tolerance. In this case, if either supply drops out of tolerance, then a RESET is generated. Figure 19. Monitoring 5 V and an Additional Supply, VX PS WITH BIDIRECTIONAL RESET In order to prevent contention for microprocessors with a bidirectional reset line, a current limiting resistor should be inserted between the ADM70x RESET output pin and the P reset pin. This limits the current to a safe level if there are conflicting output reset levels. A suitable resistor value is 4.7 k. If the reset output is required for other uses, it should be buffered as shown in Figure 20. 5V P I/O LINE BUFFERED RESET VCC WDO GND 00088-020 ADM70x RESET GND Figure 18. RESET from WDO P RESET GND Figure 20. Bidirectional I-O RESET Rev. D | Page 10 of 12 00088-022 RESET MONITORING ADDITIONAL SUPPLY LEVELS ADM705/ADM706/ADM707/ADM708 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) PIN 1 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001-BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 21. 8-Lead Plastic Dual-in-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 1 5 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2440) 4 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 0.50 (0.0196) x 45 0.25 (0.0099) 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 22. 8-Lead Small Outline Package [SOIC] (R-8) Dimensions shown in millimeters and (inches) Rev. D | Page 11 of 12 ADM705/ADM706/ADM707/ADM708 ORDERING GUIDE Model ADM705AN ADM705AR ADM705AR-REEL ADM705AR-REEL7 ADM705ARZ 1 ADM705ARZ-REEL1 ADM705ARZ-REEL71 ADM706AN ADM706ANZ1 ADM706AR ADM706AR-REEL ADM706AR-REEL7 ADM706ARZ1 ADM706ARZ-REEL1 ADM706ARZ-REEL71 ADM707AN ADM707ANZ1 ADM707AR ADM707AR-REEL ADM707ARZ1 ADM707ARZ-REEL1 ADM708AN ADM708ANZ1 ADM708AR ADM708AR-REEL ADM708ARZ1 ADM708ARZ-REEL1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] 8-Lead Standard Small Outline Package [SOIC] Z = Pb-free part. (c)2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00088-0-11/05(D) Rev. D | Page 12 of 12 Package Option N-8 R-8 R-8 R-8 R-8 R-8 R-8 N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 N-8 N-8 R-8 R-8 R-8 R-8 N-8 N-8 R-8 R-8 R-8 R-8