1
TN1510
Features
Low threshold (2.0V max.)
High input impedance
Low input capacitance (50pF typ.)
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Complementary N- and P-channel devices
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
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General Description
This low threshold enhancement-mode (normally-off) transis-
tor utilizes a vertical DMOS structure and Supertex’s well-
proven silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities of
bipolar transistors, and with the high input impedance and
positive temperature coeffi cient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally -induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input im-
pedance, low input capacitance, and fast switching speeds
are desired.
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BVDSS
Drain-to-gate voltage BVDGS
Gate-to-source voltage ±20V
Operating and storage temperature -55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Ordering Information
Device
Order Number BVDSS/ BVDGS
(V)
RDS(ON)
(max)
(Ω)
VGS(th)
(max)
(V)
ID(ON)
(min)
(A)
Die*
TN1510 TN1510NW 100 3.0 2.0 2.0
* Die in wafer form.
N-Channel Enhancement-Mode
Vertical DMOS FETs
2
TN1510
Sym Parameter Min Typ Max Units Conditions
Electrical Characteristics (TA = 25OC unless otherwise specifi ed)
Switching Waveforms and Test Circuit
BVDSS Drain-to-source breakdown voltage 100 - - V VGS= 0V, ID = 1.0mA
VGS(th) Gate threshold voltage 0.6 - 2.0 V VGS = VDS, ID = 0.5mA
∆VGS(th) Change in VGS(th) with temperature - -3.8 -5.0 mV/OCVGS = VDS, ID = 1.0mA
IGSS Gate body leakage - 0.1 100 nA VGS = ±20V, VDS = 0V
IDSS Zero gate voltage drain current --
10
μA
VGS =0V, VDS = Max Rating
VDS = 0.8 Max Rating
VGS = 0V, TA = 125OC
500
ID(ON) On-state drain current -1.4- AVGS = 5V, VDS = 25V
-3.4- VGS = 10V, VDS = 25V
RDS(ON) Static drain-to-source on-state resistance - 2.0 4.5 ΩVGS = 4.5V, ID = 250mA
-1.63.0 VGS = 10V, ID = 500mA
∆RDS(ON) Change in RDS(ON) with temperature - 0.6 1.1 %/OCVGS = 10V, ID = 0.5A
GFS Forward transconductance 225 400 - mmho VDS = 25V, ID = 500mA
CISS Input capacitance -5060
pF VGS = 0V, VDS = 25V,
f = 1.0MHz
COSS Common source output capacitance -2535
CRSS Reverse transfer capacitance - 4.0 8.05
td(ON) Turn-on delay time - 2.0 5.0
ns VDD = 25V, ID = 1.0A
RGEN = 25Ω
trRise time - 3.0 5.0
td(OFF) Turn-off delay time - 6.0 7.0
tfFall time - 3.0 6.0
VSD Diode forward voltage drop -1.01.5 VVGS = 0V, ISD = 0.5A
trr Reverse recovery time - 400 - ns VGS = 0V, ISD = 0.5A
Notes:
1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
90%
10%
90% 90%
10%
10%
PULSE
GENERATOR
V
DD
R
L
OUTPUT
D.U.T.
t(ON)
td(ON)
t(OFF)
td(OFF) tF
tr
INPUT
INPUT
OUTPUT
10V
V
DD
R
GEN
0V
0V
Doc.# DSFP-TN1510
A102907
